Ticket #1576: 1576.patch
| File 1576.patch, 49.6 KB (added by , 14 years ago) |
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headers/os/be_apps/NetPositive/NetPositive.h
1 /******************************************************************************* 2 / 3 / File: NetPositive.h 4 / 5 / Description: Defines all public APIs for communicating with NetPositive 6 / 7 / Copyright 1998-1999, Be Incorporated, All Rights Reserved 8 / 9 *******************************************************************************/ 10 1 /* 2 * Copyright 2010, Haiku Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 */ 11 5 #ifndef _NETPOSITIVE_H 12 6 #define _NETPOSITIVE_H 13 7 14 /*----------------------------------------------------------------*/15 /*----- message command constants -------------------------------*/16 8 9 /* message command constants */ 17 10 enum { 18 /* Can be sent to the NetPositive application, a window, or a replicant */19 /* view. Put the URL in a String field named be:url */20 11 B_NETPOSITIVE_OPEN_URL = 'NPOP', 21 22 /* Can be sent to a window or replicant view */23 12 B_NETPOSITIVE_BACK = 'NPBK', 24 13 B_NETPOSITIVE_FORWARD = 'NPFW', 25 14 B_NETPOSITIVE_HOME = 'NPHM', 26 15 B_NETPOSITIVE_RELOAD = 'NPRL', 27 B_NETPOSITIVE_STOP 16 B_NETPOSITIVE_STOP = 'NPST', 28 17 B_NETPOSITIVE_DOWN = 'NPDN', 29 18 B_NETPOSITIVE_UP = 'NPUP' 30 19 }; 31 32 /*----------------------------------------------------------------*/33 /*----- NetPositive-related MIME types --------------------------*/34 20 35 /* The MIME types for the NetPositive application and its bookmark files */ 21 22 /* NetPositive-related MIME types */ 36 23 #define B_NETPOSITIVE_APP_SIGNATURE "application/x-vnd.Be-NPOS" 37 24 #define B_NETPOSITIVE_BOOKMARK_SIGNATURE "application/x-vnd.Be-bookmark" 38 25 39 /* To set up your application to receive notification when the user */40 /* clicks on a specific type of URL (telnet URL's, for example), see the */41 /* details in TypeConstants.h. NetPositive will use external handlers */42 /* for all URL types except for http, https, file, netpositive, and */43 /* javascript, which it always handles internally. To maintain */44 /* compatibility with its previous behavior, if NetPositive does not */45 /* find a handler for mailto URL's, it will instead launch the handler */46 /* for "text/x-email". */47 26 48 /*----------------------------------------------------------------*/49 /*----------------------------------------------------------------*/50 51 27 #endif /* _NETPOSITIVE_H */ -
headers/os/drivers/atomizer.h
1 /******************************************************************************* 2 / 3 / File: atomizer.h 4 / 5 / Description: Kernel atomizer module API 6 / 7 / Copyright 1999, Be Incorporated, All Rights Reserved. 8 / 9 *******************************************************************************/ 1 /* 2 * Copyright 2010, Haiku Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 #ifndef _ATOMIZER_H 6 #define _ATOMIZER_H 10 7 11 #ifndef _ATOMIZER_MODULE_H_ 12 #define _ATOMIZER_MODULE_H_ 13 8 #include <SupportDefs.h> 14 9 #include <module.h> 15 10 16 #ifdef __cplusplus17 extern "C" {18 #endif19 11 20 /* 21 An atomizer is a software device that returns a unique token for a 22 null-terminated UTF8 string. 12 #define B_ATOMIZER_MODULE_NAME "generic/atomizer/v1" 13 #define B_SYSTEM_ATOMIZER_NAME "Haiku System Atomizer" 23 14 24 Each atomizer comprises a separate token space. The same string interned25 in two different atomizers will generate two distinct tokens.26 15 27 Atomizers and the tokens they generate are only guaranteed valid between 28 matched calls to get_module/put_module. 29 30 void * find_or_make_atomizer(const char *string) 31 Returns a token that identifies the named atomizer, creating a new 32 atomizer if the named atomizer does not exist. Pass null, a zero 33 length string, or the value B_SYSTEM_ATOMIZER_NAME for string will 34 return a pointer to the system atomizer. Returns (void *)(0) 35 if the atomizer could not be created (for whatever reason). A return 36 value of (void *)(-1) refers to the system atomizer. 37 38 status_t delete_atomizer(void *atomizer) 39 Delete the atomizer specified. Returns B_OK if successfull, B_ERROR 40 otherwise. An error return usually means that a race condition was 41 detected while destroying the atomizer. 42 43 void * atomize(void *atomizer, const char *string, int create) 44 Return the unique token for the specified string, creating a new token 45 if the string was not previously atomized and create is non-zero. If 46 atomizer is (void *)(-1), use the system atomizer (saving the step of 47 looking it up with find_or_make_atomizer(). Returns (const char *)(0) 48 if there were any errors detected: insufficient memory or a race 49 condition with someone deleting the atomizer. 50 51 const char * string_for_token(void *atomizer, void *atom) 52 Return a pointer to the string described by atom in the provided atomizer. 53 Returns (const char *)(0) if either the atomizer or the atom were invalid. 54 55 status_t get_next_atomizer_info(void **cookie, atomizer_info *info) 56 Returns info about the next atomizer in the list of atomizers by modifying 57 the contents of info. The pointer specified by *cookie should be set to 58 (void *)(0) to retrieve the first atomizer, and should not be modified 59 thereafter. Returns B_ERROR when there are no more atomizers. 60 Adding or deleting atomizers between calls to get_next_atomizer() results 61 in a safe but undefined behavior. 62 63 void * get_next_atom(void *atomizer, uint32 *cookie) 64 Returns the next atom interned in specified atomizer, *cookie 65 should be set to (uint32)(0) to get the first atom. Returns 66 (void *)(0) when there are no more atoms. Adding atoms between 67 calls to get_next_atom() may cause atoms to be skipped. 68 69 Atomizers are SMP-safe. Check return codes for errors! 70 71 */ 72 73 #define B_ATOMIZER_MODULE_NAME "generic/atomizer/v1" 74 #define B_SYSTEM_ATOMIZER_NAME "BeOS System Atomizer" 75 76 typedef struct { 77 void *atomizer; /* An opaque token representing the atomizer. */ 78 char name[B_OS_NAME_LENGTH]; /* The first B_OS_NAME_LENGTH bytes of the atomizer name, null terminated. */ 79 uint32 atom_count; /* The number of atoms currently interned in this atomizer. */ 16 typedef struct atomizer_info { 17 void* atomizer; 18 char name[B_OS_NAME_LENGTH]; 19 uint32 atom_count; 80 20 } atomizer_info; 81 21 82 typedef struct { 22 23 typedef struct atomizer_module_info { 83 24 module_info minfo; 84 const void * (*find_or_make_atomizer)(const char *string); 85 status_t (*delete_atomizer)(const void *atomizer); 86 const void * (*atomize)(const void *atomizer, const char *string, int create); 87 const char * (*string_for_token)(const void * atomizer, const void *atom); 88 status_t (*get_next_atomizer_info)(void **cookie, atomizer_info *info); 89 const void * (*get_next_atom)(const void *atomizer, uint32 *cookie); 25 const void* (*find_or_make_atomizer)(const char* string); 26 status_t (*delete_atomizer)(const void* atomizer); 27 const void* (*atomize) 28 (const void* atomizer, const char* string, int create); 29 const char* (*string_for_token) 30 (const void* atomizer, const void* atom); 31 status_t (*get_next_atomizer_info) 32 (void** cookie, atomizer_info* info); 33 const void* (*get_next_atom)(const void* atomizer, uint32* cookie); 90 34 } atomizer_module_info; 91 35 92 #ifdef __cplusplus93 }94 #endif95 36 96 #endif 97 37 #endif /* _ATOMIZER_H */ -
headers/os/drivers/PCI.h
1 /******************************************************************************* 2 / 3 / File: PCI.h 4 / 5 / Description: Interface to the PCI bus. 6 / For more information, see "PCI Local Bus Specification, Revision 2.1", 7 / PCI Special Interest Group, 1995. 8 / 9 / Copyright 1993-98, Be Incorporated, All Rights Reserved. 10 / 11 *******************************************************************************/ 12 13 1 /* 2 * Copyright 2010, Haiku Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 */ 14 5 #ifndef _PCI_H 15 6 #define _PCI_H 16 7 17 //#include <BeBuild.h> 18 //#include <SupportDefs.h>8 9 #include <SupportDefs.h> 19 10 #include <bus_manager.h> 20 11 21 #ifdef __cplusplus22 extern "C" {23 #endif24 12 25 26 /* ----- 27 pci device info 28 ----- */ 29 13 /* pci device info */ 14 typedef struct pci_info pci_info; 30 15 typedef struct pci_info { 31 u shortvendor_id; /* vendor id */32 u shortdevice_id; /* device id */16 uint16 vendor_id; /* vendor id */ 17 uint16 device_id; /* device id */ 33 18 uchar bus; /* bus number */ 34 19 uchar device; /* device number on bus */ 35 20 uchar function; /* function number in device */ … … 44 29 uchar reserved; /* filler, for alignment */ 45 30 union { 46 31 struct { 47 u longcardbus_cis; /* CardBus CIS pointer */48 u shortsubsystem_id; /* subsystem (add-in card) id */49 u short subsystem_vendor_id; /* subsystem (add-in card)vendor id */50 u long rom_base; /* rom base address, viewedfrom host */51 u longrom_base_pci; /* rom base addr, viewed from pci */52 u longrom_size; /* rom size */53 u long base_registers[6]; /* base registers, viewedfrom host */54 u long base_registers_pci[6]; /* base registers, viewedfrom pci */55 u long base_register_sizes[6]; /* size of what base regs point to*/32 uint32 cardbus_cis; /* CardBus CIS pointer */ 33 uint16 subsystem_id; /* subsystem (add-in card) id */ 34 uint16 subsystem_vendor_id; /* subsystem vendor id */ 35 uint32 rom_base; /* rom base addr, view from host */ 36 uint32 rom_base_pci; /* rom base addr, viewed from pci */ 37 uint32 rom_size; /* rom size */ 38 uint32 base_registers[6]; /* base registers, view from host */ 39 uint32 base_registers_pci[6]; /* base registers, view from pci */ 40 uint32 base_register_sizes[6]; /* size of what base regs point */ 56 41 uchar base_register_flags[6]; /* flags from base address fields */ 57 42 uchar interrupt_line; /* interrupt line */ 58 43 uchar interrupt_pin; /* interrupt pin */ … … 60 45 uchar max_latency; /* how often PCI access needed */ 61 46 } h0; 62 47 struct { 63 u long base_registers[2]; /* base registers, viewedfrom host */64 u long base_registers_pci[2]; /* base registers, viewedfrom pci */65 u long base_register_sizes[2]; /* size of what base regs point to*/48 uint32 base_registers[2]; /* base registers, view from host */ 49 uint32 base_registers_pci[2]; /* base registers, view from pci */ 50 uint32 base_register_sizes[2]; /* size of what base regs point */ 66 51 uchar base_register_flags[2]; /* flags from base address fields */ 67 52 uchar primary_bus; 68 53 uchar secondary_bus; … … 70 55 uchar secondary_latency; 71 56 uchar io_base; 72 57 uchar io_limit; 73 u shortsecondary_status;74 u shortmemory_base;75 u shortmemory_limit;76 u shortprefetchable_memory_base;77 u shortprefetchable_memory_limit;78 u longprefetchable_memory_base_upper32;79 u longprefetchable_memory_limit_upper32;80 u shortio_base_upper16;81 u shortio_limit_upper16;82 u long rom_base; /* rom base address, viewedfrom host */83 u long rom_base_pci; /* rom base addr, viewedfrom pci */58 uint16 secondary_status; 59 uint16 memory_base; 60 uint16 memory_limit; 61 uint16 prefetchable_memory_base; 62 uint16 prefetchable_memory_limit; 63 uint32 prefetchable_memory_base_upper32; 64 uint32 prefetchable_memory_limit_upper32; 65 uint16 io_base_upper16; 66 uint16 io_limit_upper16; 67 uint32 rom_base; /* rom base addr, view from host */ 68 uint32 rom_base_pci; /* rom base addr, view from pci */ 84 69 uchar interrupt_line; /* interrupt line */ 85 70 uchar interrupt_pin; /* interrupt pin */ 86 u shortbridge_control;87 u shortsubsystem_id; /* subsystem (add-in card) id */88 u short subsystem_vendor_id; /* subsystem (add-in card)vendor id */71 uint16 bridge_control; 72 uint16 subsystem_id; /* subsystem (add-in card) id */ 73 uint16 subsystem_vendor_id; /* subsystem vendor id */ 89 74 } h1; 90 75 struct { 91 u shortsubsystem_id; /* subsystem (add-in card) id */92 u short subsystem_vendor_id; /* subsystem (add-in card)vendor id */76 uint16 subsystem_id; /* subsystem (add-in card) id */ 77 uint16 subsystem_vendor_id; /* subsystem vendor id */ 93 78 94 79 #ifdef __HAIKU_PCI_BUS_MANAGER_TESTING 95 80 // for testing only, not final (do not use!): 96 uchar 97 uchar 98 uchar 99 uchar 100 u shortreserved;101 u longmemory_base;102 u longmemory_limit;103 u longmemory_base_upper32;104 u longmemory_limit_upper32;105 u longio_base;106 u longio_limit;107 u longio_base_upper32;108 u longio_limit_upper32;109 u shortsecondary_status;110 u shortbridge_control;81 uchar primary_bus; 82 uchar secondary_bus; 83 uchar subordinate_bus; 84 uchar secondary_latency; 85 uint16 reserved; 86 uint32 memory_base; 87 uint32 memory_limit; 88 uint32 memory_base_upper32; 89 uint32 memory_limit_upper32; 90 uint32 io_base; 91 uint32 io_limit; 92 uint32 io_base_upper32; 93 uint32 io_limit_upper32; 94 uint16 secondary_status; 95 uint16 bridge_control; 111 96 #endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */ 112 97 } h2; 113 98 } u; 114 } pci_info;99 }; 115 100 116 101 117 102 typedef struct pci_module_info pci_module_info; 118 119 struct pci_module_info { 103 typedef struct pci_module_info { 120 104 bus_manager_info binfo; 121 105 122 uint8 (*read_io_8) (int mapped_io_addr);123 void (*write_io_8) (int mapped_io_addr, uint8 value);124 uint16 (*read_io_16) (int mapped_io_addr);125 void (*write_io_16) (int mapped_io_addr, uint16 value);126 uint32 (*read_io_32) (int mapped_io_addr);127 void (*write_io_32) (int mapped_io_addr, uint32 value);106 uint8 (*read_io_8) (int32 mapped_io_addr); 107 void (*write_io_8) (int32 mapped_io_addr, uint8 value); 108 uint16 (*read_io_16) (int32 mapped_io_addr); 109 void (*write_io_16) (int32 mapped_io_addr, uint16 value); 110 uint32 (*read_io_32) (int32 mapped_io_addr); 111 void (*write_io_32) (int32 mapped_io_addr, uint32 value); 128 112 129 long(*get_nth_pci_info) (130 longindex, /* index into pci device table */131 pci_info *info /* caller-supplied buf ferfor info */113 int32 (*get_nth_pci_info) ( 114 int32 index, /* index into pci device table */ 115 pci_info *info /* caller-supplied buf for info */ 132 116 ); 133 117 uint32 (*read_pci_config) ( 134 118 uchar bus, /* bus number */ … … 146 130 uint32 value /* value to write */ 147 131 ); 148 132 149 void * (*ram_address) (const void *physical_address_in_system_memory); 133 void* (*ram_address) 134 (const void* physical_address_in_system_memory); 150 135 151 136 status_t (*find_pci_capability) ( 152 137 uchar bus, … … 156 141 uchar *offset 157 142 ); 158 143 status_t (*reserve_device) ( 159 uchar bus,160 uchar 161 uchar 162 const char *driver_name,163 void *cookie);144 uchar bus, 145 uchar device, 146 uchar function, 147 const char* driver_name, 148 void* cookie); 164 149 status_t (*unreserve_device) ( 165 uchar bus,166 uchar device,167 uchar function,168 const char *driver_name,169 void *cookie);150 uchar bus, 151 uchar device, 152 uchar function, 153 const char* driver_name, 154 void* cookie); 170 155 }; 171 156 172 157 #define B_PCI_MODULE_NAME "bus_managers/pci/v1" 173 158 174 /* ---175 offsets in PCI configuration space to the elements of the predefined176 header common to all header types177 --- */178 159 179 #define PCI_vendor_id 0x00 /* (2 byte) vendor id */ 180 #define PCI_device_id 0x02 /* (2 byte) device id */ 181 #define PCI_command 0x04 /* (2 byte) command */ 182 #define PCI_status 0x06 /* (2 byte) status */ 183 #define PCI_revision 0x08 /* (1 byte) revision id */ 184 #define PCI_class_api 0x09 /* (1 byte) specific register interface type */ 185 #define PCI_class_sub 0x0a /* (1 byte) specific device function */ 186 #define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */ 187 #define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */ 188 #define PCI_latency 0x0d /* (1 byte) latency timer */ 189 #define PCI_header_type 0x0e /* (1 byte) header type */ 190 #define PCI_bist 0x0f /* (1 byte) built-in self-test */ 160 /* offsets in PCI config space to the elements of the predefined header */ 161 /* offsets common to all header types */ 162 #define PCI_vendor_id 0x00 /* vendor id */ 163 #define PCI_device_id 0x02 /* device id */ 164 #define PCI_command 0x04 /* command */ 165 #define PCI_status 0x06 /* status */ 166 #define PCI_revision 0x08 /* revision id */ 167 #define PCI_class_api 0x09 /* specific register interface type */ 168 #define PCI_class_sub 0x0A /* specific device function */ 169 #define PCI_class_base 0x0B /* device type */ 170 #define PCI_line_size 0x0C /* cache line size in 32 bit words */ 171 #define PCI_latency 0x0D /* latency timer */ 172 #define PCI_header_type 0x0E /* header type */ 173 #define PCI_bist 0x0F /* built-in self-test */ 191 174 175 /* offsets common to header types 0x00 and 0x01 */ 176 #define PCI_base_registers 0x10 /* base registers */ 177 #define PCI_interrupt_line 0x3C /* interrupt line */ 178 #define PCI_interrupt_pin 0x3D /* interrupt pin */ 192 179 180 /* offsets common to header type 0x00 */ 181 #define PCI_cardbus_cis 0x28 /* CardBus CIS pointer */ 182 #define PCI_subsystem_vendor_id 0x2C /* subsystem vendor id */ 183 #define PCI_subsystem_id 0x2E /* subsystem id */ 184 #define PCI_rom_base 0x30 /* expansion rom base address */ 185 #define PCI_capabilities_ptr 0x34 /* point to start of cap list */ 186 #define PCI_min_grant 0x3E /* burst period @ 33 Mhz */ 187 #define PCI_max_latency 0x3F /* how often need PCI access */ 193 188 194 /* --- 195 offsets in PCI configuration space to the elements of the predefined 196 header common to header types 0x00 and 0x01 197 --- */ 198 #define PCI_base_registers 0x10 /* base registers (size varies) */ 199 #define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */ 200 #define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */ 201 202 203 204 /* --- 205 offsets in PCI configuration space to the elements of header type 0x00 206 --- */ 207 208 #define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */ 209 #define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */ 210 #define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */ 211 #define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */ 212 #define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */ 213 #define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */ 214 #define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */ 215 216 217 /* --- 218 offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge) 219 --- */ 220 221 #define PCI_primary_bus 0x18 /* (1 byte) */ 222 #define PCI_secondary_bus 0x19 /* (1 byte) */ 223 #define PCI_subordinate_bus 0x1A /* (1 byte) */ 224 #define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */ 225 #define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/ 226 #define PCI_io_limit 0x1D /* (1 byte) */ 227 #define PCI_secondary_status 0x1E /* (2 bytes) */ 228 #define PCI_memory_base 0x20 /* (2 bytes) */ 229 #define PCI_memory_limit 0x22 /* (2 bytes) */ 230 #define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */ 231 #define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */ 189 /* offsets common to the elements of header type 0x01 (PCI-to-PCI bridge) */ 190 #define PCI_primary_bus 0x18 191 #define PCI_secondary_bus 0x19 192 #define PCI_subordinate_bus 0x1A 193 #define PCI_secondary_latency 0x1B 194 #define PCI_io_base 0x1C 195 #define PCI_io_limit 0x1D 196 #define PCI_secondary_status 0x1E 197 #define PCI_memory_base 0x20 198 #define PCI_memory_limit 0x22 199 #define PCI_prefetchable_memory_base 0x24 200 #define PCI_prefetchable_memory_limit 0x26 232 201 #define PCI_prefetchable_memory_base_upper32 0x28 233 202 #define PCI_prefetchable_memory_limit_upper32 0x2C 234 #define PCI_io_base_upper16 0x30 /* (2 bytes) */235 #define PCI_io_limit_upper16 0x32 /* (2 bytes) */236 #define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */237 #define PCI_sub_device_id_1 0x36 /* (2 bytes) */203 #define PCI_io_base_upper16 0x30 204 #define PCI_io_limit_upper16 0x32 205 #define PCI_sub_vendor_id_1 0x34 206 #define PCI_sub_device_id_1 0x36 238 207 #define PCI_bridge_rom_base 0x38 239 #define PCI_bridge_control 0x3E /* (2 bytes) */208 #define PCI_bridge_control 0x3E 240 209 241 242 210 /* PCI type 2 header offsets */ 243 #define PCI_capabilities_ptr_2 0x14 /* (1 byte) */ 244 #define PCI_secondary_status_2 0x16 /* (2 bytes) */ 245 #define PCI_primary_bus_2 0x18 /* (1 byte) */ 246 #define PCI_secondary_bus_2 0x19 /* (1 byte) */ 247 #define PCI_subordinate_bus_2 0x1A /* (1 byte) */ 248 #define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */ 249 #define PCI_memory_base0_2 0x1C /* (4 bytes) */ 250 #define PCI_memory_limit0_2 0x20 /* (4 bytes) */ 251 #define PCI_memory_base1_2 0x24 /* (4 bytes) */ 252 #define PCI_memory_limit1_2 0x28 /* (4 bytes) */ 253 #define PCI_io_base0_2 0x2c /* (4 bytes) */ 254 #define PCI_io_limit0_2 0x30 /* (4 bytes) */ 255 #define PCI_io_base1_2 0x34 /* (4 bytes) */ 256 #define PCI_io_limit1_2 0x38 /* (4 bytes) */ 257 #define PCI_bridge_control_2 0x3E /* (2 bytes) */ 211 #define PCI_capabilities_ptr_2 0x14 212 #define PCI_secondary_status_2 0x16 213 #define PCI_primary_bus_2 0x18 214 #define PCI_secondary_bus_2 0x19 215 #define PCI_subordinate_bus_2 0x1A 216 #define PCI_secondary_latency_2 0x1B 217 #define PCI_memory_base0_2 0x1C 218 #define PCI_memory_limit0_2 0x20 219 #define PCI_memory_base1_2 0x24 220 #define PCI_memory_limit1_2 0x28 221 #define PCI_io_base0_2 0x2C 222 #define PCI_io_limit0_2 0x30 223 #define PCI_io_base1_2 0x34 224 #define PCI_io_limit1_2 0x38 225 #define PCI_bridge_control_2 0x3E 226 #define PCI_sub_vendor_id_2 0x40 227 #define PCI_sub_device_id_2 0x42 228 #define PCI_card_interface_2 0x44 258 229 259 #define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */260 #define PCI_sub_device_id_2 0x42 /* (2 bytes) */261 230 262 #define PCI_card_interface_2 0x44 /* ?? */ 231 /* values for the class_base field in the common header */ 232 #define PCI_early 0x00 233 #define PCI_mass_storage 0x01 234 #define PCI_network 0x02 235 #define PCI_display 0x03 236 #define PCI_multimedia 0x04 237 #define PCI_memory 0x05 238 #define PCI_bridge 0x06 239 #define PCI_simple_communications 0x07 240 #define PCI_base_peripheral 0x08 241 #define PCI_input 0x09 242 #define PCI_docking_station 0x0A 243 #define PCI_processor 0x0B 244 #define PCI_serial_bus 0x0C 245 #define PCI_wireless 0x0D 246 #define PCI_intelligent_io 0x0E 247 #define PCI_satellite_communications 0x0F 248 #define PCI_encryption_decryption 0x10 249 #define PCI_data_acquisition 0x11 250 #define PCI_undefined 0xFF 263 251 264 /* ---265 values for the class_base field in the common header 266 --- */ 252 /* values for the class_sub field for class_base = 0x00 (early) */ 253 #define PCI_early_not_vga 0x00 254 #define PCI_early_vga 0x01 267 255 268 #define PCI_early 0x00 /* built before class codes defined */ 269 #define PCI_mass_storage 0x01 /* mass storage_controller */ 270 #define PCI_network 0x02 /* network controller */ 271 #define PCI_display 0x03 /* display controller */ 272 #define PCI_multimedia 0x04 /* multimedia device */ 273 #define PCI_memory 0x05 /* memory controller */ 274 #define PCI_bridge 0x06 /* bridge controller */ 275 #define PCI_simple_communications 0x07 /* simple communications controller */ 276 #define PCI_base_peripheral 0x08 /* base system peripherals */ 277 #define PCI_input 0x09 /* input devices */ 278 #define PCI_docking_station 0x0a /* docking stations */ 279 #define PCI_processor 0x0b /* processors */ 280 #define PCI_serial_bus 0x0c /* serial bus controllers */ 281 #define PCI_wireless 0x0d /* wireless controllers */ 282 #define PCI_intelligent_io 0x0e 283 #define PCI_satellite_communications 0x0f 284 #define PCI_encryption_decryption 0x10 285 #define PCI_data_acquisition 0x11 256 /* values for the class_sub field for class_base = 0x01 (mass storage) */ 257 #define PCI_scsi 0x00 258 #define PCI_ide 0x01 259 #define PCI_floppy 0x02 260 #define PCI_ipi 0x03 261 #define PCI_raid 0x04 262 #define PCI_ata 0x05 263 #define PCI_sata 0x06 264 #define PCI_sas 0x07 265 #define PCI_mass_storage_other 0x80 286 266 287 #define PCI_undefined 0xFF /* not in any defined class */ 267 /* values of the class_api field for class_base = 0x01, class_sub = 0x06 */ 268 #define PCI_sata_other 0x00 269 #define PCI_sata_ahci 0x01 288 270 271 /* values for the class_sub field for class_base = 0x02 (network) */ 272 #define PCI_ethernet 0x00 273 #define PCI_token_ring 0x01 274 #define PCI_fddi 0x02 275 #define PCI_atm 0x03 276 #define PCI_isdn 0x04 277 #define PCI_network_other 0x80 289 278 290 /* --- 291 values for the class_sub field for class_base = 0x00 (built before 292 class codes were defined) 293 --- */ 279 /* values for the class_sub field for class_base = 0x03 (display) */ 280 #define PCI_vga 0x00 281 #define PCI_xga 0x01 282 #define PCI_3d 0x02 283 #define PCI_display_other 0x80 294 284 295 #define PCI_early_not_vga 0x00 /* all except vga */ 296 #define PCI_early_vga 0x01 /* vga devices */ 285 /* values for the class_sub field for class_base = 0x04 (multimedia device) */ 286 #define PCI_video 0x00 287 #define PCI_audio 0x01 288 #define PCI_telephony 0x02 289 #define PCI_hd_audio 0x03 290 #define PCI_multimedia_other 0x80 297 291 292 /* values for the class_sub field for class_base = 0x05 (memory) */ 293 #define PCI_ram 0x00 294 #define PCI_flash 0x01 295 #define PCI_memory_other 0x80 298 296 299 /* --- 300 values for the class_sub field for class_base = 0x01 (mass storage) 301 --- */ 297 /* values for the class_sub field for class_base = 0x06 (bridge) */ 298 #define PCI_host 0x00 299 #define PCI_isa 0x01 300 #define PCI_eisa 0x02 301 #define PCI_microchannel 0x03 302 #define PCI_pci 0x04 303 #define PCI_pcmcia 0x05 304 #define PCI_nubus 0x06 305 #define PCI_cardbus 0x07 306 #define PCI_raceway 0x08 307 #define PCI_bridge_transparent 0x09 308 #define PCI_bridge_infiniband 0x0A 309 #define PCI_bridge_other 0x80 302 310 303 #define PCI_scsi 0x00 /* SCSI controller */ 304 #define PCI_ide 0x01 /* IDE controller */ 305 #define PCI_floppy 0x02 /* floppy disk controller */ 306 #define PCI_ipi 0x03 /* IPI bus controller */ 307 #define PCI_raid 0x04 /* RAID controller */ 308 #define PCI_ata 0x05 /* ATA controller with ADMA interface */ 309 #define PCI_sata 0x06 /* Serial ATA controller */ 310 #define PCI_sas 0x07 /* Serial Attached SCSI controller */ 311 #define PCI_mass_storage_other 0x80 /* other mass storage controller */ 311 /* values for the class_sub field for class_base = 0x07 (simple comm ctrlers) */ 312 #define PCI_serial 0x00 313 #define PCI_parallel 0x01 314 #define PCI_multiport_serial 0x02 315 #define PCI_modem 0x03 316 #define PCI_simple_communications_other 0x80 312 317 313 /* --- 314 values of the class_api field for 315 class_base = 0x01 (mass storage) 316 class_sub = 0x06 (Serial ATA controller) 317 --- */ 318 /* values of the class_api field for class_base = 0x07 and class_sub = 0x00 */ 319 #define PCI_serial_xt 0x00 320 #define PCI_serial_16450 0x01 321 #define PCI_serial_16550 0x02 318 322 319 #define PCI_sata_other 0x00 /* vendor specific interface */ 320 #define PCI_sata_ahci 0x01 /* AHCI interface */ 323 /* values of the class_api field for class_base = 0x07 and class_sub = 0x01 */ 324 #define PCI_parallel_simple 0x00 325 #define PCI_parallel_bidirectional 0x01 326 #define PCI_parallel_ecp 0x02 321 327 322 328 323 /* --- 324 values for the class_sub field for class_base = 0x02 (network) 325 --- */ 329 /* values for the class_sub field for class_base = 0x08 (system peripherals) */ 330 #define PCI_pic 0x00 331 #define PCI_dma 0x01 332 #define PCI_timer 0x02 333 #define PCI_rtc 0x03 334 #define PCI_generic_hot_plug 0x04 335 #define PCI_system_peripheral_other 0x80 326 336 327 #define PCI_ethernet 0x00 /* Ethernet controller */ 328 #define PCI_token_ring 0x01 /* Token Ring controller */ 329 #define PCI_fddi 0x02 /* FDDI controller */ 330 #define PCI_atm 0x03 /* ATM controller */ 331 #define PCI_isdn 0x04 /* ISDN controller */ 332 #define PCI_network_other 0x80 /* other network controller */ 337 /* values of the class_api field for class_base = 0x08 and class_sub = 0x00 */ 338 #define PCI_pic_8259 0x00 339 #define PCI_pic_isa 0x01 340 #define PCI_pic_eisa 0x02 333 341 342 /* values of the class_api field for class_base = 0x08 and class_sub = 0x01 */ 343 #define PCI_dma_8237 0x00 344 #define PCI_dma_isa 0x01 345 #define PCI_dma_eisa 0x02 334 346 335 /* --- 336 values for the class_sub field for class_base = 0x03 (display) 337 --- */ 347 /* values of the class_api field for class_base = 0x08 and class_sub = 0x02 */ 348 #define PCI_timer_8254 0x00 349 #define PCI_timer_isa 0x01 350 #define PCI_timer_eisa 0x02 338 351 339 #define PCI_vga 0x00 /* VGA controller */ 340 #define PCI_xga 0x01 /* XGA controller */ 341 #define PCI_3d 0x02 /* 3d controller */ 342 #define PCI_display_other 0x80 /* other display controller */ 352 /* values of the class_api field for class_base = 0x08 and class_sub = 0x03 */ 353 #define PCI_rtc_generic 0x00 354 #define PCI_rtc_isa 0x01 343 355 356 /* values for the class_sub field for class_base = 0x09 (input devices) */ 357 #define PCI_keyboard 0x00 358 #define PCI_pen 0x01 359 #define PCI_mouse 0x02 360 #define PCI_scanner 0x03 361 #define PCI_gameport 0x04 362 #define PCI_input_other 0x80 344 363 345 /* ---346 values for the class_sub field for class_base = 0x04 (multimedia device) 347 --- */ 364 /* values for the class_sub field for class_base = 0x0A (docking stations) */ 365 #define PCI_docking_generic 0x00 366 #define PCI_docking_other 0x80 348 367 349 #define PCI_video 0x00 /* video */ 350 #define PCI_audio 0x01 /* audio */ 351 #define PCI_telephony 0x02 /* computer telephony device */ 352 #define PCI_hd_audio 0x03 /* HD audio */ 353 #define PCI_multimedia_other 0x80 /* other multimedia device */ 368 /* values for the class_sub field for class_base = 0x0B (processor) */ 369 #define PCI_386 0x00 370 #define PCI_486 0x01 371 #define PCI_pentium 0x02 372 #define PCI_alpha 0x10 373 #define PCI_PowerPC 0x20 374 #define PCI_mips 0x30 375 #define PCI_coprocessor 0x40 354 376 355 356 /* --- 357 values for the class_sub field for class_base = 0x05 (memory) 358 --- */ 359 360 #define PCI_ram 0x00 /* RAM */ 361 #define PCI_flash 0x01 /* flash */ 362 #define PCI_memory_other 0x80 /* other memory controller */ 363 364 365 /* --- 366 values for the class_sub field for class_base = 0x06 (bridge) 367 --- */ 368 369 #define PCI_host 0x00 /* host bridge */ 370 #define PCI_isa 0x01 /* ISA bridge */ 371 #define PCI_eisa 0x02 /* EISA bridge */ 372 #define PCI_microchannel 0x03 /* MicroChannel bridge */ 373 #define PCI_pci 0x04 /* PCI-to-PCI bridge */ 374 #define PCI_pcmcia 0x05 /* PCMCIA bridge */ 375 #define PCI_nubus 0x06 /* NuBus bridge */ 376 #define PCI_cardbus 0x07 /* CardBus bridge */ 377 #define PCI_raceway 0x08 /* RACEway bridge */ 378 #define PCI_bridge_transparent 0x09 /* PCI transparent */ 379 #define PCI_bridge_infiniband 0x0a /* Infiniband */ 380 #define PCI_bridge_other 0x80 /* other bridge device */ 381 382 383 /* --- 384 values for the class_sub field for class_base = 0x07 (simple 385 communications controllers) 386 --- */ 387 388 #define PCI_serial 0x00 /* serial port controller */ 389 #define PCI_parallel 0x01 /* parallel port */ 390 #define PCI_multiport_serial 0x02 /* multiport serial controller */ 391 #define PCI_modem 0x03 /* modem */ 392 #define PCI_simple_communications_other 0x80 /* other communications device */ 393 394 /* --- 395 values of the class_api field for 396 class_base = 0x07 (simple communications), and 397 class_sub = 0x00 (serial port controller) 398 --- */ 399 400 #define PCI_serial_xt 0x00 /* XT-compatible serial controller */ 401 #define PCI_serial_16450 0x01 /* 16450-compatible serial controller */ 402 #define PCI_serial_16550 0x02 /* 16550-compatible serial controller */ 403 404 405 /* --- 406 values of the class_api field for 407 class_base = 0x07 (simple communications), and 408 class_sub = 0x01 (parallel port) 409 --- */ 410 411 #define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */ 412 #define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */ 413 #define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */ 414 415 416 /* --- 417 values for the class_sub field for class_base = 0x08 (generic 418 system peripherals) 419 --- */ 420 421 #define PCI_pic 0x00 /* peripheral interrupt controller */ 422 #define PCI_dma 0x01 /* dma controller */ 423 #define PCI_timer 0x02 /* timers */ 424 #define PCI_rtc 0x03 /* real time clock */ 425 #define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */ 426 #define PCI_system_peripheral_other 0x80 /* other generic system peripheral */ 427 428 /* --- 429 values of the class_api field for 430 class_base = 0x08 (generic system peripherals) 431 class_sub = 0x00 (peripheral interrupt controller) 432 --- */ 433 434 #define PCI_pic_8259 0x00 /* generic 8259 */ 435 #define PCI_pic_isa 0x01 /* ISA pic */ 436 #define PCI_pic_eisa 0x02 /* EISA pic */ 437 438 /* --- 439 values of the class_api field for 440 class_base = 0x08 (generic system peripherals) 441 class_sub = 0x01 (dma controller) 442 --- */ 443 444 #define PCI_dma_8237 0x00 /* generic 8237 */ 445 #define PCI_dma_isa 0x01 /* ISA dma */ 446 #define PCI_dma_eisa 0x02 /* EISA dma */ 447 448 /* --- 449 values of the class_api field for 450 class_base = 0x08 (generic system peripherals) 451 class_sub = 0x02 (timer) 452 --- */ 453 454 #define PCI_timer_8254 0x00 /* generic 8254 */ 455 #define PCI_timer_isa 0x01 /* ISA timer */ 456 #define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */ 457 458 459 /* --- 460 values of the class_api field for 461 class_base = 0x08 (generic system peripherals) 462 class_sub = 0x03 (real time clock 463 --- */ 464 465 #define PCI_rtc_generic 0x00 /* generic real time clock */ 466 #define PCI_rtc_isa 0x01 /* ISA real time clock */ 467 468 469 /* --- 470 values for the class_sub field for class_base = 0x09 (input devices) 471 --- */ 472 473 #define PCI_keyboard 0x00 /* keyboard controller */ 474 #define PCI_pen 0x01 /* pen */ 475 #define PCI_mouse 0x02 /* mouse controller */ 476 #define PCI_scanner 0x03 /* scanner controller */ 477 #define PCI_gameport 0x04 /* gameport controller */ 478 #define PCI_input_other 0x80 /* other input controller */ 479 480 481 /* --- 482 values for the class_sub field for class_base = 0x0a (docking stations) 483 --- */ 484 485 #define PCI_docking_generic 0x00 /* generic docking station */ 486 #define PCI_docking_other 0x80 /* other docking stations */ 487 488 /* --- 489 values for the class_sub field for class_base = 0x0b (processor) 490 --- */ 491 492 #define PCI_386 0x00 /* 386 */ 493 #define PCI_486 0x01 /* 486 */ 494 #define PCI_pentium 0x02 /* Pentium */ 495 #define PCI_alpha 0x10 /* Alpha */ 496 #define PCI_PowerPC 0x20 /* PowerPC */ 497 #define PCI_mips 0x30 /* MIPS */ 498 #define PCI_coprocessor 0x40 /* co-processor */ 499 500 /* --- 501 values for the class_sub field for class_base = 0x0c (serial bus 502 controller) 503 --- */ 504 505 #define PCI_firewire 0x00 /* FireWire (IEEE 1394) */ 506 #define PCI_access 0x01 /* ACCESS bus */ 507 #define PCI_ssa 0x02 /* SSA */ 508 #define PCI_usb 0x03 /* Universal Serial Bus */ 509 #define PCI_fibre_channel 0x04 /* Fibre channel */ 377 /* values for the class_sub field for class_base = 0x0C (serial bus ctrlr) */ 378 #define PCI_firewire 0x00 379 #define PCI_access 0x01 380 #define PCI_ssa 0x02 381 #define PCI_usb 0x03 382 #define PCI_fibre_channel 0x04 510 383 #define PCI_smbus 0x05 511 #define PCI_infiniband 384 #define PCI_infiniband 0x06 512 385 #define PCI_ipmi 0x07 513 386 #define PCI_sercos 0x08 514 387 #define PCI_canbus 0x09 515 388 516 /* --- 517 values of the class_api field for 518 class_base = 0x0c ( serial bus controller ) 519 class_sub = 0x03 ( Universal Serial Bus ) 520 --- */ 389 /* values of the class_api field for class_base = 0x0C and class_sub = 0x03 */ 390 #define PCI_usb_uhci 0x00 391 #define PCI_usb_ohci 0x10 392 #define PCI_usb_ehci 0x20 521 393 522 #define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */ 523 #define PCI_usb_ohci 0x10 /* Open Host Controller Interface */ 524 #define PCI_usb_ehci 0x20 /* Enhanced Host Controller Interface */ 525 526 /* --- 527 values for the class_sub field for class_base = 0x0d (wireless controller) 528 --- */ 394 /* values for the class_sub field for class_base = 0x0d (wireless controller) */ 529 395 #define PCI_wireless_irda 0x00 530 #define PCI_wireless_consumer_ir 396 #define PCI_wireless_consumer_ir 0x01 531 397 #define PCI_wireless_rf 0x02 532 #define PCI_wireless_bluetooth 533 #define PCI_wireless_broadband 398 #define PCI_wireless_bluetooth 0x03 399 #define PCI_wireless_broadband 0x04 534 400 #define PCI_wireless_80211A 0x10 535 401 #define PCI_wireless_80211B 0x20 536 402 #define PCI_wireless_other 0x80 537 403 538 /* ---539 masks for command register bits540 --- */541 404 542 #define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */ 543 #define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */ 544 #define PCI_command_master 0x004 /* 1/0 pci master en/disabled */ 545 #define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */ 546 #define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */ 547 #define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */ 548 #define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */ 549 #define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */ 550 #define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */ 551 #define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */ 552 #define PCI_command_int_disable 0x400 /* 1/0 interrupt generation dis/enabled */ 405 /* masks for command register bits */ 406 #define PCI_command_io 0x001 407 #define PCI_command_memory 0x002 408 #define PCI_command_master 0x004 409 #define PCI_command_special 0x008 410 #define PCI_command_mwi 0x010 411 #define PCI_command_vga_snoop 0x020 412 #define PCI_command_parity 0x040 413 #define PCI_command_address_step 0x080 414 #define PCI_command_serr 0x100 415 #define PCI_command_fastback 0x200 416 #define PCI_command_int_disable 0x400 553 417 554 418 555 /* --- 556 masks for status register bits 557 --- */ 419 /* masks for status register bits */ 420 #define PCI_status_capabilities 0x0010 421 #define PCI_status_66_MHz_capable 0x0020 422 #define PCI_status_udf_supported 0x0040 423 #define PCI_status_fastback 0x0080 424 #define PCI_status_parity_signalled 0x0100 425 #define PCI_status_devsel 0x0600 426 #define PCI_status_target_abort_signalled 0x0800 427 #define PCI_status_target_abort_received 0x1000 428 #define PCI_status_master_abort_received 0x2000 429 #define PCI_status_serr_signalled 0x4000 430 #define PCI_status_parity_error_detected 0x8000 558 431 559 #define PCI_status_capabilities 0x0010 /* capabilities list */560 #define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */561 #define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */562 #define PCI_status_fastback 0x0080 /* fast back-to-back capable */563 #define PCI_status_parity_signalled 0x0100 /* parity error signalled */564 #define PCI_status_devsel 0x0600 /* devsel timing (see below) */565 #define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */566 #define PCI_status_target_abort_received 0x1000 /* received a target abort */567 #define PCI_status_master_abort_received 0x2000 /* received a master abort */568 #define PCI_status_serr_signalled 0x4000 /* signalled SERR# */569 #define PCI_status_parity_error_detected 0x8000 /* parity error detected */570 432 433 /* masks for devsel field in status register */ 434 #define PCI_status_devsel_fast 0x0000 435 #define PCI_status_devsel_medium 0x0200 436 #define PCI_status_devsel_slow 0x0400 571 437 572 /* ---573 masks for devsel field in status register574 --- */575 438 576 #define PCI_status_devsel_fast 0x0000 /* fast*/577 #define PCI_ status_devsel_medium 0x0200 /* medium */578 #define PCI_ status_devsel_slow 0x0400 /* slow */439 /* masks for header type register */ 440 #define PCI_header_type_mask 0x7F 441 #define PCI_multifunction 0x80 579 442 580 443 581 /* --- 582 masks for header type register 583 --- */ 584 585 #define PCI_header_type_mask 0x7F /* header type field */ 586 #define PCI_multifunction 0x80 /* multifunction device flag */ 587 588 589 /** types of PCI header */ 590 444 /* types of PCI header */ 591 445 #define PCI_header_type_generic 0x00 592 446 #define PCI_header_type_PCI_to_PCI_bridge 0x01 593 #define PCI_header_type_cardbus 447 #define PCI_header_type_cardbus 0x02 594 448 595 449 596 /* --- 597 masks for built in self test (bist) register bits 598 --- */ 450 /* masks for built in self test (bist) register bits */ 451 #define PCI_bist_code 0x0F 452 #define PCI_bist_start 0x40 453 #define PCI_bist_capable 0x80 599 454 600 #define PCI_bist_code 0x0F /* self-test completion code, 0 = success */601 #define PCI_bist_start 0x40 /* 1 = start self-test */602 #define PCI_bist_capable 0x80 /* 1 = self-test capable */603 455 456 /* masks for flags in the various base address registers */ 457 #define PCI_address_space 0x01 458 #define PCI_register_start 0x10 459 #define PCI_register_end 0x24 460 #define PCI_register_ppb_end 0x18 461 #define PCI_register_pcb_end 0x14 604 462 605 /** masks for flags in the various base address registers */606 463 607 #define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */ 608 #define PCI_register_start 0x10 609 #define PCI_register_end 0x24 610 #define PCI_register_ppb_end 0x18 611 #define PCI_register_pcb_end 0x14 464 /* masks for flags in memory space base address registers */ 465 #define PCI_address_type_32 0x00 466 #define PCI_address_type_32_low 0x02 467 #define PCI_address_type_64 0x04 468 #define PCI_address_type 0x06 469 #define PCI_address_prefetchable 0x08 470 #define PCI_address_memory_32_mask 0xFFFFFFF0 612 471 613 /** masks for flags in memory space base address registers */614 472 615 #define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */ 616 #define PCI_address_type_32_low 0x02 /* locate below 1 Meg */ 617 #define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */ 618 #define PCI_address_type 0x06 /* type (see below) */ 619 #define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */ 473 /* masks for flags in i/o space base address registers */ 474 #define PCI_address_io_mask 0xFFFFFFFC 620 475 621 #define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */622 476 477 /* masks for flags in expansion rom base address registers */ 478 #define PCI_rom_enable 0x00000001 479 #define PCI_rom_address_mask 0xFFFFF800 623 480 624 /* ---625 masks for flags in i/o space base address registers626 --- */627 481 628 #define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */ 482 /* PCI interrupt pin values */ 483 #define PCI_pin_mask 0x07 484 #define PCI_pin_none 0x00 485 #define PCI_pin_a 0x01 486 #define PCI_pin_b 0x02 487 #define PCI_pin_c 0x03 488 #define PCI_pin_d 0x04 489 #define PCI_pin_max 0x04 629 490 630 491 631 /* --- 632 masks for flags in expansion rom base address registers 633 --- */ 492 /* PCI Capability Codes */ 493 #define PCI_cap_id_reserved 0x00 494 #define PCI_cap_id_pm 0x01 495 #define PCI_cap_id_agp 0x02 496 #define PCI_cap_id_vpd 0x03 497 #define PCI_cap_id_slotid 0x04 498 #define PCI_cap_id_msi 0x05 499 #define PCI_cap_id_chswp 0x06 500 #define PCI_cap_id_pcix 0x07 501 #define PCI_cap_id_ldt 0x08 502 #define PCI_cap_id_vendspec 0x09 503 #define PCI_cap_id_debugport 0x0a 504 #define PCI_cap_id_cpci_rsrcctl 0x0b 505 #define PCI_cap_id_hotplug 0x0c 506 #define PCI_cap_id_subvendor 0x0d 507 #define PCI_cap_id_agp8x 0x0e 508 #define PCI_cap_id_secure_dev 0x0f 509 #define PCI_cap_id_pcie 0x10 510 #define PCI_cap_id_msix 0x11 511 #define PCI_cap_id_sata 0x12 512 #define PCI_cap_id_pciaf 0x13 634 513 635 #define PCI_rom_enable 0x00000001 /* 1 = expansion rom decode enabled */636 #define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */637 514 638 /** PCI interrupt pin values */ 639 #define PCI_pin_mask 0x07 640 #define PCI_pin_none 0x00 641 #define PCI_pin_a 0x01 642 #define PCI_pin_b 0x02 643 #define PCI_pin_c 0x03 644 #define PCI_pin_d 0x04 645 #define PCI_pin_max 0x04 515 /* Power Management Control Status Register settings */ 516 #define PCI_pm_mask 0x03 517 #define PCI_pm_ctrl 0x02 518 #define PCI_pm_d1supp 0x0200 519 #define PCI_pm_d2supp 0x0400 520 #define PCI_pm_status 0x04 521 #define PCI_pm_state_d0 0x00 522 #define PCI_pm_state_d1 0x01 523 #define PCI_pm_state_d2 0x02 524 #define PCI_pm_state_d3 0x03 646 525 647 /** PCI Capability Codes */648 #define PCI_cap_id_reserved 0x00649 #define PCI_cap_id_pm 0x01 /* Power management */650 #define PCI_cap_id_agp 0x02 /* AGP */651 #define PCI_cap_id_vpd 0x03 /* Vital product data */652 #define PCI_cap_id_slotid 0x04 /* Slot ID */653 #define PCI_cap_id_msi 0x05 /* Message signalled interrupt */654 #define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */655 #define PCI_cap_id_pcix 0x07 /* PCI-X */656 #define PCI_cap_id_ldt 0x08657 #define PCI_cap_id_vendspec 0x09658 #define PCI_cap_id_debugport 0x0a659 #define PCI_cap_id_cpci_rsrcctl 0x0b660 #define PCI_cap_id_hotplug 0x0c661 #define PCI_cap_id_subvendor 0x0d662 #define PCI_cap_id_agp8x 0x0e663 #define PCI_cap_id_secure_dev 0x0f664 #define PCI_cap_id_pcie 0x10 /* PCIe (PCI express) */665 #define PCI_cap_id_msix 0x11 /* MSI-X */666 #define PCI_cap_id_sata 0x12 /* Serial ATA Capability */667 #define PCI_cap_id_pciaf 0x13 /* PCI Advanced Features */668 526 669 /** Power Management Control Status Register settings */670 #define PCI_pm_mask 0x03671 #define PCI_pm_ctrl 0x02672 #define PCI_pm_d1supp 0x0200673 #define PCI_pm_d2supp 0x0400674 #define PCI_pm_status 0x04675 #define PCI_pm_state_d0 0x00676 #define PCI_pm_state_d1 0x01677 #define PCI_pm_state_d2 0x02678 #define PCI_pm_state_d3 0x03679 680 #ifdef __cplusplus681 }682 #endif683 684 527 #endif /* _PCI_H */ -
headers/os/drivers/ISA.h
1 /******************************************************************************* 2 / 3 / File: ISA.h 4 / 5 / Description: Interface to ISA module 6 / 7 / Copyright 1998, Be Incorporated, All Rights Reserved. 8 / 9 *******************************************************************************/ 10 1 /* 2 * Copyright 2010, Haiku Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 */ 11 5 #ifndef _ISA_H 12 6 #define _ISA_H 13 7 14 //#include <SupportDefs.h> 8 9 #include <SupportDefs.h> 15 10 #include <bus_manager.h> 16 11 17 #ifdef __cplusplus18 extern "C" {19 #endif20 12 21 /* --- 22 ISA scatter/gather dma support. 23 --- */ 24 25 typedef struct { 26 ulong address; /* memory address (little endian!) 4 bytes */ 27 ushort transfer_count; /* # transfers minus one (little endian!) 2 bytes*/ 28 uchar reserved; /* filler, 1byte*/ 29 uchar flag; /* end of link flag, 1byte */ 13 typedef struct isa_dma_entry { 14 uint32 address; 15 uint16 transfer_count; 16 uchar reserved; 17 uchar flag; 30 18 } isa_dma_entry; 31 19 32 #define B_LAST_ISA_DMA_ENTRY 0x80 /* sets end of link flag in isa_dma_entry */33 20 21 #define B_LAST_ISA_DMA_ENTRY 0x80 22 23 34 24 enum { 35 25 B_8_BIT_TRANSFER, 36 26 B_16_BIT_TRANSFER 37 27 }; 38 28 29 39 30 #define B_MAX_ISA_DMA_COUNT 0x10000 40 31 32 41 33 typedef struct isa_module_info isa_module_info; 42 34 struct isa_module_info { 43 35 bus_manager_info binfo; 44 36 45 uint8 (*read_io_8) (intmapped_io_addr);46 void (*write_io_8) (intmapped_io_addr, uint8 value);47 uint16 (*read_io_16) (intmapped_io_addr);48 void (*write_io_16) (intmapped_io_addr, uint16 value);49 uint32 (*read_io_32) (intmapped_io_addr);50 void (*write_io_32) (intmapped_io_addr, uint32 value);37 uint8 (*read_io_8) (int32 mapped_io_addr); 38 void (*write_io_8) (int32 mapped_io_addr, uint8 value); 39 uint16 (*read_io_16) (int32 mapped_io_addr); 40 void (*write_io_16) (int32 mapped_io_addr, uint16 value); 41 uint32 (*read_io_32) (int32 mapped_io_addr); 42 void (*write_io_32) (int32 mapped_io_addr, uint32 value); 51 43 52 void * (*ram_address) (const void *physical_address_in_system_memory); 44 void* (*ram_address) 45 (const void * physical_address_in_system_memory); 53 46 54 long(*make_isa_dma_table) (55 const void *buffer, /* buffer to make a table for */56 long buffer_size, /* buffer size */57 u long num_bits, /* dma transfer size that will be used */58 isa_dma_entry *table, /* -> caller-supplied scatter/gather table */59 long num_entries /* max # entries in table */47 int32 (*make_isa_dma_table) ( 48 const void *buffer, 49 int32 buffer_size, 50 uint32 num_bits, 51 isa_dma_entry *table, 52 int32 num_entries 60 53 ); 61 long(*start_isa_dma) (62 long channel, /* dma channel to use */63 void *buf, /* buffer to transfer */64 long transfer_count, /* # transfers */65 uchar mode, /* mode flags */66 uchar e_mode /* extended mode flags */54 int32 (*start_isa_dma) ( 55 int32 channel, 56 void *buf, 57 int32 transfer_count, 58 uchar mode, 59 uchar e_mode 67 60 ); 68 long(*start_scattered_isa_dma) (69 long channel, /* channel # to use */70 const isa_dma_entry *table, /* physical address of scatter/gather table */71 uchar mode, /* mode flags */72 uchar emode /* extended mode flags */61 int32 (*start_scattered_isa_dma) ( 62 int32 channel, 63 const isa_dma_entry* table, 64 uchar mode, 65 uchar emode 73 66 ); 74 long (*lock_isa_dma_channel) (longchannel);75 long (*unlock_isa_dma_channel) (longchannel);67 int32 (*lock_isa_dma_channel) (int32 channel); 68 int32 (*unlock_isa_dma_channel) (int32 channel); 76 69 }; 77 70 71 78 72 #define B_ISA_MODULE_NAME "bus_managers/isa/v1" 79 73 80 #ifdef __cplusplus81 }82 #endif83 74 84 75 #endif /* _ISA_H */
