From a1d152f5f7365789b1e5c55dd1304a75e7dcbad5 Mon Sep 17 00:00:00 2001
From: Yongcong Du <ycdu.vmcore@gmail.com>
Date: Tue, 3 Apr 2012 23:46:51 +0800
Subject: [PATCH 2/2] x86: Initialize IA32_MSR_ENERGY_PERF_BIAS
The lowest 4 bits of the MSR serves as a hint to the hardware to
favor performance or energy saving. 0 means a hint preference for
highest performance while 15 corresponds to the maximum energy
savings. A value of 7 translates into a hint to balance performance
with energy savings.
The default reset value of the MSR is 0. If BIOS doesn't intialize
the MSR, the hardware will run in performance state. This patch
initialize the MSR with value of 7 for balance between performance
and energy savings
---
headers/private/kernel/arch/x86/arch_cpu.h | 1 +
src/system/kernel/arch/x86/arch_cpu.cpp | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/headers/private/kernel/arch/x86/arch_cpu.h b/headers/private/kernel/arch/x86/arch_cpu.h
index 5794c7d..521c1d1 100644
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a
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b
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| 29 | 29 | #define IA32_MSR_SYSENTER_CS 0x174 |
| 30 | 30 | #define IA32_MSR_SYSENTER_ESP 0x175 |
| 31 | 31 | #define IA32_MSR_SYSENTER_EIP 0x176 |
| | 32 | #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 |
| 32 | 33 | #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff |
| 33 | 34 | #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 |
| 34 | 35 | #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 |
diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp
index 05b8c01..dad7d7b 100644
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a
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b
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static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = {
|
| 64 | 64 | #define CR4_OS_FXSR (1UL << 9) |
| 65 | 65 | #define CR4_OS_XMM_EXCEPTION (1UL << 10) |
| 66 | 66 | |
| | 67 | /* |
| | 68 | * 0 favors highest performance while 15 corresponds to the maximum energy |
| | 69 | * savings. 7 means balance between performance and energy savings. |
| | 70 | * Refer to Section 14.3.4 in <Intel 64 and IA-32 Architectures Software |
| | 71 | * Developer's Manual Volume 3> for details |
| | 72 | */ |
| | 73 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
| | 74 | #define ENERGY_PERF_BIAS_BALANCE 7 |
| | 75 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
| | 76 | |
| 67 | 77 | struct set_mtrr_parameter { |
| 68 | 78 | int32 index; |
| 69 | 79 | uint64 base; |
| … |
… |
arch_cpu_init_percpu(kernel_args *args, int cpu)
|
| 740 | 750 | asm volatile("lidt %0" : : "m"(descriptor)); |
| 741 | 751 | } |
| 742 | 752 | |
| | 753 | if (x86_check_feature(IA32_FEATURE_EPB, FEATURE_6_ECX)) { |
| | 754 | uint64 msr = x86_read_msr(IA32_MSR_ENERGY_PERF_BIAS); |
| | 755 | if ((msr & 0xf) == ENERGY_PERF_BIAS_PERFORMANCE) { |
| | 756 | msr &= ~0xf; |
| | 757 | msr |= ENERGY_PERF_BIAS_BALANCE; |
| | 758 | x86_write_msr(IA32_MSR_ENERGY_PERF_BIAS, msr); |
| | 759 | } |
| | 760 | } |
| | 761 | |
| 743 | 762 | return 0; |
| 744 | 763 | } |
| 745 | 764 | |
