Index: build/jam/HaikuImage
===================================================================
--- build/jam/HaikuImage	(revision 27723)
+++ build/jam/HaikuImage	(working copy)
@@ -131,7 +131,7 @@
 ;
 BEOS_ADD_ONS_DRIVERS_MIDI = emuxki ;
 BEOS_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com etherpci $(X86_ONLY)ipro1000
-	$(X86_ONLY)rtl8139 rtl8169 sis900 $(X86_ONLY)via_rhine wb840
+	$(X86_ONLY)rtl8139 rtl8169 $(X86_ONLY)re sis900 $(X86_ONLY)via_rhine wb840
 	$(X86_ONLY)ipro100 $(X86_ONLY)nforce #vlance
 	$(X86_ONLY)marvell_yukon $(X86_ONLY)syskonnect usb_ecm
 	$(GPL_ONLY)bcm440x $(GPL_ONLY)bcm570x
Index: src/add-ons/kernel/drivers/network/re/Jamfile
===================================================================
--- src/add-ons/kernel/drivers/network/re/Jamfile	(revision 0)
+++ src/add-ons/kernel/drivers/network/re/Jamfile	(revision 0)
@@ -0,0 +1,3 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network re ;
+
+SubInclude HAIKU_TOP src add-ons kernel drivers network re pci ;
Index: src/add-ons/kernel/drivers/network/re/pci/if_rlreg.h
===================================================================
--- src/add-ons/kernel/drivers/network/re/pci/if_rlreg.h	(revision 0)
+++ src/add-ons/kernel/drivers/network/re/pci/if_rlreg.h	(revision 0)
@@ -0,0 +1,1100 @@
+/*-
+ * Copyright (c) 1997, 1998-2003
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.67.2.14 2008/08/09 02:07:30 yongari Exp $
+ */
+
+/*
+ * RealTek 8129/8139 register offsets
+ */
+#define	RL_IDR0		0x0000		/* ID register 0 (station addr) */
+#define RL_IDR1		0x0001		/* Must use 32-bit accesses (?) */
+#define RL_IDR2		0x0002
+#define RL_IDR3		0x0003
+#define RL_IDR4		0x0004
+#define RL_IDR5		0x0005
+					/* 0006-0007 reserved */
+#define RL_MAR0		0x0008		/* Multicast hash table */
+#define RL_MAR1		0x0009
+#define RL_MAR2		0x000A
+#define RL_MAR3		0x000B
+#define RL_MAR4		0x000C
+#define RL_MAR5		0x000D
+#define RL_MAR6		0x000E
+#define RL_MAR7		0x000F
+
+#define RL_TXSTAT0	0x0010		/* status of TX descriptor 0 */
+#define RL_TXSTAT1	0x0014		/* status of TX descriptor 1 */
+#define RL_TXSTAT2	0x0018		/* status of TX descriptor 2 */
+#define RL_TXSTAT3	0x001C		/* status of TX descriptor 3 */
+
+#define RL_TXADDR0	0x0020		/* address of TX descriptor 0 */
+#define RL_TXADDR1	0x0024		/* address of TX descriptor 1 */
+#define RL_TXADDR2	0x0028		/* address of TX descriptor 2 */
+#define RL_TXADDR3	0x002C		/* address of TX descriptor 3 */
+
+#define RL_RXADDR		0x0030	/* RX ring start address */
+#define RL_RX_EARLY_BYTES	0x0034	/* RX early byte count */
+#define RL_RX_EARLY_STAT	0x0036	/* RX early status */
+#define RL_COMMAND	0x0037		/* command register */
+#define RL_CURRXADDR	0x0038		/* current address of packet read */
+#define RL_CURRXBUF	0x003A		/* current RX buffer address */
+#define RL_IMR		0x003C		/* interrupt mask register */
+#define RL_ISR		0x003E		/* interrupt status register */
+#define RL_TXCFG	0x0040		/* transmit config */
+#define RL_RXCFG	0x0044		/* receive config */
+#define RL_TIMERCNT	0x0048		/* timer count register */
+#define RL_MISSEDPKT	0x004C		/* missed packet counter */
+#define RL_EECMD	0x0050		/* EEPROM command register */
+#define RL_CFG0		0x0051		/* config register #0 */
+#define RL_CFG1		0x0052		/* config register #1 */
+#define	RL_CFG2		0x0053		/* config register #2 */
+#define	RL_CFG3		0x0054		/* config register #3 */
+#define	RL_CFG4		0x0055		/* config register #4 */
+#define	RL_CFG5		0x0056		/* config register #5 */
+					/* 0057 reserved */
+#define RL_MEDIASTAT	0x0058		/* media status register (8139) */
+					/* 0059-005A reserved */
+#define RL_MII		0x005A		/* 8129 chip only */
+#define RL_HALTCLK	0x005B
+#define RL_MULTIINTR	0x005C		/* multiple interrupt */
+#define RL_PCIREV	0x005E		/* PCI revision value */
+					/* 005F reserved */
+#define RL_TXSTAT_ALL	0x0060		/* TX status of all descriptors */
+
+/* Direct PHY access registers only available on 8139 */
+#define RL_BMCR		0x0062		/* PHY basic mode control */
+#define RL_BMSR		0x0064		/* PHY basic mode status */
+#define RL_ANAR		0x0066		/* PHY autoneg advert */
+#define RL_LPAR		0x0068		/* PHY link partner ability */
+#define RL_ANER		0x006A		/* PHY autoneg expansion */
+
+#define RL_DISCCNT	0x006C		/* disconnect counter */
+#define RL_FALSECAR	0x006E		/* false carrier counter */
+#define RL_NWAYTST	0x0070		/* NWAY test register */
+#define RL_RX_ER	0x0072		/* RX_ER counter */
+#define RL_CSCFG	0x0074		/* CS configuration register */
+
+/*
+ * When operating in special C+ mode, some of the registers in an
+ * 8139C+ chip have different definitions. These are also used for
+ * the 8169 gigE chip.
+ */
+#define RL_DUMPSTATS_LO		0x0010	/* counter dump command register */
+#define RL_DUMPSTATS_HI		0x0014	/* counter dump command register */
+#define RL_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte alignment */
+#define RL_CFG2			0x0053
+#define RL_TIMERINT		0x0054	/* interrupt on timer expire */
+#define RL_TXSTART		0x00D9	/* 8 bits */
+#define RL_CPLUS_CMD		0x00E0	/* 16 bits */
+#define RL_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
+#define RL_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
+#define RL_EARLY_TX_THRESH	0x00EC	/* 8 bits */
+
+/*
+ * Registers specific to the 8169 gigE chip
+ */
+#define RL_TIMERINT_8169	0x0058	/* different offset than 8139 */
+#define RL_PHYAR		0x0060
+#define RL_TBICSR		0x0064
+#define RL_TBI_ANAR		0x0068
+#define RL_TBI_LPAR		0x006A
+#define RL_GMEDIASTAT		0x006C	/* 8 bits */
+#define RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
+#define RL_GTXSTART		0x0038	/* 8 bits */
+
+/*
+ * TX config register bits
+ */
+#define RL_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
+#define RL_TXCFG_MAXDMA		0x00000700	/* max DMA burst size */
+#define RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
+#define RL_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
+#define RL_TXCFG_IFG2		0x00080000	/* 8169 only */
+#define RL_TXCFG_IFG		0x03000000	/* interframe gap */
+#define RL_TXCFG_HWREV		0x7CC00000
+
+#define RL_LOOPTEST_OFF		0x00000000
+#define RL_LOOPTEST_ON		0x00020000
+#define RL_LOOPTEST_ON_CPLUS	0x00060000
+
+/* Known revision codes. */
+
+#define RL_HWREV_8169		0x00000000
+#define RL_HWREV_8110S		0x00800000
+#define RL_HWREV_8169S		0x04000000
+#define RL_HWREV_8169_8110SB	0x10000000
+#define RL_HWREV_8169_8110SC	0x18000000
+#define RL_HWREV_8102EL		0x24800000
+#define RL_HWREV_8168_SPIN1	0x30000000
+#define RL_HWREV_8100E		0x30800000
+#define RL_HWREV_8101E		0x34000000
+#define RL_HWREV_8102E		0x34800000
+#define RL_HWREV_8168_SPIN2	0x38000000
+#define RL_HWREV_8168_SPIN3	0x38400000
+#define RL_HWREV_8168C		0x3C000000
+#define RL_HWREV_8168C_SPIN2	0x3C400000
+#define RL_HWREV_8168CP		0x3C800000
+#define RL_HWREV_8139		0x60000000
+#define RL_HWREV_8139A		0x70000000
+#define RL_HWREV_8139AG		0x70800000
+#define RL_HWREV_8139B		0x78000000
+#define RL_HWREV_8130		0x7C000000
+#define RL_HWREV_8139C		0x74000000
+#define RL_HWREV_8139D		0x74400000
+#define RL_HWREV_8139CPLUS	0x74800000
+#define RL_HWREV_8101		0x74c00000
+#define RL_HWREV_8100		0x78800000
+#define RL_HWREV_8169_8110SBL	0x7CC00000
+
+#define RL_TXDMA_16BYTES	0x00000000
+#define RL_TXDMA_32BYTES	0x00000100
+#define RL_TXDMA_64BYTES	0x00000200
+#define RL_TXDMA_128BYTES	0x00000300
+#define RL_TXDMA_256BYTES	0x00000400
+#define RL_TXDMA_512BYTES	0x00000500
+#define RL_TXDMA_1024BYTES	0x00000600
+#define RL_TXDMA_2048BYTES	0x00000700
+
+/*
+ * Transmit descriptor status register bits.
+ */
+#define RL_TXSTAT_LENMASK	0x00001FFF
+#define RL_TXSTAT_OWN		0x00002000
+#define RL_TXSTAT_TX_UNDERRUN	0x00004000
+#define RL_TXSTAT_TX_OK		0x00008000
+#define RL_TXSTAT_EARLY_THRESH	0x003F0000
+#define RL_TXSTAT_COLLCNT	0x0F000000
+#define RL_TXSTAT_CARR_HBEAT	0x10000000
+#define RL_TXSTAT_OUTOFWIN	0x20000000
+#define RL_TXSTAT_TXABRT	0x40000000
+#define RL_TXSTAT_CARRLOSS	0x80000000
+
+/*
+ * Interrupt status register bits.
+ */
+#define RL_ISR_RX_OK		0x0001
+#define RL_ISR_RX_ERR		0x0002
+#define RL_ISR_TX_OK		0x0004
+#define RL_ISR_TX_ERR		0x0008
+#define RL_ISR_RX_OVERRUN	0x0010
+#define RL_ISR_PKT_UNDERRUN	0x0020
+#define RL_ISR_LINKCHG		0x0020	/* 8169 only */
+#define RL_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
+#define RL_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
+#define RL_ISR_SWI		0x0100	/* C+ only */
+#define RL_ISR_CABLE_LEN_CHGD	0x2000
+#define RL_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
+#define RL_ISR_TIMEOUT_EXPIRED	0x4000
+#define RL_ISR_SYSTEM_ERR	0x8000
+
+#define RL_INTRS	\
+	(RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|		\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
+
+#ifdef RE_TX_MODERATION
+#define RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|			\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+#else
+#define RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|		\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+#endif
+
+/*
+ * Media status register. (8139 only)
+ */
+#define RL_MEDIASTAT_RXPAUSE	0x01
+#define RL_MEDIASTAT_TXPAUSE	0x02
+#define RL_MEDIASTAT_LINK	0x04
+#define RL_MEDIASTAT_SPEED10	0x08
+#define RL_MEDIASTAT_RXFLOWCTL	0x40	/* duplex mode */
+#define RL_MEDIASTAT_TXFLOWCTL	0x80	/* duplex mode */
+
+/*
+ * Receive config register.
+ */
+#define RL_RXCFG_RX_ALLPHYS	0x00000001	/* accept all nodes */
+#define RL_RXCFG_RX_INDIV	0x00000002	/* match filter */
+#define RL_RXCFG_RX_MULTI	0x00000004	/* accept all multicast */
+#define RL_RXCFG_RX_BROAD	0x00000008	/* accept all broadcast */
+#define RL_RXCFG_RX_RUNT	0x00000010
+#define RL_RXCFG_RX_ERRPKT	0x00000020
+#define RL_RXCFG_WRAP		0x00000080
+#define RL_RXCFG_MAXDMA		0x00000700
+#define RL_RXCFG_BUFSZ		0x00001800
+#define RL_RXCFG_FIFOTHRESH	0x0000E000
+#define RL_RXCFG_EARLYTHRESH	0x07000000
+
+#define RL_RXDMA_16BYTES	0x00000000
+#define RL_RXDMA_32BYTES	0x00000100
+#define RL_RXDMA_64BYTES	0x00000200
+#define RL_RXDMA_128BYTES	0x00000300
+#define RL_RXDMA_256BYTES	0x00000400
+#define RL_RXDMA_512BYTES	0x00000500
+#define RL_RXDMA_1024BYTES	0x00000600
+#define RL_RXDMA_UNLIMITED	0x00000700
+
+#define RL_RXBUF_8		0x00000000
+#define RL_RXBUF_16		0x00000800
+#define RL_RXBUF_32		0x00001000
+#define RL_RXBUF_64		0x00001800
+
+#define RL_RXFIFO_16BYTES	0x00000000
+#define RL_RXFIFO_32BYTES	0x00002000
+#define RL_RXFIFO_64BYTES	0x00004000
+#define RL_RXFIFO_128BYTES	0x00006000
+#define RL_RXFIFO_256BYTES	0x00008000
+#define RL_RXFIFO_512BYTES	0x0000A000
+#define RL_RXFIFO_1024BYTES	0x0000C000
+#define RL_RXFIFO_NOTHRESH	0x0000E000
+
+/*
+ * Bits in RX status header (included with RX'ed packet
+ * in ring buffer).
+ */
+#define RL_RXSTAT_RXOK		0x00000001
+#define RL_RXSTAT_ALIGNERR	0x00000002
+#define RL_RXSTAT_CRCERR	0x00000004
+#define RL_RXSTAT_GIANT		0x00000008
+#define RL_RXSTAT_RUNT		0x00000010
+#define RL_RXSTAT_BADSYM	0x00000020
+#define RL_RXSTAT_BROAD		0x00002000
+#define RL_RXSTAT_INDIV		0x00004000
+#define RL_RXSTAT_MULTI		0x00008000
+#define RL_RXSTAT_LENMASK	0xFFFF0000
+
+#define RL_RXSTAT_UNFINISHED	0xFFF0		/* DMA still in progress */
+/*
+ * Command register.
+ */
+#define RL_CMD_EMPTY_RXBUF	0x0001
+#define RL_CMD_TX_ENB		0x0004
+#define RL_CMD_RX_ENB		0x0008
+#define RL_CMD_RESET		0x0010
+
+/*
+ * EEPROM control register
+ */
+#define RL_EE_DATAOUT		0x01	/* Data out */
+#define RL_EE_DATAIN		0x02	/* Data in */
+#define RL_EE_CLK		0x04	/* clock */
+#define RL_EE_SEL		0x08	/* chip select */
+#define RL_EE_MODE		(0x40|0x80)
+
+#define RL_EEMODE_OFF		0x00
+#define RL_EEMODE_AUTOLOAD	0x40
+#define RL_EEMODE_PROGRAM	0x80
+#define RL_EEMODE_WRITECFG	(0x80|0x40)
+
+/* 9346 EEPROM commands */
+#define RL_9346_ADDR_LEN	6	/* 93C46 1K: 128x16 */
+#define RL_9356_ADDR_LEN	8	/* 93C56 2K: 256x16 */
+
+#define RL_9346_WRITE          0x5
+#define RL_9346_READ           0x6
+#define RL_9346_ERASE          0x7
+#define RL_9346_EWEN           0x4
+#define RL_9346_EWEN_ADDR      0x30
+#define RL_9456_EWDS           0x4
+#define RL_9346_EWDS_ADDR      0x00
+
+#define RL_EECMD_WRITE		0x140
+#define RL_EECMD_READ_6BIT	0x180
+#define RL_EECMD_READ_8BIT	0x600
+#define RL_EECMD_ERASE		0x1c0
+
+#define RL_EE_ID		0x00
+#define RL_EE_PCI_VID		0x01
+#define RL_EE_PCI_DID		0x02
+/* Location of station address inside EEPROM */
+#define RL_EE_EADDR		0x07
+
+/*
+ * MII register (8129 only)
+ */
+#define RL_MII_CLK		0x01
+#define RL_MII_DATAIN		0x02
+#define RL_MII_DATAOUT		0x04
+#define RL_MII_DIR		0x80	/* 0 == input, 1 == output */
+
+/*
+ * Config 0 register
+ */
+#define RL_CFG0_ROM0		0x01
+#define RL_CFG0_ROM1		0x02
+#define RL_CFG0_ROM2		0x04
+#define RL_CFG0_PL0		0x08
+#define RL_CFG0_PL1		0x10
+#define RL_CFG0_10MBPS		0x20	/* 10 Mbps internal mode */
+#define RL_CFG0_PCS		0x40
+#define RL_CFG0_SCR		0x80
+
+/*
+ * Config 1 register
+ */
+#define RL_CFG1_PWRDWN		0x01
+#define RL_CFG1_PME		0x01	
+#define RL_CFG1_SLEEP		0x02
+#define RL_CFG1_VPDEN		0x02
+#define RL_CFG1_IOMAP		0x04
+#define RL_CFG1_MEMMAP		0x08
+#define RL_CFG1_RSVD		0x10
+#define	RL_CFG1_LWACT		0x10
+#define RL_CFG1_DRVLOAD		0x20
+#define RL_CFG1_LED0		0x40
+#define RL_CFG1_FULLDUPLEX	0x40	/* 8129 only */
+#define RL_CFG1_LED1		0x80
+
+/*
+ * Config 2 register
+ */
+#define	RL_CFG2_PCI33MHZ	0x00
+#define	RL_CFG2_PCI66MHZ	0x01
+#define	RL_CFG2_PCI64BIT	0x08
+#define	RL_CFG2_AUXPWR		0x10
+#define	RL_CFG2_MSI		0x20
+
+/*
+ * Config 3 register
+ */
+#define	RL_CFG3_GRANTSEL	0x80
+#define	RL_CFG3_WOL_MAGIC	0x20
+#define	RL_CFG3_WOL_LINK	0x10
+#define	RL_CFG3_FAST_B2B	0x01
+
+/*
+ * Config 4 register
+ */
+#define	RL_CFG4_LWPTN		0x04
+#define	RL_CFG4_LWPME		0x10
+
+/*
+ * Config 5 register
+ */
+#define	RL_CFG5_WOL_BCAST	0x40
+#define	RL_CFG5_WOL_MCAST	0x20
+#define	RL_CFG5_WOL_UCAST	0x10
+#define	RL_CFG5_WOL_LANWAKE	0x02
+#define	RL_CFG5_PME_STS		0x01
+
+/*
+ * 8139C+ register definitions
+ */
+
+/* RL_DUMPSTATS_LO register */
+
+#define RL_DUMPSTATS_START	0x00000008
+
+/* Transmit start register */
+
+#define RL_TXSTART_SWI		0x01	/* generate TX interrupt */
+#define RL_TXSTART_START	0x40	/* start normal queue transmit */
+#define RL_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
+
+/*
+ * Config 2 register, 8139C+/8169/8169S/8110S only
+ */
+#define RL_CFG2_BUSFREQ		0x07
+#define RL_CFG2_BUSWIDTH	0x08
+#define RL_CFG2_AUXPWRSTS	0x10
+
+#define RL_BUSFREQ_33MHZ	0x00
+#define RL_BUSFREQ_66MHZ	0x01
+                                        
+#define RL_BUSWIDTH_32BITS	0x00
+#define RL_BUSWIDTH_64BITS	0x08
+
+/* C+ mode command register */
+
+#define RL_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
+#define RL_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
+#define RL_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
+#define RL_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
+#define RL_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
+#define RL_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
+#define	RL_CPLUSCMD_MACSTAT_DIS	0x0080	/* 8168B/C/CP */
+#define	RL_CPLUSCMD_ASF		0x0100	/* 8168C/CP */
+#define	RL_CPLUSCMD_DBG_SEL	0x0200	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_TXFC	0x0400	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_RXFC	0x0800	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_HDPX	0x1000	/* 8168C/CP */
+#define	RL_CPLUSCMD_NORMAL_MODE	0x2000	/* 8168C/CP */
+#define	RL_CPLUSCMD_DBG_ENB	0x4000	/* 8168C/CP */
+#define	RL_CPLUSCMD_BIST_ENB	0x8000	/* 8168C/CP */
+
+/* C+ early transmit threshold */
+
+#define RL_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */ 
+
+/*
+ * Gigabit PHY access register (8169 only)
+ */
+
+#define RL_PHYAR_PHYDATA	0x0000FFFF
+#define RL_PHYAR_PHYREG		0x001F0000
+#define RL_PHYAR_BUSY		0x80000000
+
+/*
+ * Gigabit media status (8169 only)
+ */
+#define RL_GMEDIASTAT_FDX	0x01	/* full duplex */
+#define RL_GMEDIASTAT_LINK	0x02	/* link up */
+#define RL_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
+#define RL_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
+#define RL_GMEDIASTAT_1000MBPS	0x10	/* gigE link */
+#define RL_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
+#define RL_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
+#define RL_GMEDIASTAT_TBI	0x80	/* TBI enabled */
+
+/*
+ * The RealTek doesn't use a fragment-based descriptor mechanism.
+ * Instead, there are only four register sets, each or which represents
+ * one 'descriptor.' Basically, each TX descriptor is just a contiguous
+ * packet buffer (32-bit aligned!) and we place the buffer addresses in
+ * the registers so the chip knows where they are.
+ *
+ * We can sort of kludge together the same kind of buffer management
+ * used in previous drivers, but we have to do buffer copies almost all
+ * the time, so it doesn't really buy us much.
+ *
+ * For reception, there's just one large buffer where the chip stores
+ * all received packets.
+ */
+
+#define RL_RX_BUF_SZ		RL_RXBUF_64
+#define RL_RXBUFLEN		(1 << ((RL_RX_BUF_SZ >> 11) + 13))
+#define RL_TX_LIST_CNT		4
+#define RL_MIN_FRAMELEN		60
+#define RL_TXTHRESH(x)		((x) << 11)
+#define RL_TX_THRESH_INIT	96
+#define RL_RX_FIFOTHRESH	RL_RXFIFO_NOTHRESH
+#define RL_RX_MAXDMA		RL_RXDMA_UNLIMITED
+#define RL_TX_MAXDMA		RL_TXDMA_2048BYTES
+
+#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
+#define RL_TXCFG_CONFIG	(RL_TXCFG_IFG|RL_TX_MAXDMA)
+
+#define RL_ETHER_ALIGN	2
+
+/*
+ * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
+ */
+#define	RL_IP4CSUMTX_MINLEN	28
+#define	RL_IP4CSUMTX_PADLEN	(ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
+
+struct rl_chain_data {
+	uint16_t		cur_rx;
+	uint8_t			*rl_rx_buf;
+	uint8_t			*rl_rx_buf_ptr;
+	bus_dmamap_t		rl_rx_dmamap;
+
+	struct mbuf		*rl_tx_chain[RL_TX_LIST_CNT];
+	bus_dmamap_t		rl_tx_dmamap[RL_TX_LIST_CNT];
+	uint8_t			last_tx;
+	uint8_t			cur_tx;
+};
+
+#define RL_INC(x)		(x = (x + 1) % RL_TX_LIST_CNT)
+#define RL_CUR_TXADDR(x)	((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
+#define RL_CUR_TXSTAT(x)	((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
+#define RL_CUR_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
+#define RL_CUR_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
+#define RL_LAST_TXADDR(x)	((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
+#define RL_LAST_TXSTAT(x)	((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
+#define RL_LAST_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
+#define RL_LAST_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
+
+struct rl_type {
+	uint16_t		rl_vid;
+	uint16_t		rl_did;
+	int			rl_basetype;
+	char			*rl_name;
+};
+
+struct rl_hwrev {
+	uint32_t		rl_rev;
+	int			rl_type;
+	char			*rl_desc;
+};
+
+struct rl_mii_frame {
+	uint8_t		mii_stdelim;
+	uint8_t		mii_opcode;
+	uint8_t		mii_phyaddr;
+	uint8_t		mii_regaddr;
+	uint8_t		mii_turnaround;
+	uint16_t	mii_data;
+};
+
+/*
+ * MII constants
+ */
+#define RL_MII_STARTDELIM	0x01
+#define RL_MII_READOP		0x02
+#define RL_MII_WRITEOP		0x01
+#define RL_MII_TURNAROUND	0x02
+
+#define RL_8129			1
+#define RL_8139			2
+#define RL_8139CPLUS		3
+#define RL_8169			4
+
+#define RL_ISCPLUS(x)		((x)->rl_type == RL_8139CPLUS ||	\
+				 (x)->rl_type == RL_8169)
+
+/*
+ * The 8139C+ and 8160 gigE chips support descriptor-based TX
+ * and RX. In fact, they even support TCP large send. Descriptors
+ * must be allocated in contiguous blocks that are aligned on a
+ * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
+ */
+
+/*
+ * RX/TX descriptor definition. When large send mode is enabled, the
+ * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
+ * the checksum offload bits are disabled. The structure layout is
+ * the same for RX and TX descriptors
+ */
+
+struct rl_desc {
+	uint32_t		rl_cmdstat;
+	uint32_t		rl_vlanctl;
+	uint32_t		rl_bufaddr_lo;
+	uint32_t		rl_bufaddr_hi;
+};
+
+#define RL_TDESC_CMD_FRAGLEN	0x0000FFFF
+#define RL_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
+#define RL_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
+#define RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
+#define RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
+#define RL_TDESC_CMD_MSSVAL_SHIFT	16	/* Large send MSS value shift */
+#define RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
+#define RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
+#define RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
+#define RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
+#define RL_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
+
+#define RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
+#define RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
+#define	RL_TDESC_CMD_UDPCSUMV2	0x80000000
+#define	RL_TDESC_CMD_TCPCSUMV2	0x40000000	
+#define	RL_TDESC_CMD_IPCSUMV2	0x20000000	
+
+/*
+ * Error bits are valid only on the last descriptor of a frame
+ * (i.e. RL_TDESC_CMD_EOF == 1)
+ */
+
+#define RL_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
+#define RL_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
+#define RL_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
+#define RL_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
+#define RL_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
+#define RL_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occured */
+#define RL_TDESC_STAT_OWN	0x80000000
+
+/*
+ * RX descriptor cmd/vlan definitions
+ */
+
+#define RL_RDESC_CMD_EOR	0x40000000
+#define RL_RDESC_CMD_OWN	0x80000000
+#define RL_RDESC_CMD_BUFLEN	0x00001FFF
+
+#define RL_RDESC_STAT_OWN	0x80000000
+#define RL_RDESC_STAT_EOR	0x40000000
+#define RL_RDESC_STAT_SOF	0x20000000
+#define RL_RDESC_STAT_EOF	0x10000000
+#define RL_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
+#define RL_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
+#define RL_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
+#define RL_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
+#define RL_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
+#define RL_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
+#define RL_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
+#define RL_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
+#define RL_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
+#define RL_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
+#define RL_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
+#define	RL_RDESC_STAT_UDP	0x00020000	/* UDP, 8168C/CP, 8111C/CP */
+#define	RL_RDESC_STAT_TCP	0x00010000	/* TCP, 8168C/CP, 8111C/CP */
+#define RL_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
+#define RL_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
+#define RL_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
+#define RL_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
+#define RL_RDESC_STAT_GFRAGLEN	0x00003FFF	/* RX'ed frame/frag len */
+#define RL_RDESC_STAT_ERRS	(RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
+				 RL_RDESC_STAT_CRCERR)
+
+#define RL_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
+						   (rl_vlandata valid)*/
+#define RL_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
+#define	RL_RDESC_IPV6		0x80000000
+#define	RL_RDESC_IPV4		0x40000000
+
+#define RL_PROTOID_NONIP	0x00000000
+#define RL_PROTOID_TCPIP	0x00010000
+#define RL_PROTOID_UDPIP	0x00020000
+#define RL_PROTOID_IP		0x00030000
+#define RL_TCPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_TCPIP)
+#define RL_UDPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_UDPIP)
+
+/*
+ * Statistics counter structure (8139C+ and 8169 only)
+ */
+struct rl_stats {
+	uint32_t		rl_tx_pkts_lo;
+	uint32_t		rl_tx_pkts_hi;
+	uint32_t		rl_tx_errs_lo;
+	uint32_t		rl_tx_errs_hi;
+	uint32_t		rl_tx_errs;
+	uint16_t		rl_missed_pkts;
+	uint16_t		rl_rx_framealign_errs;
+	uint32_t		rl_tx_onecoll;
+	uint32_t		rl_tx_multicolls;
+	uint32_t		rl_rx_ucasts_hi;
+	uint32_t		rl_rx_ucasts_lo;
+	uint32_t		rl_rx_bcasts_lo;
+	uint32_t		rl_rx_bcasts_hi;
+	uint32_t		rl_rx_mcasts;
+	uint16_t		rl_tx_aborts;
+	uint16_t		rl_rx_underruns;
+};
+
+/*
+ * Rx/Tx descriptor parameters (8139C+ and 8169 only)
+ *
+ * 8139C+
+ *  Number of descriptors supported : up to 64
+ *  Descriptor alignment : 256 bytes
+ *  Tx buffer : At least 4 bytes in length.
+ *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
+ *  
+ * 8169
+ *  Number of descriptors supported : up to 1024
+ *  Descriptor alignment : 256 bytes
+ *  Tx buffer : At least 4 bytes in length.
+ *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
+ */
+#ifndef	__NO_STRICT_ALIGNMENT
+#define RE_FIXUP_RX	1
+#endif
+
+#define RL_8169_TX_DESC_CNT	256
+#define RL_8169_RX_DESC_CNT	256
+#define RL_8139_TX_DESC_CNT	64
+#define RL_8139_RX_DESC_CNT	64
+#define RL_TX_DESC_CNT		RL_8169_TX_DESC_CNT
+#define RL_RX_DESC_CNT		RL_8169_RX_DESC_CNT
+#define	RL_NTXSEGS		32
+
+#define RL_RING_ALIGN		256
+#define RL_IFQ_MAXLEN		512
+#define RL_TX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
+#define RL_TX_DESC_PRV(sc,x)	((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
+#define RL_RX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
+#define RL_OWN(x)		(le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
+#define RL_RXBYTES(x)		(le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
+#define RL_PKTSZ(x)		((x)/* >> 3*/)
+#ifdef RE_FIXUP_RX
+#define RE_ETHER_ALIGN	sizeof(uint64_t)
+#define RE_RX_DESC_BUFLEN	(MCLBYTES - RE_ETHER_ALIGN)
+#else
+#define RE_ETHER_ALIGN	0
+#define RE_RX_DESC_BUFLEN	MCLBYTES
+#endif
+
+#define	RL_MSI_MESSAGES	2
+
+#define RL_ADDR_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
+#define RL_ADDR_HI(y)		((uint64_t) (y) >> 32)
+
+/*
+ * The number of bits reserved for MSS in RealTek controllers is
+ * 11bits. This limits the maximum interface MTU size in TSO case
+ * as upper stack should not generate TCP segments with MSS greater
+ * than the limit.
+ */
+#define	RL_TSO_MTU		(2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
+
+/* see comment in dev/re/if_re.c */
+#define RL_JUMBO_FRAMELEN	7440
+#define RL_JUMBO_MTU		(RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define	RL_MAX_FRAMELEN		\
+	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
+
+struct rl_txdesc {
+	struct mbuf		*tx_m;
+	bus_dmamap_t		tx_dmamap;
+};
+
+struct rl_rxdesc {
+	struct mbuf		*rx_m;
+	bus_dmamap_t		rx_dmamap;
+	bus_size_t		rx_size;
+};
+
+struct rl_list_data {
+	struct rl_txdesc	rl_tx_desc[RL_TX_DESC_CNT];
+	struct rl_rxdesc	rl_rx_desc[RL_RX_DESC_CNT];
+	int			rl_tx_desc_cnt;
+	int			rl_rx_desc_cnt;
+	int			rl_tx_prodidx;
+	int			rl_rx_prodidx;
+	int			rl_tx_considx;
+	int			rl_tx_free;
+	bus_dma_tag_t		rl_tx_mtag;	/* mbuf TX mapping tag */
+	bus_dma_tag_t		rl_rx_mtag;	/* mbuf RX mapping tag */
+	bus_dmamap_t		rl_rx_sparemap;
+	bus_dma_tag_t		rl_stag;	/* stats mapping tag */
+	bus_dmamap_t		rl_smap;	/* stats map */
+	struct rl_stats		*rl_stats;
+	bus_addr_t		rl_stats_addr;
+	bus_dma_tag_t		rl_rx_list_tag;
+	bus_dmamap_t		rl_rx_list_map;
+	struct rl_desc		*rl_rx_list;
+	bus_addr_t		rl_rx_list_addr;
+	bus_dma_tag_t		rl_tx_list_tag;
+	bus_dmamap_t		rl_tx_list_map;
+	struct rl_desc		*rl_tx_list;
+	bus_addr_t		rl_tx_list_addr;
+};
+
+struct rl_softc {
+	struct ifnet		*rl_ifp;	/* interface info */
+	bus_space_handle_t	rl_bhandle;	/* bus space handle */
+	bus_space_tag_t		rl_btag;	/* bus space tag */
+	device_t		rl_dev;
+	struct resource		*rl_res;
+	int			rl_res_id;
+	int			rl_res_type;
+	struct resource		*rl_irq[RL_MSI_MESSAGES];
+	void			*rl_intrhand[RL_MSI_MESSAGES];
+	device_t		rl_miibus;
+	bus_dma_tag_t		rl_parent_tag;
+	bus_dma_tag_t		rl_tag;
+	uint8_t			rl_type;
+	int			rl_eecmd_read;
+	int			rl_eewidth;
+	uint8_t			rl_stats_no_timeout;
+	int			rl_txthresh;
+	struct rl_chain_data	rl_cdata;
+	struct rl_list_data	rl_ldata;
+	struct callout		rl_stat_callout;
+	int			rl_watchdog_timer;
+	struct mtx		rl_mtx;
+	struct mbuf		*rl_head;
+	struct mbuf		*rl_tail;
+	uint32_t		rl_hwrev;
+	uint32_t		rl_rxlenmask;
+	int			rl_testmode;
+	int			rl_if_flags;
+	int			suspended;	/* 0 = normal  1 = suspended */
+#ifdef DEVICE_POLLING
+	int			rxcycles;
+#endif
+
+	struct task		rl_txtask;
+	struct task		rl_inttask;
+
+	int			rl_txstart;
+	uint32_t		rl_flags;
+#define	RL_FLAG_MSI		0x0001
+#define	RL_FLAG_INVMAR		0x0004
+#define	RL_FLAG_PHYWAKE		0x0008
+#define	RL_FLAG_NOJUMBO		0x0010
+#define	RL_FLAG_PAR		0x0020
+#define	RL_FLAG_DESCV2		0x0040
+#define	RL_FLAG_MACSTAT		0x0080
+#define	RL_FLAG_LINK		0x8000
+};
+
+#define	RL_LOCK(_sc)		mtx_lock(&(_sc)->rl_mtx)
+#define	RL_UNLOCK(_sc)		mtx_unlock(&(_sc)->rl_mtx)
+#define	RL_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_STREAM_4(sc, reg, val)	\
+	bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define CSR_WRITE_2(sc, reg, val)	\
+	bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define CSR_WRITE_1(sc, reg, val)	\
+	bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg)		\
+	bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
+#define CSR_READ_2(sc, reg)		\
+	bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
+#define CSR_READ_1(sc, reg)		\
+	bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
+
+#define CSR_SETBIT_1(sc, offset, val)		\
+	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
+
+#define CSR_CLRBIT_1(sc, offset, val)		\
+	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
+
+#define CSR_SETBIT_2(sc, offset, val)		\
+	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
+
+#define CSR_CLRBIT_2(sc, offset, val)		\
+	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
+
+#define CSR_SETBIT_4(sc, offset, val)		\
+	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
+
+#define CSR_CLRBIT_4(sc, offset, val)		\
+	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
+
+#define RL_TIMEOUT		1000
+
+/*
+ * General constants that are fun to know.
+ *
+ * RealTek PCI vendor ID
+ */
+#define	RT_VENDORID				0x10EC
+
+/*
+ * RealTek chip device IDs.
+ */
+#define RT_DEVICEID_8139D			0x8039
+#define	RT_DEVICEID_8129			0x8129
+#define RT_DEVICEID_8101E			0x8136
+#define	RT_DEVICEID_8138			0x8138
+#define	RT_DEVICEID_8139			0x8139
+#define RT_DEVICEID_8169SC			0x8167
+#define RT_DEVICEID_8168			0x8168
+#define RT_DEVICEID_8169			0x8169
+#define RT_DEVICEID_8100			0x8100
+
+#define RT_REVID_8139CPLUS			0x20
+
+/*
+ * Accton PCI vendor ID
+ */
+#define ACCTON_VENDORID				0x1113
+
+/*
+ * Accton MPX 5030/5038 device ID.
+ */
+#define ACCTON_DEVICEID_5030			0x1211
+
+/*
+ * Nortel PCI vendor ID
+ */
+#define NORTEL_VENDORID				0x126C
+
+/*
+ * Delta Electronics Vendor ID.
+ */
+#define DELTA_VENDORID				0x1500
+
+/*
+ * Delta device IDs.
+ */
+#define DELTA_DEVICEID_8139			0x1360
+
+/*
+ * Addtron vendor ID.
+ */
+#define ADDTRON_VENDORID			0x4033
+
+/*
+ * Addtron device IDs.
+ */
+#define ADDTRON_DEVICEID_8139			0x1360
+
+/*
+ * D-Link vendor ID.
+ */
+#define DLINK_VENDORID				0x1186
+
+/*
+ * D-Link DFE-530TX+ device ID
+ */
+#define DLINK_DEVICEID_530TXPLUS		0x1300
+
+/*
+ * D-Link DFE-5280T device ID
+ */
+#define DLINK_DEVICEID_528T			0x4300
+
+/*
+ * D-Link DFE-690TXD device ID
+ */
+#define DLINK_DEVICEID_690TXD			0x1340
+
+/*
+ * Corega K.K vendor ID
+ */
+#define COREGA_VENDORID				0x1259
+
+/*
+ * Corega FEther CB-TXD device ID
+ */
+#define COREGA_DEVICEID_FETHERCBTXD		0xa117
+
+/*
+ * Corega FEtherII CB-TXD device ID
+ */
+#define COREGA_DEVICEID_FETHERIICBTXD		0xa11e
+
+/*
+ * Corega CG-LAPCIGT device ID
+ */
+#define COREGA_DEVICEID_CGLAPCIGT		0xc107
+
+/*
+ * Linksys vendor ID
+ */
+#define LINKSYS_VENDORID			0x1737
+
+/*
+ * Linksys EG1032 device ID
+ */
+#define LINKSYS_DEVICEID_EG1032			0x1032
+
+/*
+ * Linksys EG1032 rev 3 sub-device ID
+ */
+#define LINKSYS_SUBDEVICE_EG1032_REV3		0x0024
+
+/*
+ * Peppercon vendor ID
+ */
+#define PEPPERCON_VENDORID			0x1743
+
+/*
+ * Peppercon ROL-F device ID
+ */
+#define PEPPERCON_DEVICEID_ROLF			0x8139
+
+/*
+ * Planex Communications, Inc. vendor ID
+ */
+#define PLANEX_VENDORID				0x14ea
+
+/*
+ * Planex FNW-3603-TX device ID
+ */
+#define PLANEX_DEVICEID_FNW3603TX		0xab06
+
+/*
+ * Planex FNW-3800-TX device ID
+ */
+#define PLANEX_DEVICEID_FNW3800TX		0xab07
+
+/*
+ * LevelOne vendor ID
+ */
+#define LEVEL1_VENDORID				0x018A
+
+/*
+ * LevelOne FPC-0106TX devide ID
+ */
+#define LEVEL1_DEVICEID_FPC0106TX		0x0106
+
+/*
+ * Compaq vendor ID
+ */
+#define CP_VENDORID				0x021B
+
+/*
+ * Edimax vendor ID
+ */
+#define EDIMAX_VENDORID				0x13D1
+
+/*
+ * Edimax EP-4103DL cardbus device ID
+ */
+#define EDIMAX_DEVICEID_EP4103DL		0xAB06
+
+/* US Robotics vendor ID */
+
+#define USR_VENDORID		0x16EC
+
+/* US Robotics 997902 device ID */
+
+#define USR_DEVICEID_997902	0x0116
+
+/*
+ * PCI low memory base and low I/O base register, and
+ * other PCI registers.
+ */
+
+#define RL_PCI_VENDOR_ID	0x00
+#define RL_PCI_DEVICE_ID	0x02
+#define RL_PCI_COMMAND		0x04
+#define RL_PCI_STATUS		0x06
+#define RL_PCI_CLASSCODE	0x09
+#define RL_PCI_LATENCY_TIMER	0x0D
+#define RL_PCI_HEADER_TYPE	0x0E
+#define RL_PCI_LOIO		0x10
+#define RL_PCI_LOMEM		0x14
+#define RL_PCI_BIOSROM		0x30
+#define RL_PCI_INTLINE		0x3C
+#define RL_PCI_INTPIN		0x3D
+#define RL_PCI_MINGNT		0x3E
+#define RL_PCI_MINLAT		0x0F
+#define RL_PCI_RESETOPT		0x48
+#define RL_PCI_EEPROM_DATA	0x4C
+
+#define RL_PCI_CAPID		0x50 /* 8 bits */
+#define RL_PCI_NEXTPTR		0x51 /* 8 bits */
+#define RL_PCI_PWRMGMTCAP	0x52 /* 16 bits */
+#define RL_PCI_PWRMGMTCTRL	0x54 /* 16 bits */
+
+#define RL_PSTATE_MASK		0x0003
+#define RL_PSTATE_D0		0x0000
+#define RL_PSTATE_D1		0x0002
+#define RL_PSTATE_D2		0x0002
+#define RL_PSTATE_D3		0x0003
+#define RL_PME_EN		0x0010
+#define RL_PME_STATUS		0x8000
+
Index: src/add-ons/kernel/drivers/network/re/pci/if_re.c
===================================================================
--- src/add-ons/kernel/drivers/network/re/pci/if_re.c	(revision 0)
+++ src/add-ons/kernel/drivers/network/re/pci/if_re.c	(revision 0)
@@ -0,0 +1,3149 @@
+/*-
+ * Copyright (c) 1997, 1998-2003
+ *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.95.2.36 2008/09/19 03:36:53 yongari Exp $");
+
+/*
+ * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
+ *
+ * Written by Bill Paul <wpaul@windriver.com>
+ * Senior Networking Software Engineer
+ * Wind River Systems
+ */
+
+/*
+ * This driver is designed to support RealTek's next generation of
+ * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
+ * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
+ * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
+ *
+ * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
+ * with the older 8139 family, however it also supports a special
+ * C+ mode of operation that provides several new performance enhancing
+ * features. These include:
+ *
+ *	o Descriptor based DMA mechanism. Each descriptor represents
+ *	  a single packet fragment. Data buffers may be aligned on
+ *	  any byte boundary.
+ *
+ *	o 64-bit DMA
+ *
+ *	o TCP/IP checksum offload for both RX and TX
+ *
+ *	o High and normal priority transmit DMA rings
+ *
+ *	o VLAN tag insertion and extraction
+ *
+ *	o TCP large send (segmentation offload)
+ *
+ * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
+ * programming API is fairly straightforward. The RX filtering, EEPROM
+ * access and PHY access is the same as it is on the older 8139 series
+ * chips.
+ *
+ * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
+ * same programming API and feature set as the 8139C+ with the following
+ * differences and additions:
+ *
+ *	o 1000Mbps mode
+ *
+ *	o Jumbo frames
+ *
+ *	o GMII and TBI ports/registers for interfacing with copper
+ *	  or fiber PHYs
+ *
+ *	o RX and TX DMA rings can have up to 1024 descriptors
+ *	  (the 8139C+ allows a maximum of 64)
+ *
+ *	o Slight differences in register layout from the 8139C+
+ *
+ * The TX start and timer interrupt registers are at different locations
+ * on the 8169 than they are on the 8139C+. Also, the status word in the
+ * RX descriptor has a slightly different bit layout. The 8169 does not
+ * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
+ * copper gigE PHY.
+ *
+ * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
+ * (the 'S' stands for 'single-chip'). These devices have the same
+ * programming API as the older 8169, but also have some vendor-specific
+ * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
+ * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
+ *
+ * This driver takes advantage of the RX and TX checksum offload and
+ * VLAN tag insertion/extraction features. It also implements TX
+ * interrupt moderation using the timer interrupt registers, which
+ * significantly reduces TX interrupt load. There is also support
+ * for jumbo frames, however the 8169/8169S/8110S can not transmit
+ * jumbo frames larger than 7440, so the max MTU possible with this
+ * driver is 7422 bytes.
+ */
+
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/taskqueue.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <pci/if_rlreg.h>
+
+MODULE_DEPEND(re, pci, 1, 1, 1);
+MODULE_DEPEND(re, ether, 1, 1, 1);
+MODULE_DEPEND(re, miibus, 1, 1, 1);
+
+/* "device miibus" required.  See GENERIC if you get errors here. */
+#include "miibus_if.h"
+
+/* Tunables. */
+static int msi_disable = 1;
+TUNABLE_INT("hw.re.msi_disable", &msi_disable);
+
+#define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static struct rl_type re_devs[] = {
+	{ DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
+	    "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
+	{ RT_VENDORID, RT_DEVICEID_8139, 0,
+	    "RealTek 8139C+ 10/100BaseTX" },
+	{ RT_VENDORID, RT_DEVICEID_8101E, 0,
+	    "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" },
+	{ RT_VENDORID, RT_DEVICEID_8168, 0,
+	    "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe "
+	    "Gigabit Ethernet" },
+	{ RT_VENDORID, RT_DEVICEID_8169, 0,
+	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
+	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
+	    "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
+	{ COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
+	    "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
+	{ LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
+	    "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
+	{ USR_VENDORID, USR_DEVICEID_997902, 0,
+	    "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
+};
+
+static struct rl_hwrev re_hwrevs[] = {
+	{ RL_HWREV_8139, RL_8139,  "" },
+	{ RL_HWREV_8139A, RL_8139, "A" },
+	{ RL_HWREV_8139AG, RL_8139, "A-G" },
+	{ RL_HWREV_8139B, RL_8139, "B" },
+	{ RL_HWREV_8130, RL_8139, "8130" },
+	{ RL_HWREV_8139C, RL_8139, "C" },
+	{ RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
+	{ RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
+	{ RL_HWREV_8168_SPIN1, RL_8169, "8168"},
+	{ RL_HWREV_8169, RL_8169, "8169"},
+	{ RL_HWREV_8169S, RL_8169, "8169S"},
+	{ RL_HWREV_8110S, RL_8169, "8110S"},
+	{ RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
+	{ RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
+	{ RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"},
+	{ RL_HWREV_8100, RL_8139, "8100"},
+	{ RL_HWREV_8101, RL_8139, "8101"},
+	{ RL_HWREV_8100E, RL_8169, "8100E"},
+	{ RL_HWREV_8101E, RL_8169, "8101E"},
+	{ RL_HWREV_8102E, RL_8169, "8102E"},
+	{ RL_HWREV_8102EL, RL_8169, "8102EL"},
+	{ RL_HWREV_8168_SPIN2, RL_8169, "8168"},
+	{ RL_HWREV_8168_SPIN3, RL_8169, "8168"},
+	{ RL_HWREV_8168C, RL_8169, "8168C/8111C"},
+	{ RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
+	{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
+	{ 0, 0, NULL }
+};
+
+static int re_probe		(device_t);
+static int re_attach		(device_t);
+static int re_detach		(device_t);
+
+static struct mbuf *re_defrag	(struct mbuf *, int, int);
+static int re_encap		(struct rl_softc *, struct mbuf **);
+
+static void re_dma_map_addr	(void *, bus_dma_segment_t *, int, int);
+static int re_allocmem		(device_t, struct rl_softc *);
+static __inline void re_discard_rxbuf
+				(struct rl_softc *, int);
+static int re_newbuf		(struct rl_softc *, int);
+static int re_rx_list_init	(struct rl_softc *);
+static int re_tx_list_init	(struct rl_softc *);
+#ifdef RE_FIXUP_RX
+static __inline void re_fixup_rx
+				(struct mbuf *);
+#endif
+static int re_rxeof		(struct rl_softc *);
+static void re_txeof		(struct rl_softc *);
+#ifdef DEVICE_POLLING
+static void re_poll		(struct ifnet *, enum poll_cmd, int);
+static void re_poll_locked	(struct ifnet *, enum poll_cmd, int);
+#endif
+static int re_intr		(void *);
+static void re_tick		(void *);
+static void re_tx_task		(void *, int);
+static void re_int_task		(void *, int);
+static void re_start		(struct ifnet *);
+static int re_ioctl		(struct ifnet *, u_long, caddr_t);
+static void re_init		(void *);
+static void re_init_locked	(struct rl_softc *);
+static void re_stop		(struct rl_softc *);
+static void re_watchdog		(struct rl_softc *);
+static int re_suspend		(device_t);
+static int re_resume		(device_t);
+static int re_shutdown		(device_t);
+static int re_ifmedia_upd	(struct ifnet *);
+static void re_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
+
+static void re_eeprom_putbyte	(struct rl_softc *, int);
+static void re_eeprom_getword	(struct rl_softc *, int, u_int16_t *);
+static void re_read_eeprom	(struct rl_softc *, caddr_t, int, int);
+static int re_gmii_readreg	(device_t, int, int);
+static int re_gmii_writereg	(device_t, int, int, int);
+
+static int re_miibus_readreg	(device_t, int, int);
+static int re_miibus_writereg	(device_t, int, int, int);
+static void re_miibus_statchg	(device_t);
+
+static void re_setmulti		(struct rl_softc *);
+static void re_reset		(struct rl_softc *);
+static void re_setwol		(struct rl_softc *);
+static void re_clrwol		(struct rl_softc *);
+
+#ifdef RE_DIAG
+static int re_diag		(struct rl_softc *);
+#endif
+
+static device_method_t re_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		re_probe),
+	DEVMETHOD(device_attach,	re_attach),
+	DEVMETHOD(device_detach,	re_detach),
+	DEVMETHOD(device_suspend,	re_suspend),
+	DEVMETHOD(device_resume,	re_resume),
+	DEVMETHOD(device_shutdown,	re_shutdown),
+
+	/* bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	re_miibus_readreg),
+	DEVMETHOD(miibus_writereg,	re_miibus_writereg),
+	DEVMETHOD(miibus_statchg,	re_miibus_statchg),
+
+	{ 0, 0 }
+};
+
+static driver_t re_driver = {
+	"re",
+	re_methods,
+	sizeof(struct rl_softc)
+};
+
+static devclass_t re_devclass;
+
+DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
+DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
+DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
+
+#define EE_SET(x)					\
+	CSR_WRITE_1(sc, RL_EECMD,			\
+		CSR_READ_1(sc, RL_EECMD) | x)
+
+#define EE_CLR(x)					\
+	CSR_WRITE_1(sc, RL_EECMD,			\
+		CSR_READ_1(sc, RL_EECMD) & ~x)
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void
+re_eeprom_putbyte(struct rl_softc *sc, int addr)
+{
+	int			d, i;
+
+	d = addr | (RL_9346_READ << sc->rl_eewidth);
+
+	/*
+	 * Feed in each bit and strobe the clock.
+	 */
+
+	for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
+		if (d & i) {
+			EE_SET(RL_EE_DATAIN);
+		} else {
+			EE_CLR(RL_EE_DATAIN);
+		}
+		DELAY(100);
+		EE_SET(RL_EE_CLK);
+		DELAY(150);
+		EE_CLR(RL_EE_CLK);
+		DELAY(100);
+	}
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void
+re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
+{
+	int			i;
+	u_int16_t		word = 0;
+
+	/*
+	 * Send address of word we want to read.
+	 */
+	re_eeprom_putbyte(sc, addr);
+
+	/*
+	 * Start reading bits from EEPROM.
+	 */
+	for (i = 0x8000; i; i >>= 1) {
+		EE_SET(RL_EE_CLK);
+		DELAY(100);
+		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
+			word |= i;
+		EE_CLR(RL_EE_CLK);
+		DELAY(100);
+	}
+
+	*dest = word;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void
+re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
+{
+	int			i;
+	u_int16_t		word = 0, *ptr;
+
+	CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
+
+        DELAY(100);
+
+	for (i = 0; i < cnt; i++) {
+		CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
+		re_eeprom_getword(sc, off + i, &word);
+		CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
+		ptr = (u_int16_t *)(dest + (i * 2));
+                *ptr = word;
+	}
+
+	CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
+}
+
+static int
+re_gmii_readreg(device_t dev, int phy, int reg)
+{
+	struct rl_softc		*sc;
+	u_int32_t		rval;
+	int			i;
+
+	if (phy != 1)
+		return (0);
+
+	sc = device_get_softc(dev);
+
+	/* Let the rgephy driver read the GMEDIASTAT register */
+
+	if (reg == RL_GMEDIASTAT) {
+		rval = CSR_READ_1(sc, RL_GMEDIASTAT);
+		return (rval);
+	}
+
+	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
+	DELAY(1000);
+
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		rval = CSR_READ_4(sc, RL_PHYAR);
+		if (rval & RL_PHYAR_BUSY)
+			break;
+		DELAY(100);
+	}
+
+	if (i == RL_TIMEOUT) {
+		device_printf(sc->rl_dev, "PHY read failed\n");
+		return (0);
+	}
+
+	return (rval & RL_PHYAR_PHYDATA);
+}
+
+static int
+re_gmii_writereg(device_t dev, int phy, int reg, int data)
+{
+	struct rl_softc		*sc;
+	u_int32_t		rval;
+	int			i;
+
+	sc = device_get_softc(dev);
+
+	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
+	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
+	DELAY(1000);
+
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		rval = CSR_READ_4(sc, RL_PHYAR);
+		if (!(rval & RL_PHYAR_BUSY))
+			break;
+		DELAY(100);
+	}
+
+	if (i == RL_TIMEOUT) {
+		device_printf(sc->rl_dev, "PHY write failed\n");
+		return (0);
+	}
+
+	return (0);
+}
+
+static int
+re_miibus_readreg(device_t dev, int phy, int reg)
+{
+	struct rl_softc		*sc;
+	u_int16_t		rval = 0;
+	u_int16_t		re8139_reg = 0;
+
+	sc = device_get_softc(dev);
+
+	if (sc->rl_type == RL_8169) {
+		rval = re_gmii_readreg(dev, phy, reg);
+		return (rval);
+	}
+
+	/* Pretend the internal PHY is only at address 0 */
+	if (phy) {
+		return (0);
+	}
+	switch (reg) {
+	case MII_BMCR:
+		re8139_reg = RL_BMCR;
+		break;
+	case MII_BMSR:
+		re8139_reg = RL_BMSR;
+		break;
+	case MII_ANAR:
+		re8139_reg = RL_ANAR;
+		break;
+	case MII_ANER:
+		re8139_reg = RL_ANER;
+		break;
+	case MII_ANLPAR:
+		re8139_reg = RL_LPAR;
+		break;
+	case MII_PHYIDR1:
+	case MII_PHYIDR2:
+		return (0);
+	/*
+	 * Allow the rlphy driver to read the media status
+	 * register. If we have a link partner which does not
+	 * support NWAY, this is the register which will tell
+	 * us the results of parallel detection.
+	 */
+	case RL_MEDIASTAT:
+		rval = CSR_READ_1(sc, RL_MEDIASTAT);
+		return (rval);
+	default:
+		device_printf(sc->rl_dev, "bad phy register\n");
+		return (0);
+	}
+	rval = CSR_READ_2(sc, re8139_reg);
+	if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
+		/* 8139C+ has different bit layout. */
+		rval &= ~(BMCR_LOOP | BMCR_ISO);
+	}
+	return (rval);
+}
+
+static int
+re_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+	struct rl_softc		*sc;
+	u_int16_t		re8139_reg = 0;
+	int			rval = 0;
+
+	sc = device_get_softc(dev);
+
+	if (sc->rl_type == RL_8169) {
+		rval = re_gmii_writereg(dev, phy, reg, data);
+		return (rval);
+	}
+
+	/* Pretend the internal PHY is only at address 0 */
+	if (phy)
+		return (0);
+
+	switch (reg) {
+	case MII_BMCR:
+		re8139_reg = RL_BMCR;
+		if (sc->rl_type == RL_8139CPLUS) {
+			/* 8139C+ has different bit layout. */
+			data &= ~(BMCR_LOOP | BMCR_ISO);
+		}
+		break;
+	case MII_BMSR:
+		re8139_reg = RL_BMSR;
+		break;
+	case MII_ANAR:
+		re8139_reg = RL_ANAR;
+		break;
+	case MII_ANER:
+		re8139_reg = RL_ANER;
+		break;
+	case MII_ANLPAR:
+		re8139_reg = RL_LPAR;
+		break;
+	case MII_PHYIDR1:
+	case MII_PHYIDR2:
+		return (0);
+		break;
+	default:
+		device_printf(sc->rl_dev, "bad phy register\n");
+		return (0);
+	}
+	CSR_WRITE_2(sc, re8139_reg, data);
+	return (0);
+}
+
+static void
+re_miibus_statchg(device_t dev)
+{
+
+}
+
+/*
+ * Program the 64-bit multicast hash filter.
+ */
+static void
+re_setmulti(struct rl_softc *sc)
+{
+	struct ifnet		*ifp;
+	int			h = 0;
+	u_int32_t		hashes[2] = { 0, 0 };
+	struct ifmultiaddr	*ifma;
+	u_int32_t		rxfilt;
+	int			mcnt = 0;
+
+	RL_LOCK_ASSERT(sc);
+
+	ifp = sc->rl_ifp;
+
+
+	rxfilt = CSR_READ_4(sc, RL_RXCFG);
+	rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI);
+	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+		if (ifp->if_flags & IFF_PROMISC)
+			rxfilt |= RL_RXCFG_RX_ALLPHYS;
+		/*
+		 * Unlike other hardwares, we have to explicitly set
+		 * RL_RXCFG_RX_MULTI to receive multicast frames in
+		 * promiscuous mode.
+		 */
+		rxfilt |= RL_RXCFG_RX_MULTI;
+		CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
+		CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
+		CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
+		return;
+	}
+
+	/* first, zot all the existing hash bits */
+	CSR_WRITE_4(sc, RL_MAR0, 0);
+	CSR_WRITE_4(sc, RL_MAR4, 0);
+
+	/* now program new ones */
+	IF_ADDR_LOCK(ifp);
+	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+		if (ifma->ifma_addr->sa_family != AF_LINK)
+			continue;
+		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
+		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
+		if (h < 32)
+			hashes[0] |= (1 << h);
+		else
+			hashes[1] |= (1 << (h - 32));
+		mcnt++;
+	}
+	IF_ADDR_UNLOCK(ifp);
+
+	if (mcnt)
+		rxfilt |= RL_RXCFG_RX_MULTI;
+	else
+		rxfilt &= ~RL_RXCFG_RX_MULTI;
+
+	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
+
+	/*
+	 * For some unfathomable reason, RealTek decided to reverse
+	 * the order of the multicast hash registers in the PCI Express
+	 * parts. This means we have to write the hash pattern in reverse
+	 * order for those devices.
+	 */
+
+	if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) {
+		CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1]));
+		CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0]));
+	} else {
+		CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
+		CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
+	}
+}
+
+static void
+re_reset(struct rl_softc *sc)
+{
+	int			i;
+
+	RL_LOCK_ASSERT(sc);
+
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
+
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		DELAY(10);
+		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
+			break;
+	}
+	if (i == RL_TIMEOUT)
+		device_printf(sc->rl_dev, "reset never completed!\n");
+
+	CSR_WRITE_1(sc, 0x82, 1);
+}
+
+#ifdef RE_DIAG
+
+/*
+ * The following routine is designed to test for a defect on some
+ * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
+ * lines connected to the bus, however for a 32-bit only card, they
+ * should be pulled high. The result of this defect is that the
+ * NIC will not work right if you plug it into a 64-bit slot: DMA
+ * operations will be done with 64-bit transfers, which will fail
+ * because the 64-bit data lines aren't connected.
+ *
+ * There's no way to work around this (short of talking a soldering
+ * iron to the board), however we can detect it. The method we use
+ * here is to put the NIC into digital loopback mode, set the receiver
+ * to promiscuous mode, and then try to send a frame. We then compare
+ * the frame data we sent to what was received. If the data matches,
+ * then the NIC is working correctly, otherwise we know the user has
+ * a defective NIC which has been mistakenly plugged into a 64-bit PCI
+ * slot. In the latter case, there's no way the NIC can work correctly,
+ * so we print out a message on the console and abort the device attach.
+ */
+
+static int
+re_diag(struct rl_softc *sc)
+{
+	struct ifnet		*ifp = sc->rl_ifp;
+	struct mbuf		*m0;
+	struct ether_header	*eh;
+	struct rl_desc		*cur_rx;
+	u_int16_t		status;
+	u_int32_t		rxstat;
+	int			total_len, i, error = 0, phyaddr;
+	u_int8_t		dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
+	u_int8_t		src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
+
+	/* Allocate a single mbuf */
+	MGETHDR(m0, M_DONTWAIT, MT_DATA);
+	if (m0 == NULL)
+		return (ENOBUFS);
+
+	RL_LOCK(sc);
+
+	/*
+	 * Initialize the NIC in test mode. This sets the chip up
+	 * so that it can send and receive frames, but performs the
+	 * following special functions:
+	 * - Puts receiver in promiscuous mode
+	 * - Enables digital loopback mode
+	 * - Leaves interrupts turned off
+	 */
+
+	ifp->if_flags |= IFF_PROMISC;
+	sc->rl_testmode = 1;
+	re_reset(sc);
+	re_init_locked(sc);
+	sc->rl_flags |= RL_FLAG_LINK;
+	if (sc->rl_type == RL_8169)
+		phyaddr = 1;
+	else
+		phyaddr = 0;
+
+	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
+		if (!(status & BMCR_RESET))
+			break;
+	}
+
+	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
+	CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
+
+	DELAY(100000);
+
+	/* Put some data in the mbuf */
+
+	eh = mtod(m0, struct ether_header *);
+	bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
+	bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
+	eh->ether_type = htons(ETHERTYPE_IP);
+	m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
+
+	/*
+	 * Queue the packet, start transmission.
+	 * Note: IF_HANDOFF() ultimately calls re_start() for us.
+	 */
+
+	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
+	RL_UNLOCK(sc);
+	/* XXX: re_diag must not be called when in ALTQ mode */
+	IF_HANDOFF(&ifp->if_snd, m0, ifp);
+	RL_LOCK(sc);
+	m0 = NULL;
+
+	/* Wait for it to propagate through the chip */
+
+	DELAY(100000);
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		status = CSR_READ_2(sc, RL_ISR);
+		CSR_WRITE_2(sc, RL_ISR, status);
+		if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
+		    (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
+			break;
+		DELAY(10);
+	}
+
+	if (i == RL_TIMEOUT) {
+		device_printf(sc->rl_dev,
+		    "diagnostic failed, failed to receive packet in"
+		    " loopback mode\n");
+		error = EIO;
+		goto done;
+	}
+
+	/*
+	 * The packet should have been dumped into the first
+	 * entry in the RX DMA ring. Grab it from there.
+	 */
+
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
+	    sc->rl_ldata.rl_rx_list_map,
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
+	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
+	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
+
+	m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
+	sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
+	eh = mtod(m0, struct ether_header *);
+
+	cur_rx = &sc->rl_ldata.rl_rx_list[0];
+	total_len = RL_RXBYTES(cur_rx);
+	rxstat = le32toh(cur_rx->rl_cmdstat);
+
+	if (total_len != ETHER_MIN_LEN) {
+		device_printf(sc->rl_dev,
+		    "diagnostic failed, received short packet\n");
+		error = EIO;
+		goto done;
+	}
+
+	/* Test that the received packet data matches what we sent. */
+
+	if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
+	    bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
+	    ntohs(eh->ether_type) != ETHERTYPE_IP) {
+		device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
+		device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
+		    dst, ":", src, ":", ETHERTYPE_IP);
+		device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
+		    eh->ether_dhost, ":",  eh->ether_shost, ":",
+		    ntohs(eh->ether_type));
+		device_printf(sc->rl_dev, "You may have a defective 32-bit "
+		    "NIC plugged into a 64-bit PCI slot.\n");
+		device_printf(sc->rl_dev, "Please re-install the NIC in a "
+		    "32-bit slot for proper operation.\n");
+		device_printf(sc->rl_dev, "Read the re(4) man page for more "
+		    "details.\n");
+		error = EIO;
+	}
+
+done:
+	/* Turn interface off, release resources */
+
+	sc->rl_testmode = 0;
+	sc->rl_flags &= ~RL_FLAG_LINK;
+	ifp->if_flags &= ~IFF_PROMISC;
+	re_stop(sc);
+	if (m0 != NULL)
+		m_freem(m0);
+
+	RL_UNLOCK(sc);
+
+	return (error);
+}
+
+#endif
+
+/*
+ * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int
+re_probe(device_t dev)
+{
+	struct rl_type		*t;
+	uint16_t		devid, vendor;
+	uint16_t		revid, sdevid;
+	int			i;
+	
+	vendor = pci_get_vendor(dev);
+	devid = pci_get_device(dev);
+	revid = pci_get_revid(dev);
+	sdevid = pci_get_subdevice(dev);
+
+	if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
+		if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
+			/*
+			 * Only attach to rev. 3 of the Linksys EG1032 adapter.
+			 * Rev. 2 is supported by sk(4).
+			 */
+			return (ENXIO);
+		}
+	}
+
+	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
+		if (revid != 0x20) {
+			/* 8139, let rl(4) take care of this device. */
+			return (ENXIO);
+		}
+	}
+
+	t = re_devs;
+	for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
+		if (vendor == t->rl_vid && devid == t->rl_did) {
+			device_set_desc(dev, t->rl_name);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+
+	return (ENXIO);
+}
+
+/*
+ * Map a single buffer address.
+ */
+
+static void
+re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+	bus_addr_t		*addr;
+
+	if (error)
+		return;
+
+	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
+	addr = arg;
+	*addr = segs->ds_addr;
+}
+
+static int
+re_allocmem(device_t dev, struct rl_softc *sc)
+{
+	bus_size_t		rx_list_size, tx_list_size;
+	int			error;
+	int			i;
+
+	rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
+	tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
+
+	/*
+	 * Allocate the parent bus DMA tag appropriate for PCI.
+	 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
+	 * register should be set. However some RealTek chips are known
+	 * to be buggy on DAC handling, therefore disable DAC by limiting
+	 * DMA address space to 32bit. PCIe variants of RealTek chips
+	 * may not have the limitation but I took safer path.
+	 */
+	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
+	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
+	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
+	    NULL, NULL, &sc->rl_parent_tag);
+	if (error) {
+		device_printf(dev, "could not allocate parent DMA tag\n");
+		return (error);
+	}
+
+	/*
+	 * Allocate map for TX mbufs.
+	 */
+	error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
+	    NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
+	    NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
+	if (error) {
+		device_printf(dev, "could not allocate TX DMA tag\n");
+		return (error);
+	}
+
+	/*
+	 * Allocate map for RX mbufs.
+	 */
+
+	error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
+	if (error) {
+		device_printf(dev, "could not allocate RX DMA tag\n");
+		return (error);
+	}
+
+	/*
+	 * Allocate map for TX descriptor list.
+	 */
+	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
+	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
+	    NULL, tx_list_size, 1, tx_list_size, 0,
+	    NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
+	if (error) {
+		device_printf(dev, "could not allocate TX DMA ring tag\n");
+		return (error);
+	}
+
+	/* Allocate DMA'able memory for the TX ring */
+
+	error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
+	    (void **)&sc->rl_ldata.rl_tx_list,
+	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
+	    &sc->rl_ldata.rl_tx_list_map);
+	if (error) {
+		device_printf(dev, "could not allocate TX DMA ring\n");
+		return (error);
+	}
+
+	/* Load the map for the TX ring. */
+
+	sc->rl_ldata.rl_tx_list_addr = 0;
+	error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
+	     sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
+	     tx_list_size, re_dma_map_addr,
+	     &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
+	if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
+		device_printf(dev, "could not load TX DMA ring\n");
+		return (ENOMEM);
+	}
+
+	/* Create DMA maps for TX buffers */
+
+	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
+		error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
+		    &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
+		if (error) {
+			device_printf(dev, "could not create DMA map for TX\n");
+			return (error);
+		}
+	}
+
+	/*
+	 * Allocate map for RX descriptor list.
+	 */
+	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
+	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
+	    NULL, rx_list_size, 1, rx_list_size, 0,
+	    NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
+	if (error) {
+		device_printf(dev, "could not create RX DMA ring tag\n");
+		return (error);
+	}
+
+	/* Allocate DMA'able memory for the RX ring */
+
+	error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
+	    (void **)&sc->rl_ldata.rl_rx_list,
+	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
+	    &sc->rl_ldata.rl_rx_list_map);
+	if (error) {
+		device_printf(dev, "could not allocate RX DMA ring\n");
+		return (error);
+	}
+
+	/* Load the map for the RX ring. */
+
+	sc->rl_ldata.rl_rx_list_addr = 0;
+	error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
+	     sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
+	     rx_list_size, re_dma_map_addr,
+	     &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
+	if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
+		device_printf(dev, "could not load RX DMA ring\n");
+		return (ENOMEM);
+	}
+
+	/* Create DMA maps for RX buffers */
+
+	error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
+	    &sc->rl_ldata.rl_rx_sparemap);
+	if (error) {
+		device_printf(dev, "could not create spare DMA map for RX\n");
+		return (error);
+	}
+	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
+		error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
+		    &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
+		if (error) {
+			device_printf(dev, "could not create DMA map for RX\n");
+			return (error);
+		}
+	}
+
+	return (0);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static int
+re_attach(device_t dev)
+{
+	u_char			eaddr[ETHER_ADDR_LEN];
+	u_int16_t		as[ETHER_ADDR_LEN / 2];
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+	struct rl_hwrev		*hw_rev;
+	int			hwrev;
+	u_int16_t		devid, re_did = 0;
+	int			error = 0, rid, i;
+	int			msic, reg;
+	uint8_t			cfg;
+
+	sc = device_get_softc(dev);
+	sc->rl_dev = dev;
+
+	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+	    MTX_DEF);
+	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
+
+	/*
+	 * Map control/status registers.
+	 */
+	pci_enable_busmaster(dev);
+
+	devid = pci_get_device(dev);
+	/* Prefer memory space register mapping over IO space. */
+	sc->rl_res_id = PCIR_BAR(1);
+	sc->rl_res_type = SYS_RES_MEMORY;
+	/* RTL8168/8101E seems to use different BARs. */
+	if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
+		sc->rl_res_id = PCIR_BAR(2);
+	sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
+	    &sc->rl_res_id, RF_ACTIVE);
+
+	if (sc->rl_res == NULL) {
+		sc->rl_res_id = PCIR_BAR(0);
+		sc->rl_res_type = SYS_RES_IOPORT;
+		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
+		    &sc->rl_res_id, RF_ACTIVE);
+		if (sc->rl_res == NULL) {
+			device_printf(dev, "couldn't map ports/memory\n");
+			error = ENXIO;
+			goto fail;
+		}
+	}
+
+	sc->rl_btag = rman_get_bustag(sc->rl_res);
+	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
+
+	msic = 0;
+	if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
+		msic = pci_msi_count(dev);
+		if (bootverbose)
+			device_printf(dev, "MSI count : %d\n", msic);
+	}
+	if (msic == RL_MSI_MESSAGES  && msi_disable == 0) {
+		if (pci_alloc_msi(dev, &msic) == 0) {
+			if (msic == RL_MSI_MESSAGES) {
+				device_printf(dev, "Using %d MSI messages\n",
+				    msic);
+				sc->rl_flags |= RL_FLAG_MSI;
+				/* Explicitly set MSI enable bit. */
+				CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+				cfg = CSR_READ_1(sc, RL_CFG2);
+				cfg |= RL_CFG2_MSI;
+				CSR_WRITE_1(sc, RL_CFG2, cfg);
+				CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+			} else
+				pci_release_msi(dev);
+		}
+	}
+
+	/* Allocate interrupt */
+	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
+		rid = 0;
+		sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+		    RF_SHAREABLE | RF_ACTIVE);
+		if (sc->rl_irq[0] == NULL) {
+			device_printf(dev, "couldn't allocate IRQ resources\n");
+			error = ENXIO;
+			goto fail;
+		}
+	} else {
+		for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
+			sc->rl_irq[i] = bus_alloc_resource_any(dev,
+			    SYS_RES_IRQ, &rid, RF_ACTIVE);
+			if (sc->rl_irq[i] == NULL) {
+				device_printf(dev,
+				    "couldn't llocate IRQ resources for "
+				    "message %d\n", rid);
+				error = ENXIO;
+				goto fail;
+			}
+		}
+	}
+
+	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
+		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+		cfg = CSR_READ_1(sc, RL_CFG2);
+		if ((cfg & RL_CFG2_MSI) != 0) {
+			device_printf(dev, "turning off MSI enable bit.\n");
+			cfg &= ~RL_CFG2_MSI;
+			CSR_WRITE_1(sc, RL_CFG2, cfg);
+		}
+		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+	}
+
+	/* Reset the adapter. */
+	RL_LOCK(sc);
+	re_reset(sc);
+	RL_UNLOCK(sc);
+
+	hw_rev = re_hwrevs;
+	hwrev = CSR_READ_4(sc, RL_TXCFG);
+	device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
+	device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
+	hwrev &= RL_TXCFG_HWREV;
+	while (hw_rev->rl_desc != NULL) {
+		if (hw_rev->rl_rev == hwrev) {
+			sc->rl_type = hw_rev->rl_type;
+			break;
+		}
+		hw_rev++;
+	}
+	if (hw_rev->rl_desc == NULL) {
+		device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
+		error = ENXIO;
+		goto fail;
+	}
+
+	switch (hw_rev->rl_rev) {
+	case RL_HWREV_8139CPLUS:
+		sc->rl_flags |= RL_FLAG_NOJUMBO;
+		break;
+	case RL_HWREV_8100E:
+	case RL_HWREV_8101E:
+		sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
+		    RL_FLAG_PHYWAKE;
+		break;
+	case RL_HWREV_8102E:
+	case RL_HWREV_8102EL:
+		sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
+		    RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
+		    RL_FLAG_MACSTAT;
+		break;
+	case RL_HWREV_8168_SPIN1:
+	case RL_HWREV_8168_SPIN2:
+	case RL_HWREV_8168_SPIN3:
+		sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
+		    RL_FLAG_MACSTAT;
+		break;
+	case RL_HWREV_8168C:
+	case RL_HWREV_8168C_SPIN2:
+	case RL_HWREV_8168CP:
+		sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
+		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT;
+		/*
+		 * These controllers support jumbo frame but it seems
+		 * that enabling it requires touching additional magic
+		 * registers. Depending on MAC revisions some
+		 * controllers need to disable checksum offload. So
+		 * disable jumbo frame until I have better idea what
+		 * it really requires to make it support.
+		 * RTL8168C/CP : supports up to 6KB jumbo frame.
+		 * RTL8111C/CP : supports up to 9KB jumbo frame.
+		 */
+		sc->rl_flags |= RL_FLAG_NOJUMBO;
+		break;
+	case RL_HWREV_8169_8110SB:
+	case RL_HWREV_8169_8110SC:
+	case RL_HWREV_8169_8110SBL:
+		sc->rl_flags |= RL_FLAG_PHYWAKE;
+		break;
+	default:
+		break;
+	}
+
+	/* Enable PME. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+	cfg = CSR_READ_1(sc, RL_CFG1);
+	cfg |= RL_CFG1_PME;
+	CSR_WRITE_1(sc, RL_CFG1, cfg);
+	cfg = CSR_READ_1(sc, RL_CFG5);
+	cfg &= RL_CFG5_PME_STS;
+	CSR_WRITE_1(sc, RL_CFG5, cfg);
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
+		/*
+		 * XXX Should have a better way to extract station
+		 * address from EEPROM.
+		 */
+		for (i = 0; i < ETHER_ADDR_LEN; i++)
+			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
+	} else {
+		sc->rl_eewidth = RL_9356_ADDR_LEN;
+		re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
+		if (re_did != 0x8129)
+			sc->rl_eewidth = RL_9346_ADDR_LEN;
+
+		/*
+		 * Get station address from the EEPROM.
+		 */
+		re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
+		for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
+			as[i] = le16toh(as[i]);
+		bcopy(as, eaddr, sizeof(eaddr));
+	}
+
+	if (sc->rl_type == RL_8169) {
+		/* Set RX length mask and number of descriptors. */
+		sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
+		sc->rl_txstart = RL_GTXSTART;
+		sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
+		sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
+	} else {
+		/* Set RX length mask and number of descriptors. */
+		sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
+		sc->rl_txstart = RL_TXSTART;
+		sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
+		sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
+	}
+
+	error = re_allocmem(dev, sc);
+	if (error)
+		goto fail;
+
+	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
+	if (ifp == NULL) {
+		device_printf(dev, "can not if_alloc()\n");
+		error = ENOSPC;
+		goto fail;
+	}
+
+	/* Take PHY out of power down mode. */
+	if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
+		re_gmii_writereg(dev, 1, 0x1f, 0);
+		re_gmii_writereg(dev, 1, 0x0e, 0);
+	}
+
+	/* Do MII setup */
+	if (mii_phy_probe(dev, &sc->rl_miibus,
+	    re_ifmedia_upd, re_ifmedia_sts)) {
+		device_printf(dev, "MII without any phy!\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	ifp->if_softc = sc;
+	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = re_ioctl;
+	ifp->if_start = re_start;
+	ifp->if_hwassist = RE_CSUM_FEATURES;
+	ifp->if_capabilities = IFCAP_HWCSUM;
+	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_init = re_init;
+	IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
+	ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
+	IFQ_SET_READY(&ifp->if_snd);
+
+	TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
+	TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
+
+	/*
+	 * XXX
+	 * Still have no idea how to make TSO work on 8168C, 8168CP,
+	 * 8111C and 8111CP.
+	 */
+	if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
+		ifp->if_hwassist |= CSUM_TSO;
+		ifp->if_capabilities |= IFCAP_TSO4;
+	}
+
+	/*
+	 * Call MI attach routine.
+	 */
+	ether_ifattach(ifp, eaddr);
+
+	/* VLAN capability setup */
+	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
+	if (ifp->if_capabilities & IFCAP_HWCSUM)
+		ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
+#ifdef ENABLE_WOL
+	/* Enable WOL if PM is supported. */
+	if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &reg) == 0)
+		ifp->if_capabilities |= IFCAP_WOL;
+#endif
+	ifp->if_capenable = ifp->if_capabilities;
+	/*
+	 * Don't enable TSO by default. Under certain
+	 * circumtances the controller generated corrupted
+	 * packets in TSO size.
+	 */
+	ifp->if_hwassist &= ~CSUM_TSO;
+	ifp->if_capenable &= ~IFCAP_TSO4;
+#ifdef DEVICE_POLLING
+	ifp->if_capabilities |= IFCAP_POLLING;
+#endif
+	/*
+	 * Tell the upper layer(s) we support long frames.
+	 * Must appear after the call to ether_ifattach() because
+	 * ether_ifattach() sets ifi_hdrlen to the default value.
+	 */
+	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
+
+#ifdef RE_DIAG
+	/*
+	 * Perform hardware diagnostic on the original RTL8169.
+	 * Some 32-bit cards were incorrectly wired and would
+	 * malfunction if plugged into a 64-bit slot.
+	 */
+
+	if (hwrev == RL_HWREV_8169) {
+		error = re_diag(sc);
+		if (error) {
+			device_printf(dev,
+		    	"attach aborted due to hardware diag failure\n");
+			ether_ifdetach(ifp);
+			goto fail;
+		}
+	}
+#endif
+
+	/* Hook interrupt last to avoid having to lock softc */
+	if ((sc->rl_flags & RL_FLAG_MSI) == 0)
+		error = bus_setup_intr(dev, sc->rl_irq[0],
+		    INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
+		    &sc->rl_intrhand[0]);
+	else {
+		for (i = 0; i < RL_MSI_MESSAGES; i++) {
+			error = bus_setup_intr(dev, sc->rl_irq[i],
+			    INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
+		    	    &sc->rl_intrhand[i]);
+			if (error != 0)
+				break;
+		}
+	}
+	if (error) {
+		device_printf(dev, "couldn't set up irq\n");
+		ether_ifdetach(ifp);
+	}
+
+fail:
+
+	if (error)
+		re_detach(dev);
+
+	return (error);
+}
+
+/*
+ * Shutdown hardware and free up resources. This can be called any
+ * time after the mutex has been initialized. It is called in both
+ * the error case in attach and the normal detach case so it needs
+ * to be careful about only freeing resources that have actually been
+ * allocated.
+ */
+static int
+re_detach(device_t dev)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+	int			i, rid;
+
+	sc = device_get_softc(dev);
+	ifp = sc->rl_ifp;
+	KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
+
+	/* These should only be active if attach succeeded */
+	if (device_is_attached(dev)) {
+#ifdef DEVICE_POLLING
+		if (ifp->if_capenable & IFCAP_POLLING)
+			ether_poll_deregister(ifp);
+#endif
+		RL_LOCK(sc);
+#if 0
+		sc->suspended = 1;
+#endif
+		re_stop(sc);
+		RL_UNLOCK(sc);
+		callout_drain(&sc->rl_stat_callout);
+		taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
+		taskqueue_drain(taskqueue_fast, &sc->rl_txtask);
+		/*
+		 * Force off the IFF_UP flag here, in case someone
+		 * still had a BPF descriptor attached to this
+		 * interface. If they do, ether_ifdetach() will cause
+		 * the BPF code to try and clear the promisc mode
+		 * flag, which will bubble down to re_ioctl(),
+		 * which will try to call re_init() again. This will
+		 * turn the NIC back on and restart the MII ticker,
+		 * which will panic the system when the kernel tries
+		 * to invoke the re_tick() function that isn't there
+		 * anymore.
+		 */
+		ifp->if_flags &= ~IFF_UP;
+		ether_ifdetach(ifp);
+	}
+	if (sc->rl_miibus)
+		device_delete_child(dev, sc->rl_miibus);
+	bus_generic_detach(dev);
+
+	/*
+	 * The rest is resource deallocation, so we should already be
+	 * stopped here.
+	 */
+
+	for (i = 0; i < RL_MSI_MESSAGES; i++) {
+		if (sc->rl_intrhand[i] != NULL) {
+			bus_teardown_intr(dev, sc->rl_irq[i],
+			    sc->rl_intrhand[i]);
+			sc->rl_intrhand[i] = NULL;
+		}
+	}
+	if (ifp != NULL)
+		if_free(ifp);
+	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
+		if (sc->rl_irq[0] != NULL) {
+			bus_release_resource(dev, SYS_RES_IRQ, 0,
+			    sc->rl_irq[0]);
+			sc->rl_irq[0] = NULL;
+		}
+	} else {
+		for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
+			if (sc->rl_irq[i] != NULL) {
+				bus_release_resource(dev, SYS_RES_IRQ, rid,
+				    sc->rl_irq[i]);
+				sc->rl_irq[i] = NULL;
+			}
+		}
+		pci_release_msi(dev);
+	}
+	if (sc->rl_res)
+		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
+		    sc->rl_res);
+
+	/* Unload and free the RX DMA ring memory and map */
+
+	if (sc->rl_ldata.rl_rx_list_tag) {
+		bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
+		    sc->rl_ldata.rl_rx_list_map);
+		bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
+		    sc->rl_ldata.rl_rx_list,
+		    sc->rl_ldata.rl_rx_list_map);
+		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
+	}
+
+	/* Unload and free the TX DMA ring memory and map */
+
+	if (sc->rl_ldata.rl_tx_list_tag) {
+		bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
+		    sc->rl_ldata.rl_tx_list_map);
+		bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
+		    sc->rl_ldata.rl_tx_list,
+		    sc->rl_ldata.rl_tx_list_map);
+		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
+	}
+
+	/* Destroy all the RX and TX buffer maps */
+
+	if (sc->rl_ldata.rl_tx_mtag) {
+		for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
+			bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
+			    sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
+		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
+	}
+	if (sc->rl_ldata.rl_rx_mtag) {
+		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++)
+			bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
+			    sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
+		if (sc->rl_ldata.rl_rx_sparemap)
+			bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
+			    sc->rl_ldata.rl_rx_sparemap);
+		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
+	}
+
+	/* Unload and free the stats buffer and map */
+
+	if (sc->rl_ldata.rl_stag) {
+		bus_dmamap_unload(sc->rl_ldata.rl_stag,
+		    sc->rl_ldata.rl_rx_list_map);
+		bus_dmamem_free(sc->rl_ldata.rl_stag,
+		    sc->rl_ldata.rl_stats,
+		    sc->rl_ldata.rl_smap);
+		bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
+	}
+
+	if (sc->rl_parent_tag)
+		bus_dma_tag_destroy(sc->rl_parent_tag);
+
+	mtx_destroy(&sc->rl_mtx);
+
+	return (0);
+}
+
+static __inline void
+re_discard_rxbuf(struct rl_softc *sc, int idx)
+{
+	struct rl_desc		*desc;
+	struct rl_rxdesc	*rxd;
+	uint32_t		cmdstat;
+
+	rxd = &sc->rl_ldata.rl_rx_desc[idx];
+	desc = &sc->rl_ldata.rl_rx_list[idx];
+	desc->rl_vlanctl = 0;
+	cmdstat = rxd->rx_size;
+	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
+		cmdstat |= RL_RDESC_CMD_EOR;
+	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
+}
+
+static int
+re_newbuf(struct rl_softc *sc, int idx)
+{
+	struct mbuf		*m;
+	struct rl_rxdesc	*rxd;
+	bus_dma_segment_t	segs[1];
+	bus_dmamap_t		map;
+	struct rl_desc		*desc;
+	uint32_t		cmdstat;
+	int			error, nsegs;
+
+	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+	if (m == NULL)
+		return (ENOBUFS);
+
+	m->m_len = m->m_pkthdr.len = MCLBYTES;
+#ifdef RE_FIXUP_RX
+	/*
+	 * This is part of an evil trick to deal with non-x86 platforms.
+	 * The RealTek chip requires RX buffers to be aligned on 64-bit
+	 * boundaries, but that will hose non-x86 machines. To get around
+	 * this, we leave some empty space at the start of each buffer
+	 * and for non-x86 hosts, we copy the buffer back six bytes
+	 * to achieve word alignment. This is slightly more efficient
+	 * than allocating a new buffer, copying the contents, and
+	 * discarding the old buffer.
+	 */
+	m_adj(m, RE_ETHER_ALIGN);
+#endif
+	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
+	    sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
+	if (error != 0) {
+		m_freem(m);
+		return (ENOBUFS);
+	}
+	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
+
+	rxd = &sc->rl_ldata.rl_rx_desc[idx];
+	if (rxd->rx_m != NULL) {
+		bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
+	}
+
+	rxd->rx_m = m;
+	map = rxd->rx_dmamap;
+	rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
+	rxd->rx_size = segs[0].ds_len;
+	sc->rl_ldata.rl_rx_sparemap = map;
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
+	    BUS_DMASYNC_PREREAD);
+
+	desc = &sc->rl_ldata.rl_rx_list[idx];
+	desc->rl_vlanctl = 0;
+	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
+	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
+	cmdstat = segs[0].ds_len;
+	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
+		cmdstat |= RL_RDESC_CMD_EOR;
+	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
+
+	return (0);
+}
+
+#ifdef RE_FIXUP_RX
+static __inline void
+re_fixup_rx(struct mbuf *m)
+{
+	int                     i;
+	uint16_t                *src, *dst;
+
+	src = mtod(m, uint16_t *);
+	dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
+
+	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
+		*dst++ = *src++;
+
+	m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
+}
+#endif
+
+static int
+re_tx_list_init(struct rl_softc *sc)
+{
+	struct rl_desc		*desc;
+	int			i;
+
+	RL_LOCK_ASSERT(sc);
+
+	bzero(sc->rl_ldata.rl_tx_list,
+	    sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
+	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
+		sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
+	/* Set EOR. */
+	desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
+	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
+
+	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
+	    sc->rl_ldata.rl_tx_list_map,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	sc->rl_ldata.rl_tx_prodidx = 0;
+	sc->rl_ldata.rl_tx_considx = 0;
+	sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
+
+	return (0);
+}
+
+static int
+re_rx_list_init(struct rl_softc *sc)
+{
+	int			error, i;
+
+	bzero(sc->rl_ldata.rl_rx_list,
+	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
+	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
+		sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
+		if ((error = re_newbuf(sc, i)) != 0)
+			return (error);
+	}
+
+	/* Flush the RX descriptors */
+
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
+	    sc->rl_ldata.rl_rx_list_map,
+	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
+
+	sc->rl_ldata.rl_rx_prodidx = 0;
+	sc->rl_head = sc->rl_tail = NULL;
+
+	return (0);
+}
+
+/*
+ * RX handler for C+ and 8169. For the gigE chips, we support
+ * the reception of jumbo frames that have been fragmented
+ * across multiple 2K mbuf cluster buffers.
+ */
+static int
+re_rxeof(struct rl_softc *sc)
+{
+	struct mbuf		*m;
+	struct ifnet		*ifp;
+	int			i, total_len;
+	struct rl_desc		*cur_rx;
+	u_int32_t		rxstat, rxvlan;
+	int			maxpkt = 16;
+
+	RL_LOCK_ASSERT(sc);
+
+	ifp = sc->rl_ifp;
+
+	/* Invalidate the descriptor memory */
+
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
+	    sc->rl_ldata.rl_rx_list_map,
+	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
+	    i = RL_RX_DESC_NXT(sc, i)) {
+		cur_rx = &sc->rl_ldata.rl_rx_list[i];
+		rxstat = le32toh(cur_rx->rl_cmdstat);
+		if ((rxstat & RL_RDESC_STAT_OWN) != 0)
+			break;
+		total_len = rxstat & sc->rl_rxlenmask;
+		rxvlan = le32toh(cur_rx->rl_vlanctl);
+		m = sc->rl_ldata.rl_rx_desc[i].rx_m;
+
+		if (!(rxstat & RL_RDESC_STAT_EOF)) {
+			if (re_newbuf(sc, i) != 0) {
+				/*
+				 * If this is part of a multi-fragment packet,
+				 * discard all the pieces.
+				 */
+				if (sc->rl_head != NULL) {
+					m_freem(sc->rl_head);
+					sc->rl_head = sc->rl_tail = NULL;
+				}
+				re_discard_rxbuf(sc, i);
+				continue;
+			}
+			m->m_len = RE_RX_DESC_BUFLEN;
+			if (sc->rl_head == NULL)
+				sc->rl_head = sc->rl_tail = m;
+			else {
+				m->m_flags &= ~M_PKTHDR;
+				sc->rl_tail->m_next = m;
+				sc->rl_tail = m;
+			}
+			continue;
+		}
+
+		/*
+		 * NOTE: for the 8139C+, the frame length field
+		 * is always 12 bits in size, but for the gigE chips,
+		 * it is 13 bits (since the max RX frame length is 16K).
+		 * Unfortunately, all 32 bits in the status word
+		 * were already used, so to make room for the extra
+		 * length bit, RealTek took out the 'frame alignment
+		 * error' bit and shifted the other status bits
+		 * over one slot. The OWN, EOR, FS and LS bits are
+		 * still in the same places. We have already extracted
+		 * the frame length and checked the OWN bit, so rather
+		 * than using an alternate bit mapping, we shift the
+		 * status bits one space to the right so we can evaluate
+		 * them using the 8169 status as though it was in the
+		 * same format as that of the 8139C+.
+		 */
+		if (sc->rl_type == RL_8169)
+			rxstat >>= 1;
+
+		/*
+		 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
+		 * set, but if CRC is clear, it will still be a valid frame.
+		 */
+		if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
+		    (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
+			ifp->if_ierrors++;
+			/*
+			 * If this is part of a multi-fragment packet,
+			 * discard all the pieces.
+			 */
+			if (sc->rl_head != NULL) {
+				m_freem(sc->rl_head);
+				sc->rl_head = sc->rl_tail = NULL;
+			}
+			re_discard_rxbuf(sc, i);
+			continue;
+		}
+
+		/*
+		 * If allocating a replacement mbuf fails,
+		 * reload the current one.
+		 */
+
+		if (re_newbuf(sc, i) != 0) {
+			ifp->if_iqdrops++;
+			if (sc->rl_head != NULL) {
+				m_freem(sc->rl_head);
+				sc->rl_head = sc->rl_tail = NULL;
+			}
+			re_discard_rxbuf(sc, i);
+			continue;
+		}
+
+		if (sc->rl_head != NULL) {
+			m->m_len = total_len % RE_RX_DESC_BUFLEN;
+			if (m->m_len == 0)
+				m->m_len = RE_RX_DESC_BUFLEN;
+			/*
+			 * Special case: if there's 4 bytes or less
+			 * in this buffer, the mbuf can be discarded:
+			 * the last 4 bytes is the CRC, which we don't
+			 * care about anyway.
+			 */
+			if (m->m_len <= ETHER_CRC_LEN) {
+				sc->rl_tail->m_len -=
+				    (ETHER_CRC_LEN - m->m_len);
+				m_freem(m);
+			} else {
+				m->m_len -= ETHER_CRC_LEN;
+				m->m_flags &= ~M_PKTHDR;
+				sc->rl_tail->m_next = m;
+			}
+			m = sc->rl_head;
+			sc->rl_head = sc->rl_tail = NULL;
+			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
+		} else
+			m->m_pkthdr.len = m->m_len =
+			    (total_len - ETHER_CRC_LEN);
+
+#ifdef RE_FIXUP_RX
+		re_fixup_rx(m);
+#endif
+		ifp->if_ipackets++;
+		m->m_pkthdr.rcvif = ifp;
+
+		/* Do RX checksumming if enabled */
+
+		if (ifp->if_capenable & IFCAP_RXCSUM) {
+			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
+				/* Check IP header checksum */
+				if (rxstat & RL_RDESC_STAT_PROTOID)
+					m->m_pkthdr.csum_flags |=
+					    CSUM_IP_CHECKED;
+				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
+					m->m_pkthdr.csum_flags |=
+					    CSUM_IP_VALID;
+
+				/* Check TCP/UDP checksum */
+				if ((RL_TCPPKT(rxstat) &&
+				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
+				    (RL_UDPPKT(rxstat) &&
+				     !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
+					m->m_pkthdr.csum_flags |=
+						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
+					m->m_pkthdr.csum_data = 0xffff;
+				}
+			} else {
+				/*
+				 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
+				 */
+				if ((rxstat & RL_RDESC_STAT_PROTOID) &&
+				    (rxvlan & RL_RDESC_IPV4))
+					m->m_pkthdr.csum_flags |=
+					    CSUM_IP_CHECKED;
+				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
+				    (rxvlan & RL_RDESC_IPV4))
+					m->m_pkthdr.csum_flags |=
+					    CSUM_IP_VALID;
+				if (((rxstat & RL_RDESC_STAT_TCP) &&
+				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
+				    ((rxstat & RL_RDESC_STAT_UDP) &&
+				    !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
+					m->m_pkthdr.csum_flags |=
+						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
+					m->m_pkthdr.csum_data = 0xffff;
+				}
+			}
+		}
+		maxpkt--;
+		if (rxvlan & RL_RDESC_VLANCTL_TAG) {
+			m->m_pkthdr.ether_vtag =
+			    bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
+			m->m_flags |= M_VLANTAG;
+		}
+		RL_UNLOCK(sc);
+		(*ifp->if_input)(ifp, m);
+		RL_LOCK(sc);
+	}
+
+	/* Flush the RX DMA ring */
+
+	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
+	    sc->rl_ldata.rl_rx_list_map,
+	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
+
+	sc->rl_ldata.rl_rx_prodidx = i;
+
+	if (maxpkt)
+		return(EAGAIN);
+
+	return(0);
+}
+
+static void
+re_txeof(struct rl_softc *sc)
+{
+	struct ifnet		*ifp;
+	struct rl_txdesc	*txd;
+	u_int32_t		txstat;
+	int			cons;
+
+	cons = sc->rl_ldata.rl_tx_considx;
+	if (cons == sc->rl_ldata.rl_tx_prodidx)
+		return;
+
+	ifp = sc->rl_ifp;
+	/* Invalidate the TX descriptor list */
+	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
+	    sc->rl_ldata.rl_tx_list_map,
+	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	for (; cons != sc->rl_ldata.rl_tx_prodidx;
+	    cons = RL_TX_DESC_NXT(sc, cons)) {
+		txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
+		if (txstat & RL_TDESC_STAT_OWN)
+			break;
+		/*
+		 * We only stash mbufs in the last descriptor
+		 * in a fragment chain, which also happens to
+		 * be the only place where the TX status bits
+		 * are valid.
+		 */
+		if (txstat & RL_TDESC_CMD_EOF) {
+			txd = &sc->rl_ldata.rl_tx_desc[cons];
+			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
+			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
+			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
+			    txd->tx_dmamap);
+			KASSERT(txd->tx_m != NULL,
+			    ("%s: freeing NULL mbufs!", __func__));
+			m_freem(txd->tx_m);
+			txd->tx_m = NULL;
+			if (txstat & (RL_TDESC_STAT_EXCESSCOL|
+			    RL_TDESC_STAT_COLCNT))
+				ifp->if_collisions++;
+			if (txstat & RL_TDESC_STAT_TXERRSUM)
+				ifp->if_oerrors++;
+			else
+				ifp->if_opackets++;
+		}
+		sc->rl_ldata.rl_tx_free++;
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	}
+	sc->rl_ldata.rl_tx_considx = cons;
+
+	/* No changes made to the TX ring, so no flush needed */
+
+	if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
+		/*
+		 * Some chips will ignore a second TX request issued
+		 * while an existing transmission is in progress. If
+		 * the transmitter goes idle but there are still
+		 * packets waiting to be sent, we need to restart the
+		 * channel here to flush them out. This only seems to
+		 * be required with the PCIe devices.
+		 */
+		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
+
+#ifdef RE_TX_MODERATION
+		/*
+		 * If not all descriptors have been reaped yet, reload
+		 * the timer so that we will eventually get another
+		 * interrupt that will cause us to re-enter this routine.
+		 * This is done in case the transmitter has gone idle.
+		 */
+		CSR_WRITE_4(sc, RL_TIMERCNT, 1);
+#endif
+	} else
+		sc->rl_watchdog_timer = 0;
+}
+
+static void
+re_tick(void *xsc)
+{
+	struct rl_softc		*sc;
+	struct mii_data		*mii;
+	struct ifnet		*ifp;
+
+	sc = xsc;
+	ifp = sc->rl_ifp;
+
+	RL_LOCK_ASSERT(sc);
+
+	re_watchdog(sc);
+
+	mii = device_get_softc(sc->rl_miibus);
+	mii_tick(mii);
+	if ((sc->rl_flags & RL_FLAG_LINK) != 0) {
+		if (!(mii->mii_media_status & IFM_ACTIVE))
+			sc->rl_flags &= ~RL_FLAG_LINK;
+	} else {
+		if (mii->mii_media_status & IFM_ACTIVE &&
+		    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
+			sc->rl_flags |= RL_FLAG_LINK;
+			if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+				taskqueue_enqueue_fast(taskqueue_fast,
+				    &sc->rl_txtask);
+		}
+	}
+
+	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
+}
+
+#ifdef DEVICE_POLLING
+static void
+re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
+{
+	struct rl_softc *sc = ifp->if_softc;
+
+	RL_LOCK(sc);
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+		re_poll_locked(ifp, cmd, count);
+	RL_UNLOCK(sc);
+}
+
+static void
+re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
+{
+	struct rl_softc *sc = ifp->if_softc;
+
+	RL_LOCK_ASSERT(sc);
+
+	sc->rxcycles = count;
+	re_rxeof(sc);
+	re_txeof(sc);
+
+	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
+
+	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
+		u_int16_t       status;
+
+		status = CSR_READ_2(sc, RL_ISR);
+		if (status == 0xffff)
+			return;
+		if (status)
+			CSR_WRITE_2(sc, RL_ISR, status);
+
+		/*
+		 * XXX check behaviour on receiver stalls.
+		 */
+
+		if (status & RL_ISR_SYSTEM_ERR) {
+			re_reset(sc);
+			re_init_locked(sc);
+		}
+	}
+}
+#endif /* DEVICE_POLLING */
+
+static int
+re_intr(void *arg)
+{
+	struct rl_softc		*sc;
+	uint16_t		status;
+
+	sc = arg;
+
+	status = CSR_READ_2(sc, RL_ISR);
+	if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
+                return (FILTER_STRAY);
+	CSR_WRITE_2(sc, RL_IMR, 0);
+
+	taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
+
+	return (FILTER_HANDLED);
+}
+
+static void
+re_int_task(void *arg, int npending)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+	u_int16_t		status;
+	int			rval = 0;
+
+	sc = arg;
+	ifp = sc->rl_ifp;
+
+	RL_LOCK(sc);
+
+	status = CSR_READ_2(sc, RL_ISR);
+        CSR_WRITE_2(sc, RL_ISR, status);
+
+	if (sc->suspended ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+		RL_UNLOCK(sc);
+		return;
+	}
+
+#ifdef DEVICE_POLLING
+	if  (ifp->if_capenable & IFCAP_POLLING) {
+		RL_UNLOCK(sc);
+		return;
+	}
+#endif
+
+	if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
+		rval = re_rxeof(sc);
+
+	if (status & (
+#ifdef RE_TX_MODERATION
+	    RL_ISR_TIMEOUT_EXPIRED|
+#else
+	    RL_ISR_TX_OK|
+#endif
+	    RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
+		re_txeof(sc);
+
+	if (status & RL_ISR_SYSTEM_ERR) {
+		re_reset(sc);
+		re_init_locked(sc);
+	}
+
+	if (status & RL_ISR_LINKCHG) {
+		callout_stop(&sc->rl_stat_callout);
+		re_tick(sc);
+	}
+
+	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
+
+	RL_UNLOCK(sc);
+
+        if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
+		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
+		return;
+	}
+
+	CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
+}
+
+/*
+ * It's copy of ath_defrag(ath(4)).
+ *
+ * Defragment an mbuf chain, returning at most maxfrags separate
+ * mbufs+clusters.  If this is not possible NULL is returned and
+ * the original mbuf chain is left in it's present (potentially
+ * modified) state.  We use two techniques: collapsing consecutive
+ * mbufs and replacing consecutive mbufs by a cluster.
+ */
+static struct mbuf *
+re_defrag(m0, how, maxfrags)
+	struct mbuf *m0;
+	int how;
+	int maxfrags;
+{
+	struct mbuf *m, *n, *n2, **prev;
+	u_int curfrags;
+
+	/*
+	 * Calculate the current number of frags.
+	 */
+	curfrags = 0;
+	for (m = m0; m != NULL; m = m->m_next)
+		curfrags++;
+	/*
+	 * First, try to collapse mbufs.  Note that we always collapse
+	 * towards the front so we don't need to deal with moving the
+	 * pkthdr.  This may be suboptimal if the first mbuf has much
+	 * less data than the following.
+	 */
+	m = m0;
+again:
+	for (;;) {
+		n = m->m_next;
+		if (n == NULL)
+			break;
+		if ((m->m_flags & M_RDONLY) == 0 &&
+		    n->m_len < M_TRAILINGSPACE(m)) {
+			bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
+				n->m_len);
+			m->m_len += n->m_len;
+			m->m_next = n->m_next;
+			m_free(n);
+			if (--curfrags <= maxfrags)
+				return (m0);
+		} else
+			m = n;
+	}
+	KASSERT(maxfrags > 1,
+		("maxfrags %u, but normal collapse failed", maxfrags));
+	/*
+	 * Collapse consecutive mbufs to a cluster.
+	 */
+	prev = &m0->m_next;		/* NB: not the first mbuf */
+	while ((n = *prev) != NULL) {
+		if ((n2 = n->m_next) != NULL &&
+		    n->m_len + n2->m_len < MCLBYTES) {
+			m = m_getcl(how, MT_DATA, 0);
+			if (m == NULL)
+				goto bad;
+			bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
+			bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
+				n2->m_len);
+			m->m_len = n->m_len + n2->m_len;
+			m->m_next = n2->m_next;
+			*prev = m;
+			m_free(n);
+			m_free(n2);
+			if (--curfrags <= maxfrags)	/* +1 cl -2 mbufs */
+				return m0;
+			/*
+			 * Still not there, try the normal collapse
+			 * again before we allocate another cluster.
+			 */
+			goto again;
+		}
+		prev = &n->m_next;
+	}
+	/*
+	 * No place where we can collapse to a cluster; punt.
+	 * This can occur if, for example, you request 2 frags
+	 * but the packet requires that both be clusters (we
+	 * never reallocate the first mbuf to avoid moving the
+	 * packet header).
+	 */
+bad:
+	return (NULL);
+}
+
+
+
+static int
+re_encap(struct rl_softc *sc, struct mbuf **m_head)
+{
+	struct rl_txdesc	*txd, *txd_last;
+	bus_dma_segment_t	segs[RL_NTXSEGS];
+	bus_dmamap_t		map;
+	struct mbuf		*m_new;
+	struct rl_desc		*desc;
+	int			nsegs, prod;
+	int			i, error, ei, si;
+	int			padlen;
+	uint32_t		cmdstat, csum_flags, vlanctl;
+
+	RL_LOCK_ASSERT(sc);
+	M_ASSERTPKTHDR((*m_head));
+
+	/*
+	 * With some of the RealTek chips, using the checksum offload
+	 * support in conjunction with the autopadding feature results
+	 * in the transmission of corrupt frames. For example, if we
+	 * need to send a really small IP fragment that's less than 60
+	 * bytes in size, and IP header checksumming is enabled, the
+	 * resulting ethernet frame that appears on the wire will
+	 * have garbled payload. To work around this, if TX IP checksum
+	 * offload is enabled, we always manually pad short frames out
+	 * to the minimum ethernet frame size.
+	 */
+	if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 &&
+	    (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
+	    ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
+		padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
+		if (M_WRITABLE(*m_head) == 0) {
+			/* Get a writable copy. */
+			m_new = m_dup(*m_head, M_DONTWAIT);
+			m_freem(*m_head);
+			if (m_new == NULL) {
+				*m_head = NULL;
+				return (ENOBUFS);
+			}
+			*m_head = m_new;
+		}
+		if ((*m_head)->m_next != NULL ||
+		    M_TRAILINGSPACE(*m_head) < padlen) {
+			m_new = m_defrag(*m_head, M_DONTWAIT);
+			if (m_new == NULL) {
+				m_freem(*m_head);
+				*m_head = NULL;
+				return (ENOBUFS);
+			}
+		} else
+			m_new = *m_head;
+
+		/*
+		 * Manually pad short frames, and zero the pad space
+		 * to avoid leaking data.
+		 */
+		bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
+		m_new->m_pkthdr.len += padlen;
+		m_new->m_len = m_new->m_pkthdr.len;
+		*m_head = m_new;
+	}
+
+	prod = sc->rl_ldata.rl_tx_prodidx;
+	txd = &sc->rl_ldata.rl_tx_desc[prod];
+	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
+	    *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
+	if (error == EFBIG) {
+		m_new = re_defrag(*m_head, M_DONTWAIT, RL_NTXSEGS);
+		if (m_new == NULL) {
+			m_freem(*m_head);
+			*m_head = NULL;
+			return (ENOBUFS);
+		}
+		*m_head = m_new;
+		error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
+		    txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
+		if (error != 0) {
+			m_freem(*m_head);
+			*m_head = NULL;
+			return (error);
+		}
+	} else if (error != 0)
+		return (error);
+	if (nsegs == 0) {
+		m_freem(*m_head);
+		*m_head = NULL;
+		return (EIO);
+	}
+
+	/* Check for number of available descriptors. */
+	if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
+		bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
+		return (ENOBUFS);
+	}
+
+	bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
+	    BUS_DMASYNC_PREWRITE);
+
+	/*
+	 * Set up checksum offload. Note: checksum offload bits must
+	 * appear in all descriptors of a multi-descriptor transmit
+	 * attempt. This is according to testing done with an 8169
+	 * chip. This is a requirement.
+	 */
+	vlanctl = 0;
+	csum_flags = 0;
+	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0)
+		csum_flags = RL_TDESC_CMD_LGSEND |
+		    ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
+		    RL_TDESC_CMD_MSSVAL_SHIFT);
+	else {
+		/*
+		 * Unconditionally enable IP checksum if TCP or UDP
+		 * checksum is required. Otherwise, TCP/UDP checksum
+		 * does't make effects.
+		 */
+		if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
+			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
+				csum_flags |= RL_TDESC_CMD_IPCSUM;
+				if (((*m_head)->m_pkthdr.csum_flags &
+				    CSUM_TCP) != 0)
+					csum_flags |= RL_TDESC_CMD_TCPCSUM;
+				if (((*m_head)->m_pkthdr.csum_flags &
+				    CSUM_UDP) != 0)
+					csum_flags |= RL_TDESC_CMD_UDPCSUM;
+			} else {
+				vlanctl |= RL_TDESC_CMD_IPCSUMV2;
+				if (((*m_head)->m_pkthdr.csum_flags &
+				    CSUM_TCP) != 0)
+					vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
+				if (((*m_head)->m_pkthdr.csum_flags &
+				    CSUM_UDP) != 0)
+					vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
+			}
+		}
+	}
+
+	/*
+	 * Set up hardware VLAN tagging. Note: vlan tag info must
+	 * appear in all descriptors of a multi-descriptor
+	 * transmission attempt.
+	 */
+	if ((*m_head)->m_flags & M_VLANTAG)
+		vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
+		    RL_TDESC_VLANCTL_TAG;
+
+	si = prod;
+	for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
+		desc = &sc->rl_ldata.rl_tx_list[prod];
+		desc->rl_vlanctl = htole32(vlanctl);
+		desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
+		desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
+		cmdstat = segs[i].ds_len;
+		if (i != 0)
+			cmdstat |= RL_TDESC_CMD_OWN;
+		if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
+			cmdstat |= RL_TDESC_CMD_EOR;
+		desc->rl_cmdstat = htole32(cmdstat | csum_flags);
+		sc->rl_ldata.rl_tx_free--;
+	}
+	/* Update producer index. */
+	sc->rl_ldata.rl_tx_prodidx = prod;
+
+	/* Set EOF on the last descriptor. */
+	ei = RL_TX_DESC_PRV(sc, prod);
+	desc = &sc->rl_ldata.rl_tx_list[ei];
+	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
+
+	desc = &sc->rl_ldata.rl_tx_list[si];
+	/* Set SOF and transfer ownership of packet to the chip. */
+	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
+
+	/*
+	 * Insure that the map for this transmission
+	 * is placed at the array index of the last descriptor
+	 * in this chain.  (Swap last and first dmamaps.)
+	 */
+	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
+	map = txd->tx_dmamap;
+	txd->tx_dmamap = txd_last->tx_dmamap;
+	txd_last->tx_dmamap = map;
+	txd_last->tx_m = *m_head;
+
+	return (0);
+}
+
+static void
+re_tx_task(void *arg, int npending)
+{
+	struct ifnet		*ifp;
+
+	ifp = arg;
+	re_start(ifp);
+}
+
+/*
+ * Main transmit routine for C+ and gigE NICs.
+ */
+static void
+re_start(struct ifnet *ifp)
+{
+	struct rl_softc		*sc;
+	struct mbuf		*m_head;
+	int			queued;
+
+	sc = ifp->if_softc;
+
+	RL_LOCK(sc);
+
+	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) {
+		RL_UNLOCK(sc);
+		return;
+	}
+
+	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
+	    sc->rl_ldata.rl_tx_free > 1;) {
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		if (re_encap(sc, &m_head) != 0) {
+			if (m_head == NULL)
+				break;
+			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			break;
+		}
+
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+		ETHER_BPF_MTAP(ifp, m_head);
+
+		queued++;
+	}
+
+	if (queued == 0) {
+#ifdef RE_TX_MODERATION
+		if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
+			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
+#endif
+		RL_UNLOCK(sc);
+		return;
+	}
+
+	/* Flush the TX descriptors */
+
+	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
+	    sc->rl_ldata.rl_tx_list_map,
+	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
+
+	CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
+
+#ifdef RE_TX_MODERATION
+	/*
+	 * Use the countdown timer for interrupt moderation.
+	 * 'TX done' interrupts are disabled. Instead, we reset the
+	 * countdown timer, which will begin counting until it hits
+	 * the value in the TIMERINT register, and then trigger an
+	 * interrupt. Each time we write to the TIMERCNT register,
+	 * the timer count is reset to 0.
+	 */
+	CSR_WRITE_4(sc, RL_TIMERCNT, 1);
+#endif
+
+	/*
+	 * Set a timeout in case the chip goes out to lunch.
+	 */
+	sc->rl_watchdog_timer = 5;
+
+	RL_UNLOCK(sc);
+}
+
+static void
+re_init(void *xsc)
+{
+	struct rl_softc		*sc = xsc;
+
+	RL_LOCK(sc);
+	re_init_locked(sc);
+	RL_UNLOCK(sc);
+}
+
+static void
+re_init_locked(struct rl_softc *sc)
+{
+	struct ifnet		*ifp = sc->rl_ifp;
+	struct mii_data		*mii;
+	u_int32_t		rxcfg = 0;
+	uint16_t		cfg;
+	union {
+		uint32_t align_dummy;
+		u_char eaddr[ETHER_ADDR_LEN];
+        } eaddr;
+
+	RL_LOCK_ASSERT(sc);
+
+	mii = device_get_softc(sc->rl_miibus);
+
+	/*
+	 * Cancel pending I/O and free all RX/TX buffers.
+	 */
+	re_stop(sc);
+
+	/*
+	 * Enable C+ RX and TX mode, as well as VLAN stripping and
+	 * RX checksum offload. We must configure the C+ register
+	 * before all others.
+	 */
+	cfg = RL_CPLUSCMD_PCI_MRW;
+	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
+		cfg |= RL_CPLUSCMD_RXCSUM_ENB;
+	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
+		cfg |= RL_CPLUSCMD_VLANSTRIP;
+	if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
+		cfg |= RL_CPLUSCMD_MACSTAT_DIS;
+		/* XXX magic. */
+		cfg |= 0x0001;
+	} else
+		cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
+	CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
+	/*
+	 * Disable TSO if interface MTU size is greater than MSS
+	 * allowed in controller.
+	 */
+	if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
+		ifp->if_capenable &= ~IFCAP_TSO4;
+		ifp->if_hwassist &= ~CSUM_TSO;
+	}
+
+	/*
+	 * Init our MAC address.  Even though the chipset
+	 * documentation doesn't mention it, we need to enter "Config
+	 * register write enable" mode to modify the ID registers.
+	 */
+	/* Copy MAC address on stack to align. */
+	bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
+	CSR_WRITE_4(sc, RL_IDR0,
+	    htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
+	CSR_WRITE_4(sc, RL_IDR4,
+	    htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	/*
+	 * For C+ mode, initialize the RX descriptors and mbufs.
+	 */
+	re_rx_list_init(sc);
+	re_tx_list_init(sc);
+
+	/*
+	 * Load the addresses of the RX and TX lists into the chip.
+	 */
+
+	CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
+	    RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
+	CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
+	    RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
+
+	CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
+	    RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
+	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
+	    RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
+
+	/*
+	 * Enable transmit and receive.
+	 */
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
+
+	/*
+	 * Set the initial TX and RX configuration.
+	 */
+	if (sc->rl_testmode) {
+		if (sc->rl_type == RL_8169)
+			CSR_WRITE_4(sc, RL_TXCFG,
+			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
+		else
+			CSR_WRITE_4(sc, RL_TXCFG,
+			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
+	} else
+		CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
+
+	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
+
+	CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
+
+	/* Set the individual bit to receive frames for this host only. */
+	rxcfg = CSR_READ_4(sc, RL_RXCFG);
+	rxcfg |= RL_RXCFG_RX_INDIV;
+
+	/* If we want promiscuous mode, set the allframes bit. */
+	if (ifp->if_flags & IFF_PROMISC)
+		rxcfg |= RL_RXCFG_RX_ALLPHYS;
+	else
+		rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
+	CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
+
+	/*
+	 * Set capture broadcast bit to capture broadcast frames.
+	 */
+	if (ifp->if_flags & IFF_BROADCAST)
+		rxcfg |= RL_RXCFG_RX_BROAD;
+	else
+		rxcfg &= ~RL_RXCFG_RX_BROAD;
+	CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
+
+	/*
+	 * Program the multicast filter, if necessary.
+	 */
+	re_setmulti(sc);
+
+#ifdef DEVICE_POLLING
+	/*
+	 * Disable interrupts if we are polling.
+	 */
+	if (ifp->if_capenable & IFCAP_POLLING)
+		CSR_WRITE_2(sc, RL_IMR, 0);
+	else	/* otherwise ... */
+#endif
+
+	/*
+	 * Enable interrupts.
+	 */
+	if (sc->rl_testmode)
+		CSR_WRITE_2(sc, RL_IMR, 0);
+	else
+		CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
+	CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
+
+	/* Set initial TX threshold */
+	sc->rl_txthresh = RL_TX_THRESH_INIT;
+
+	/* Start RX/TX process. */
+	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
+#ifdef notdef
+	/* Enable receiver and transmitter. */
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
+#endif
+
+#ifdef RE_TX_MODERATION
+	/*
+	 * Initialize the timer interrupt register so that
+	 * a timer interrupt will be generated once the timer
+	 * reaches a certain number of ticks. The timer is
+	 * reloaded on each transmit. This gives us TX interrupt
+	 * moderation, which dramatically improves TX frame rate.
+	 */
+	if (sc->rl_type == RL_8169)
+		CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
+	else
+		CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
+#endif
+
+	/*
+	 * For 8169 gigE NICs, set the max allowed RX packet
+	 * size so we can receive jumbo frames.
+	 */
+	if (sc->rl_type == RL_8169)
+		CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
+
+	if (sc->rl_testmode)
+		return;
+
+	mii_mediachg(mii);
+
+	CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
+
+	ifp->if_drv_flags |= IFF_DRV_RUNNING;
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+	sc->rl_flags &= ~RL_FLAG_LINK;
+	sc->rl_watchdog_timer = 0;
+	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
+}
+
+/*
+ * Set media options.
+ */
+static int
+re_ifmedia_upd(struct ifnet *ifp)
+{
+	struct rl_softc		*sc;
+	struct mii_data		*mii;
+
+	sc = ifp->if_softc;
+	mii = device_get_softc(sc->rl_miibus);
+	RL_LOCK(sc);
+	mii_mediachg(mii);
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct rl_softc		*sc;
+	struct mii_data		*mii;
+
+	sc = ifp->if_softc;
+	mii = device_get_softc(sc->rl_miibus);
+
+	RL_LOCK(sc);
+	mii_pollstat(mii);
+	RL_UNLOCK(sc);
+	ifmr->ifm_active = mii->mii_media_active;
+	ifmr->ifm_status = mii->mii_media_status;
+}
+
+static int
+re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+	struct rl_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	struct mii_data		*mii;
+	int			error = 0;
+
+	switch (command) {
+	case SIOCSIFMTU:
+		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) {
+			error = EINVAL;
+			break;
+		}
+		if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 &&
+		    ifr->ifr_mtu > RL_MAX_FRAMELEN) {
+			error = EINVAL;
+			break;
+		}
+		RL_LOCK(sc);
+		if (ifp->if_mtu != ifr->ifr_mtu)
+			ifp->if_mtu = ifr->ifr_mtu;
+		if (ifp->if_mtu > RL_TSO_MTU &&
+		    (ifp->if_capenable & IFCAP_TSO4) != 0) {
+			ifp->if_capenable &= ~IFCAP_TSO4;
+			ifp->if_hwassist &= ~CSUM_TSO;
+		}
+		RL_UNLOCK(sc);
+		break;
+	case SIOCSIFFLAGS:
+		RL_LOCK(sc);
+		if ((ifp->if_flags & IFF_UP) != 0) {
+			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
+				if (((ifp->if_flags ^ sc->rl_if_flags)
+				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
+					re_setmulti(sc);
+			} else
+				re_init_locked(sc);
+		} else {
+			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+				re_stop(sc);
+		}
+		sc->rl_if_flags = ifp->if_flags;
+		RL_UNLOCK(sc);
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		RL_LOCK(sc);
+		re_setmulti(sc);
+		RL_UNLOCK(sc);
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		mii = device_get_softc(sc->rl_miibus);
+		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+		break;
+	case SIOCSIFCAP:
+	    {
+		int mask, reinit;
+
+		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+		reinit = 0;
+#ifdef DEVICE_POLLING
+		if (mask & IFCAP_POLLING) {
+			if (ifr->ifr_reqcap & IFCAP_POLLING) {
+				error = ether_poll_register(re_poll, ifp);
+				if (error)
+					return(error);
+				RL_LOCK(sc);
+				/* Disable interrupts */
+				CSR_WRITE_2(sc, RL_IMR, 0x0000);
+				ifp->if_capenable |= IFCAP_POLLING;
+				RL_UNLOCK(sc);
+			} else {
+				error = ether_poll_deregister(ifp);
+				/* Enable interrupts. */
+				RL_LOCK(sc);
+				CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
+				ifp->if_capenable &= ~IFCAP_POLLING;
+				RL_UNLOCK(sc);
+			}
+		}
+#endif /* DEVICE_POLLING */
+		if (mask & IFCAP_HWCSUM) {
+			ifp->if_capenable ^= IFCAP_HWCSUM;
+			if (ifp->if_capenable & IFCAP_TXCSUM)
+				ifp->if_hwassist |= RE_CSUM_FEATURES;
+			else
+				ifp->if_hwassist &= ~RE_CSUM_FEATURES;
+			reinit = 1;
+		}
+		if (mask & IFCAP_VLAN_HWTAGGING) {
+			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
+			reinit = 1;
+		}
+		if (mask & IFCAP_TSO4) {
+			ifp->if_capenable ^= IFCAP_TSO4;
+			if ((IFCAP_TSO4 & ifp->if_capenable) &&
+			    (IFCAP_TSO4 & ifp->if_capabilities))
+				ifp->if_hwassist |= CSUM_TSO;
+			else
+				ifp->if_hwassist &= ~CSUM_TSO;
+			if (ifp->if_mtu > RL_TSO_MTU &&
+			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
+				ifp->if_capenable &= ~IFCAP_TSO4;
+				ifp->if_hwassist &= ~CSUM_TSO;
+			}
+		}
+#ifdef ENABLE_WOL
+		if ((mask & IFCAP_WOL) != 0 &&
+		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
+			if ((mask & IFCAP_WOL_UCAST) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_UCAST;
+			if ((mask & IFCAP_WOL_MCAST) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_MCAST;
+			if ((mask & IFCAP_WOL_MAGIC) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
+		}
+#endif
+		if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
+			re_init(sc);
+		VLAN_CAPABILITIES(ifp);
+	    }
+		break;
+	default:
+		error = ether_ioctl(ifp, command, data);
+		break;
+	}
+
+	return (error);
+}
+
+static void
+re_watchdog(struct rl_softc *sc)
+{
+
+	RL_LOCK_ASSERT(sc);
+
+	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
+		return;
+
+	device_printf(sc->rl_dev, "watchdog timeout\n");
+	sc->rl_ifp->if_oerrors++;
+
+	re_txeof(sc);
+	re_rxeof(sc);
+	re_init_locked(sc);
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void
+re_stop(struct rl_softc *sc)
+{
+	int			i;
+	struct ifnet		*ifp;
+	struct rl_txdesc	*txd;
+	struct rl_rxdesc	*rxd;
+
+	RL_LOCK_ASSERT(sc);
+
+	ifp = sc->rl_ifp;
+
+	sc->rl_watchdog_timer = 0;
+	callout_stop(&sc->rl_stat_callout);
+	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+
+	CSR_WRITE_1(sc, RL_COMMAND, 0x00);
+	CSR_WRITE_2(sc, RL_IMR, 0x0000);
+	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
+
+	if (sc->rl_head != NULL) {
+		m_freem(sc->rl_head);
+		sc->rl_head = sc->rl_tail = NULL;
+	}
+
+	/* Free the TX list buffers. */
+
+	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
+		txd = &sc->rl_ldata.rl_tx_desc[i];
+		if (txd->tx_m != NULL) {
+			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
+			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
+			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
+			    txd->tx_dmamap);
+			m_freem(txd->tx_m);
+			txd->tx_m = NULL;
+		}
+	}
+
+	/* Free the RX list buffers. */
+
+	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
+		rxd = &sc->rl_ldata.rl_rx_desc[i];
+		if (rxd->rx_m != NULL) {
+			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
+			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
+			    rxd->rx_dmamap);
+			m_freem(rxd->rx_m);
+			rxd->rx_m = NULL;
+		}
+	}
+}
+
+/*
+ * Device suspend routine.  Stop the interface and save some PCI
+ * settings in case the BIOS doesn't restore them properly on
+ * resume.
+ */
+static int
+re_suspend(device_t dev)
+{
+	struct rl_softc		*sc;
+
+	sc = device_get_softc(dev);
+
+	RL_LOCK(sc);
+	re_stop(sc);
+	re_setwol(sc);
+	sc->suspended = 1;
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Device resume routine.  Restore some PCI settings in case the BIOS
+ * doesn't, re-enable busmastering, and restart the interface if
+ * appropriate.
+ */
+static int
+re_resume(device_t dev)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+
+	sc = device_get_softc(dev);
+
+	RL_LOCK(sc);
+
+	ifp = sc->rl_ifp;
+
+	/* reinitialize interface if necessary */
+	if (ifp->if_flags & IFF_UP)
+		re_init_locked(sc);
+
+	/*
+	 * Clear WOL matching such that normal Rx filtering
+	 * wouldn't interfere with WOL patterns.
+	 */
+	re_clrwol(sc);
+	sc->suspended = 0;
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static int
+re_shutdown(device_t dev)
+{
+	struct rl_softc		*sc;
+
+	sc = device_get_softc(dev);
+
+	RL_LOCK(sc);
+	re_stop(sc);
+	/*
+	 * Mark interface as down since otherwise we will panic if
+	 * interrupt comes in later on, which can happen in some
+	 * cases.
+	 */
+	sc->rl_ifp->if_flags &= ~IFF_UP;
+	re_setwol(sc);
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+static void
+re_setwol(struct rl_softc *sc)
+{
+#ifdef ENABLE_WOL
+	struct ifnet		*ifp;
+	int			pmc;
+	uint16_t		pmstat;
+	uint8_t			v;
+
+	RL_LOCK_ASSERT(sc);
+
+	if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
+		return;
+
+	ifp = sc->rl_ifp;
+	/* Enable config register write. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+
+	/* Enable PME. */
+	v = CSR_READ_1(sc, RL_CFG1);
+	v &= ~RL_CFG1_PME;
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		v |= RL_CFG1_PME;
+	CSR_WRITE_1(sc, RL_CFG1, v);
+
+	v = CSR_READ_1(sc, RL_CFG3);
+	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
+	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
+		v |= RL_CFG3_WOL_MAGIC;
+	CSR_WRITE_1(sc, RL_CFG3, v);
+
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	v = CSR_READ_1(sc, RL_CFG5);
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
+	v &= ~RL_CFG5_WOL_LANWAKE;
+	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
+		v |= RL_CFG5_WOL_UCAST;
+	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
+		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		v |= RL_CFG5_WOL_LANWAKE;
+	CSR_WRITE_1(sc, RL_CFG5, v);
+
+	/*
+	 * It seems that hardware resets its link speed to 100Mbps in
+	 * power down mode so switching to 100Mbps in driver is not
+	 * needed.
+	 */
+
+	/* Request PME if WOL is requested. */
+	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
+	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
+	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
+#endif
+}
+
+static void
+re_clrwol(struct rl_softc *sc)
+{
+#ifdef ENABLE_WOL
+	int			pmc;
+	uint8_t			v;
+
+	RL_LOCK_ASSERT(sc);
+
+	if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
+		return;
+
+	/* Enable config register write. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+
+	v = CSR_READ_1(sc, RL_CFG3);
+	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
+	CSR_WRITE_1(sc, RL_CFG3, v);
+
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	v = CSR_READ_1(sc, RL_CFG5);
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
+	v &= ~RL_CFG5_WOL_LANWAKE;
+	CSR_WRITE_1(sc, RL_CFG5, v);
+#endif
+}
+
Index: src/add-ons/kernel/drivers/network/re/pci/Jamfile
===================================================================
--- src/add-ons/kernel/drivers/network/re/pci/Jamfile	(revision 0)
+++ src/add-ons/kernel/drivers/network/re/pci/Jamfile	(revision 0)
@@ -0,0 +1,16 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network re pci ;
+
+UsePrivateHeaders kernel net ;
+
+UseHeaders [ FDirName $(SUBDIR) .. ] : true ;
+UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
+UseHeaders [ FDirName $(HAIKU_TOP) src add-ons kernel drivers network rtl8139 ] : true ;
+
+SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
+
+KernelAddon re :
+	if_re.c
+	glue.c
+	: libfreebsd_network.a rtl8139_mii.a
+	;
+
Index: src/add-ons/kernel/drivers/network/re/pci/glue.c
===================================================================
--- src/add-ons/kernel/drivers/network/re/pci/glue.c	(revision 0)
+++ src/add-ons/kernel/drivers/network/re/pci/glue.c	(revision 0)
@@ -0,0 +1,37 @@
+#include <sys/bus.h>
+#include <pci/if_rlreg.h>
+
+HAIKU_FBSD_DRIVER_GLUE(re, re, pci);
+HAIKU_FBSD_MII_DRIVER(rlphy);
+HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE);
+
+int
+HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
+{
+	struct rl_softc *sc = device_get_softc(dev);
+	uint16_t status;
+
+	status = CSR_READ_2(sc, RL_ISR);
+	if (status == 0xffff)
+		return 0;
+	if (status != 0 && (status & RL_INTRS) == 0) {
+		CSR_WRITE_2(sc, RL_ISR, status);
+		return 0;
+	}
+	if ((status & RL_INTRS) == 0)
+		return 0;
+
+	CSR_WRITE_2(sc, RL_IMR, 0);
+	return 1;
+}
+
+
+void
+HAIKU_REENABLE_INTERRUPTS(device_t dev)
+{
+	struct rl_softc *sc = device_get_softc(dev);
+	RL_LOCK(sc);
+	CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
+	RL_UNLOCK(sc);
+}
+
Index: src/add-ons/kernel/drivers/network/Jamfile
===================================================================
--- src/add-ons/kernel/drivers/network/Jamfile	(revision 27723)
+++ src/add-ons/kernel/drivers/network/Jamfile	(working copy)
@@ -21,6 +21,7 @@
 SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ;
 SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect ;
 SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 ;
+SubInclude HAIKU_TOP src add-ons kernel drivers network re ;
 
 SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
 SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;
