Ticket #10606: radeon-bar.diff

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

@@ -137 +137 @@
                 // *** Discreet card on IGP, check PCI BAR 0
                 // On post, the bios puts a copy of the IGP
                 // AtomBIOS at the start of the video ram
-                romBase = info.pci->u.h0.base_registers[PCI_BAR_FB];
+                romBase = info.shared_info->frame_buffer_phys;
                 romSize = 256 * 1024;
 
                 if (romBase == 0 || romSize == 0) {
@@ -517 +517 @@
 }
 
 
-static uint32
-radeon_hd_pci_bar_mmio(uint16 chipsetID)
+static void
+radeon_hd_locate_bars(radeon_info &info, radeon_bar_map &barMap)
 {
-    if (chipsetID < RADEON_BONAIRE)
-        return 2;
-    else
-        return 5;
+    // Locate some good bars
+
+    // DCE < 8
+    //  BAR 0 == FB
+    //  BAR 2 == MMIO
+    // DCE >= 8
+    //  BAR 0 == FB
+    //  BAR 2 == DOORBELL
+    //  BAR 5 == MMIO
+
+    barMap.framebuffer = 0;
+    barMap.mmio = info.shared_info->dceMajor < 8 ? 2 : 5;
+    barMap.doorbell = info.shared_info->dceMajor >= 8 ? 2 : -1;
 }
 
 
@@ -550 +559 @@
     memset((void*)info.shared_info, 0, sizeof(radeon_shared_info));
     sharedCreator.Detach();
 
-    // *** Map Memory mapped IO
+    // *** Find bars
+    radeon_bar_map barMap;
+    radeon_hd_locate_bars(info, &barMap)
+
+    // *** Memory mapped IO
     AreaKeeper mmioMapper;
-    const uint32 pciBarMmio = radeon_hd_pci_bar_mmio(info.chipsetID);
+    
     info.registers_area = mmioMapper.Map("radeon hd mmio",
-        info.pci->u.h0.base_registers[pciBarMmio],
-        info.pci->u.h0.base_register_sizes[pciBarMmio],
+        info.pci->u.h0.base_registers[barMap.mmio],
+        info.pci->u.h0.base_register_sizes[barMap.mmio],
         B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
         (void**)&info.registers);
     if (mmioMapper.InitCheck() < B_OK) {
@@ -603 +616 @@
         }
     }
 
-    uint32 barSize = info.pci->u.h0.base_register_sizes[PCI_BAR_FB] / 1024;
+    // TODO: if barMap.doorbell >= 0, map
+
+    uint32 fbBarSize = info.pci->u.h0.base_register_sizes[barMap.framebuffer] / 1024;
 
     // if graphics memory is larger then PCI bar, just map bar
     if (info.shared_info->graphics_memory_size == 0) {
@@ -627 +642 @@
     // *** Framebuffer mapping
     AreaKeeper frambufferMapper;
     info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer",
-        info.pci->u.h0.base_registers[PCI_BAR_FB],
+        info.pci->u.h0.base_registers[barMap.framebuffer],
         info.shared_info->frame_buffer_size * 1024,
         B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA,
         (void**)&info.shared_info->frame_buffer);
@@ -639 +654 @@
 
     // Turn on write combining for the frame buffer area
     vm_set_area_memory_type(info.framebuffer_area,
-        info.pci->u.h0.base_registers[PCI_BAR_FB], B_MTR_WC);
+        info.pci->u.h0.base_registers[barMap.framebuffer], B_MTR_WC);
 
     frambufferMapper.Detach();
 
     info.shared_info->frame_buffer_area = info.framebuffer_area;
     info.shared_info->frame_buffer_phys
-        = info.pci->u.h0.base_registers[PCI_BAR_FB];
+        = info.pci->u.h0.base_registers[barMap.framebuffer];
 
     // Pass common information to accelerant
     info.shared_info->deviceIndex = info.id;

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd_private.h

@@ -28 +28 @@
     ((RADEON_BIOS16(adr, v) | RADEON_BIOS16(adr, v + 2) << 16))
 
 
+struct radeon_bar_map {
+    int framebuffer;
+    int mmio;
+    int doorbell;
+};
+
 struct radeon_info {
     int32           open_count;
     status_t        init_status;