Ticket #1293: ek_radeon_dual_dvi_patch1.diff

File ek_radeon_dual_dvi_patch1.diff, 35.4 KB (added by euan, 17 years ago)

First beta patch

  • src/add-ons/kernel/drivers/graphics/radeon/init.c

     
    1515*/
    1616
    1717#include "dac_regs.h"
     18#include "tv_out_regs.h"
    1819#include "fp_regs.h"
    1920#include "mmio.h"
    2021#include "radeon_driver.h"
    … …  
    266267    // so we let the first accelerant take care of it
    267268    si->theatre_channel = -1;
    268269   
    269 /*  si->ports[0].disp_type = di->disp_type[0];
    270     si->ports[1].disp_type = di->disp_type[1];*/
    271270    si->crtc[0].crtc_idx = 0;
    272271    si->crtc[0].flatpanel_port = 0;
    273272    si->crtc[1].crtc_idx = 1;
    274273    si->crtc[1].flatpanel_port = 1;
    275274    si->num_crtc = di->num_crtc;
    276275   
    277     si->flatpanels[0] = di->fp_info;
     276    if (di->is_mobility)
     277        si->flatpanels[0] = di->fp_info;
     278
    278279    si->pll = di->pll;
    279 /*  si->ram = di->ram;
    280     strcpy( si->ram_type, di->ram_type );*/
    281     //si->local_mem_size = di->local_mem_size;
    282        
     280
    283281    // create virtual card info; don't allow access by apps -
    284282    // they'll clone it
    285283    sprintf( buffer, "%04X_%04X_%02X%02X%02X virtual card 0",
    … …  
    306304    di->vc->assigned_crtc[0] = true;
    307305    di->vc->assigned_crtc[1] = si->num_crtc > 1;
    308306    di->vc->controlled_displays =
    309         dd_tv_crt | dd_crt | dd_lvds | dd_dvi | dd_ctv | dd_stv;
     307        dd_tv_crt | dd_crt | dd_lvds | dd_dvi | dd_dvi_ext | dd_ctv | dd_stv;
    310308
    311309    di->vc->fb_mem_handle = 0;
    312310    di->vc->cursor.mem_handle = 0;
    … …  
    324322    if( di->asic == rt_rv100 && di->is_mobility)
    325323        di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 );
    326324   
     325    memcpy(&si->tmds_pll, &di->tmds_pll, sizeof(di->tmds_pll));
     326    si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL);
     327    si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL);
     328
    327329    // print these out to capture bios status...
    328     if ( di->is_mobility ) {
    329         SHOW_INFO0( 4, "Copy of Laptop Display Regs for Reference:");
    330         SHOW_INFO( 4, "LVDS CNTL = %8lx", INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
    331         SHOW_INFO( 4, "FP1  CNTL = %8lx", INREG( di->regs, RADEON_FP_GEN_CNTL ));
    332         SHOW_INFO( 4, "FP2  CNTL = %8lx", INREG( di->regs, RADEON_FP2_GEN_CNTL ));
    333     }
     330//  if ( di->is_mobility ) {
     331        SHOW_INFO0( 2, "Copy of Laptop Display Regs for Reference:");
     332        SHOW_INFO( 2, "LVDS GEN = %8lx", INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
     333        SHOW_INFO( 2, "LVDS PLL = %8lx", INREG( di->regs, RADEON_LVDS_PLL_CNTL ));
     334        SHOW_INFO( 2, "TMDS PLL = %8lx", INREG( di->regs, RADEON_TMDS_PLL_CNTL ));
     335        SHOW_INFO( 2, "TMDS TRANS = %8lx", INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));
     336        SHOW_INFO( 2, "FP1 GEN = %8lx", INREG( di->regs, RADEON_FP_GEN_CNTL ));
     337        SHOW_INFO( 2, "FP2 GEN = %8lx", INREG( di->regs, RADEON_FP2_GEN_CNTL ));
     338        SHOW_INFO( 2, "TV DAC = %8lx", INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi
     339//  }
    334340   
    335341    result = Radeon_InitPCIGART( di );
    336342    if( result < 0 )

  • src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h

     
    116116    disp_entity routing;
    117117   
    118118    general_pll_info pll;
     119    tmds_pll_info    tmds_pll[4];
    119120    ram_info    ram;   
    120121    char        ram_type[32];   // human-readable name of ram type
    121122    uint32      local_mem_size;

  • src/add-ons/kernel/drivers/graphics/radeon/bios.c

     
    3131
    3232#define RADEON_BIOS8(v)      (di->rom.rom_ptr[v])
    3333#define RADEON_BIOS16(v)    ((di->rom.rom_ptr[v]) | \
    34                              (di->rom.rom_ptr[(v) + 1] << 8))
     34                (di->rom.rom_ptr[(v) + 1] << 8))
    3535#define RADEON_BIOS32(v)    ((di->rom.rom_ptr[v]) | \
    36                              (di->rom.rom_ptr[(v) + 1] << 8) \
    37                              (di->rom.rom_ptr[(v) + 2] << 16) \
    38                              (di->rom.rom_ptr[(v) + 3] << 24))
     36                (di->rom.rom_ptr[(v) + 1] << 8) | \
     37                (di->rom.rom_ptr[(v) + 2] << 16) | \
     38                (di->rom.rom_ptr[(v) + 3] << 24))
    3939
    4040static const char ati_rom_sig[] = "761295520";
    4141
     42static const tmds_pll_info default_tmds_pll[14][4] =
     43{
     44    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},          // r100
     45    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},          // rv100
     46    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},                       // rs100
     47    {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},          // rv200
     48    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},          // rs200
     49    {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},          // r200
     50    {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},          // rv250
     51    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},                       // rs300
     52    {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    // rv280
     53    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},                // r300
     54    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},                // r350
     55    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},          // rv350
     56    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},          // rv380
     57    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},                // r420
     58};
     59
     60
    4261// find address of ROM;
    4362// this code is really nasty as maintaining the radeon signatures
    4463// is almost impossible (the signatures provided by ATI are always out-dated);
    … …  
    691710        >> RADEON_CRTC_V_SYNC_WID_SHIFT);
    692711}
    693712
     713//snaffled from X.org hope it works...
     714static void Radeon_GetTMDSInfoFromBios( device_info *di )
     715{
     716    uint32 tmp, maxfreq;
     717    uint32 found = FALSE;
     718    int i, n;
     719    uint16 bios_header;
    694720
     721    bios_header = RADEON_BIOS16( 0x48 );
     722
     723    for (i = 0; i < 4; i++) {
     724        di->tmds_pll[i].value = 0;
     725        di->tmds_pll[i].freq = 0;
     726    }
     727   
     728    if (di->is_atombios)
     729    {
     730        int master_data_start;
     731        master_data_start = RADEON_BIOS16( bios_header + 32 );
     732       
     733        if((tmp = RADEON_BIOS16 (master_data_start + 18))) {
     734   
     735            maxfreq = RADEON_BIOS16(tmp + 4);
     736           
     737            for (i = 0; i < 4; i++) {
     738                di->tmds_pll[i].freq = RADEON_BIOS16(tmp + i * 6 + 6);
     739                // This assumes each field in TMDS_PLL has 6 bit as in R300/R420
     740                di->tmds_pll[i].value = ((RADEON_BIOS8(tmp + i * 6 + 8) & 0x3f) |
     741                   ((RADEON_BIOS8(tmp + i * 6 + 10) & 0x3f) << 6) |
     742                   ((RADEON_BIOS8(tmp + i * 6 +  9) & 0xf) << 12) |
     743                   ((RADEON_BIOS8(tmp + i * 6 + 11) & 0xf) << 16));
     744                SHOW_ERROR( 2, "TMDS PLL from BIOS: %ld %lx",
     745                   di->tmds_pll[i].freq, di->tmds_pll[i].value);
     746                       
     747                if (maxfreq == di->tmds_pll[i].freq) {
     748                    di->tmds_pll[i].freq = 0xffffffff;
     749                    break;
     750                }
     751            }
     752            found = TRUE;
     753        }
     754    } else {
     755
     756        tmp = RADEON_BIOS16(bios_header + 0x34);
     757        if (tmp) {
     758            SHOW_ERROR( 2, "DFP table revision: %d", RADEON_BIOS8(tmp));
     759            if (RADEON_BIOS8(tmp) == 3) {
     760                n = RADEON_BIOS8(tmp + 5) + 1;
     761                if (n > 4)
     762                    n = 4;
     763                for (i = 0; i < n; i++) {
     764                    di->tmds_pll[i].value = RADEON_BIOS32(tmp + i * 10 + 0x08);
     765                    di->tmds_pll[i].freq = RADEON_BIOS16(tmp + i * 10 + 0x10);
     766                }
     767                found = TRUE;
     768            } else if (RADEON_BIOS8(tmp) == 4) {
     769                int stride = 0;
     770                n = RADEON_BIOS8(tmp + 5) + 1;
     771                if (n > 4)
     772                    n = 4;
     773                for (i = 0; i < n; i++) {
     774                    di->tmds_pll[i].value = RADEON_BIOS32(tmp + stride + 0x08);
     775                    di->tmds_pll[i].freq = RADEON_BIOS16(tmp + stride + 0x10);
     776                    if (i == 0)
     777                        stride += 10;
     778                    else
     779                        stride += 6;
     780                }
     781                found = TRUE;
     782            }
     783   
     784            // revision 4 has some problem as it appears in RV280,
     785            // comment it off for now, use default instead   
     786            /*
     787                else if (RADEON_BIOS8(tmp) == 4) {
     788                int stride = 0;
     789                n = RADEON_BIOS8(tmp + 5) + 1;
     790                if (n > 4) n = 4;
     791                for (i = 0; i < n; i++) {
     792                    di->tmds_pll[i].value = RADEON_BIOS32(tmp + stride + 0x08);
     793                    di->tmds_pll[i].freq = RADEON_BIOS16(tmp + stride + 0x10);
     794                    if (i == 0)
     795                        stride += 10;
     796                    else
     797                        stride += 6;
     798                }
     799                found = TRUE;
     800            }
     801            */
     802           
     803        }
     804    }
     805   
     806    if (found == FALSE) {
     807        for (i = 0; i < 4; i++) {
     808            di->tmds_pll[i].value = default_tmds_pll[di->asic][i].value;
     809            di->tmds_pll[i].freq = default_tmds_pll[di->asic][i].freq;
     810            SHOW_ERROR( 2, "TMDS PLL from DEFAULTS: %ld %lx",
     811                di->tmds_pll[i].freq, di->tmds_pll[i].value);
     812        }
     813    }
     814}
     815
    695816/*
    696817// get everything in terms of monitors connected to the card
    697818static void Radeon_GetBIOSMon( device_info *di )
    … …  
    9641085    di->routing.port_info[0].dac_type = dac_unknown;
    9651086    di->routing.port_info[0].tmds_type = tmds_unknown;
    9661087    di->routing.port_info[0].connector_type = connector_none;
     1088
     1089    di->routing.port_info[1].mon_type = mt_unknown;
     1090    di->routing.port_info[1].ddc_type = ddc_none_detected;
     1091    di->routing.port_info[1].dac_type = dac_unknown;
     1092    di->routing.port_info[1].tmds_type = tmds_unknown;
     1093    di->routing.port_info[1].connector_type = connector_none;
    9671094   
    9681095    if ( !Radeon_GetConnectorInfoFromBIOS( di ) )
    9691096    {
    … …  
    9811108
    9821109    }
    9831110    Radeon_GetFPData( di );
     1111    Radeon_GetTMDSInfoFromBios( di );
    9841112    Radeon_DetectRAM( di );
    9851113   
    9861114    Radeon_UnmapDevice( di );

  • src/add-ons/accelerants/radeon/radeon_accelerant.h

     
    3232
    3333#define DEBUG_MSG_PREFIX "Radeon - "
    3434
    35 #define DEBUG_MAX_LEVEL_FLOW 2
     35#define DEBUG_MAX_LEVEL_FLOW 3
    3636
    3737#include "debug_ext.h"
    3838

  • src/add-ons/accelerants/radeon/ProposeDisplayMode.c

     
    148148    int eff_virtual_width;
    149149    fp_info *flatpanel = &si->flatpanels[crtc->flatpanel_port];
    150150
     151    SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port );
     152    SHOW_FLOW( 4, "X %d, virtX %d", target->timing.h_display,  target->virtual_width);
     153    SHOW_FLOW( 4, "fpRes %dx%d", flatpanel->panel_xres,  flatpanel->panel_yres);
     154
    151155    // save refresh rate - we want to leave this (artifical) value untouched
    152156    // don't use floating point, we are in kernel mode
    153157    target_refresh =
    … …  
    163167    // for flat panels, check maximum resolution;
    164168    // all the other tricks (like fixed resolution and resulting scaling)
    165169    // are done automagically by set_display_mode
    166     if( (crtc->chosen_displays & (dd_lvds | dd_dvi | dd_dvi_ext)) != 0 ) {
     170    if( (crtc->chosen_displays & (dd_lvds | dd_dvi)) != 0 ) {
    167171        if( target->timing.h_display > flatpanel->panel_xres )
    168172            target->timing.h_display = flatpanel->panel_xres;
    169173       
    … …  
    171175            target->timing.v_display = flatpanel->panel_yres;
    172176    }
    173177
     178    // for secondary flat panels there is no RMX unit for
     179    // scaling up lower resolutions.  Until we can do centered timings
     180    // we need to disable the screen unless it is the native resolution.
     181    // if the DVI input has a scaler we would need to know about it somehow...
     182    if( (crtc->chosen_displays & dd_dvi_ext) != 0 ) {
     183        SHOW_FLOW0( 4, "external (secondary) DVI cannot support non-native resolutions" );
     184        if( ( target->timing.h_display != flatpanel->panel_xres ) ||
     185            ( target->timing.v_display != flatpanel->panel_yres ) )
     186            return B_ERROR;
     187    }
     188
    174189/*
    175190    // the TV-Out encoder can "only" handle up to 1024x768
    176191    if( (head->chosen_displays & (dd_ctv | dd_stv)) != 0 ) {
    … …  
    325340    if( target->timing.pixel_clock / 10 > pll->max_pll_freq ||
    326341        target->timing.pixel_clock / 10 * 12 < pll->min_pll_freq )
    327342    {
    328         SHOW_ERROR( 2, "pixel_clock (%ld) out of range (%d, %d)", target->timing.pixel_clock,
     343        SHOW_ERROR( 4, "pixel_clock (%ld) out of range (%d, %d)", target->timing.pixel_clock,
    329344            pll->max_pll_freq * 10, pll->min_pll_freq / 12 );
    330345        return B_ERROR;
    331346    }
    … …  
    371386
    372387    // make sure we haven't shrunk virtual height too much
    373388    if (target->virtual_height < target->timing.v_display) {
    374         SHOW_ERROR( 2, "not enough memory for this mode (could show only %d of %d lines)",
     389        SHOW_ERROR( 4, "not enough memory for this mode (could show only %d of %d lines)",
    375390            target->virtual_height, target->timing.v_display );
    376391        return B_ERROR;
    377392    }
    … …  
    516531{
    517532    shared_info *si = ai->si;
    518533   
    519     fp_info *fp_info = &si->flatpanels[0];
     534    fp_info *fp_info = &si->flatpanels[0];  //todo fix the hardcoding what about ext dvi?
    520535   
    521     if( (ai->vc->connected_displays & (dd_dvi | dd_lvds)) != 0 ) {
     536    if( (ai->vc->connected_displays & (dd_dvi | dd_dvi_ext | dd_lvds)) != 0 ) {
    522537        display_mode mode;
    523        
     538        SHOW_FLOW0( 2, "" );
    524539        mode.virtual_width = mode.timing.h_display = fp_info->panel_xres;
    525540        mode.virtual_height = mode.timing.v_display = fp_info->panel_yres;
    526541       
    … …  
    631646    Radeon_DetectMultiMode( vc, target );
    632647    Radeon_VerifyMultiMode( vc, si, target );
    633648   
    634     SHOW_FLOW0( 3, "wished:" );
    635     SHOW_FLOW( 3, "H: %4d %4d %4d %4d (v=%4d)",
     649    SHOW_FLOW0( 2, "wished:" );
     650    SHOW_FLOW( 2, "H: %4d %4d %4d %4d (v=%4d)",
    636651        target->timing.h_display, target->timing.h_sync_start,
    637652        target->timing.h_sync_end, target->timing.h_total, target->virtual_width );
    638     SHOW_FLOW( 3, "V: %4d %4d %4d %4d (h=%4d)",
     653    SHOW_FLOW( 2, "V: %4d %4d %4d %4d (h=%4d)",
    639654        target->timing.v_display, target->timing.v_sync_start,
    640655        target->timing.v_sync_end, target->timing.v_total, target->virtual_height );
    641     SHOW_FLOW( 3, "clk: %ld", target->timing.pixel_clock );
     656    SHOW_FLOW( 2, "clk: %ld", target->timing.pixel_clock );
    642657   
    643658    // we must assure that each ProposeMode call doesn't tweak the mode in
    644659    // a way that it cannot be handled by the other port anymore
    … …  
    659674        result2 = B_OK;
    660675    }
    661676   
    662     SHOW_INFO0( 4, "got:" );
    663     SHOW_INFO( 4, "H: %4d %4d %4d %4d (v=%4d)",
     677    SHOW_INFO0( 2, "got:" );
     678    SHOW_INFO( 2, "H: %4d %4d %4d %4d (v=%4d)",
    664679        target->timing.h_display, target->timing.h_sync_start,
    665680        target->timing.h_sync_end, target->timing.h_total, target->virtual_width );
    666     SHOW_INFO( 4, "V: %4d %4d %4d %4d (h=%4d)",
     681    SHOW_INFO( 2, "V: %4d %4d %4d %4d (h=%4d)",
    667682        target->timing.v_display, target->timing.v_sync_start,
    668683        target->timing.v_sync_end, target->timing.v_total, target->virtual_height );
    669     SHOW_INFO( 4, "clk: %ld", target->timing.pixel_clock );
     684    SHOW_INFO( 2, "clk: %ld", target->timing.pixel_clock );
    670685
    671686    Radeon_HideMultiMode( vc, target );
    672687   

  • src/add-ons/accelerants/radeon/monitor_detection.c

     
    269269        RADEON_DAC_FORCE_DATA_SEL_RGB |
    270270        (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT ));
    271271       
    272     old_dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
     272    old_dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
    273273
    274274    // enable CRT mode of TV-DAC and enable comparator   
    275     tmp = old_dac_cntl2 | RADEON_DAC2_CLK_SEL_CRT | RADEON_DAC2_CMP_EN;
     275    tmp = old_dac_cntl2 | RADEON_DAC2_CLK_SEL_CRT | RADEON_DAC2_CMP_EN;
    276276   
    277     OUTREG( regs, RADEON_DAC_CNTL2, tmp );
     277    OUTREG( regs, RADEON_DAC_CNTL2, tmp );
    278278   
    279     snooze( 10000 );
     279    snooze( 10000 );
    280280   
    281     // check connection of blue data signal to see whether there is a CRT
     281    // check connection of blue data signal to see whether there is a CRT
    282282    found = (INREG( regs, RADEON_DAC_CNTL2 ) & RADEON_DAC2_CMP_OUT_B) != 0;
    283283   
    284     // clean up the mess
     284    // clean up the mess
    285285    OUTREG( regs, RADEON_DAC_CNTL2, old_dac_cntl2 );
    286286    OUTREG( regs, RADEON_DAC_EXT_CNTL, 0 );
    287287    OUTREG( regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl );
    … …  
    289289
    290290    OUTREGP( regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1 );
    291291   
    292     return found;
     292    return found;
    293293}
    294294
    295295
    … …  
    800800}
    801801   
    802802// read edid data of flat panel and setup its timing accordingly
    803 static status_t Radeon_StoreFPEDID( accelerator_info *ai, const edid1_info *edid )
     803static status_t Radeon_StoreFPEDID( accelerator_info *ai, int port, const edid1_info *edid )
    804804{
    805     fp_info *fp = &ai->si->flatpanels[0];
     805    fp_info *fp = &ai->si->flatpanels[port];
    806806    uint32 max_hsize, max_vsize;
    807807
    808808    //SHOW_FLOW0( 2, "EDID data read from DVI port via DDC2:" );
    … …  
    954954    // use DDC to detect monitors - if we can read DDC, there must be a monitor
    955955    for ( i = 0; i < 2; i++ )
    956956    {
    957         if (routes->port_info[i].mon_type != mt_unknown ) {
    958             SHOW_FLOW0( 2, "known type, skpping detection" );   
    959             continue;
    960         }
     957        //TODO could skip edid reading instead if we already have it, but what
     958        //if monitors have been hot swapped?  Also rely on edid for DVI-D detection
     959        //if (routes->port_info[i].mon_type != mt_unknown ) {
     960        //  SHOW_FLOW0( 2, "known type, skpping detection" );   
     961        //  continue;
     962        //}
    961963       
    962964        memset( &routes->port_info[i].edid , 0, sizeof(edid1_info) );
    963965        switch ( routes->port_info[i].ddc_type ) {
    … …  
    993995                // both LDVS and TMDS are disable, we still need to treat it as a LVDS panel.
    994996                if ( routes->port_info[i].tmds_type == tmds_ext ){
    995997                    // store info about DVI-connected flat-panel
    996                     if( Radeon_StoreFPEDID( ai, &routes->port_info[i].edid ) == B_OK ) {
     998                    if( Radeon_StoreFPEDID( ai, i, &routes->port_info[i].edid ) == B_OK ) {
    997999                        SHOW_INFO0( 2, "Found Ext Laptop DVI" );
    9981000                        routes->port_info[i].mon_type = mt_dfp;
     1001                        ai->si->flatpanels[i].is_fp2 = true;
    9991002                        displays |= dd_dvi_ext;
    10001003                    } else {
    10011004                        SHOW_ERROR0( 2, "Disabled Ext DVI - invalid EDID" );
    … …  
    10031006                } else {
    10041007                    if( INREG( ai->regs, RADEON_FP_GEN_CNTL) & (1 << 7) || ( !si->is_mobility ) ) {
    10051008                        // store info about DVI-connected flat-panel
    1006                         if( Radeon_StoreFPEDID( ai, &routes->port_info[i].edid ) == B_OK ) {
     1009                        if( Radeon_StoreFPEDID( ai, i, &routes->port_info[i].edid ) == B_OK ) {
    10071010                            SHOW_INFO0( 2, "Found DVI" );
    10081011                            routes->port_info[i].mon_type = mt_dfp;
    10091012                            displays |= dd_dvi;
    … …  
    10151018                        routes->port_info[i].mon_type = mt_lcd;
    10161019                        displays |= dd_lvds;
    10171020                    }
     1021                    ai->si->flatpanels[1].is_fp2 = FALSE;
    10181022                }
    10191023            } else {
    10201024                // must be the analog portion of DVI
    … …  
    10491053        if ( si->is_mobility && (INREG( ai->regs, RADEON_FP2_GEN_CNTL) & RADEON_FP2_FPON)) {
    10501054            SHOW_INFO0( 2, "Found Ext Laptop DVI" );
    10511055            routes->port_info[1].mon_type = mt_dfp;
    1052             displays |= dd_dvi;
     1056            displays |= dd_dvi_ext;
    10531057        }
    10541058    }
    10551059   

  • src/add-ons/accelerants/radeon/SetDisplayMode.c

     
    2323#include "fp_regs.h"
    2424#include "gpiopad_regs.h"
    2525
     26#include "pll_regs.h"
     27#include "tv_out_regs.h"
     28#include "config_regs.h"
     29#include "ddc_regs.h"
     30#include "pll_access.h"
     31#include "theatre_regs.h"
    2632#include "set_mode.h"
     33#include "ddc.h"
    2734
     35#include "set_mode.h"
     36
    2837#include <string.h>
    2938
    30 void Radeon_SetMode(
     39status_t Radeon_SetMode(
    3140    accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params );
    3241
    3342// round virtual width up to next valid size
    … …  
    94103
    95104// set display mode of one head;
    96105// port restrictions, like fixed-sync TFTs connected to it, are taken care of
    97 void Radeon_SetMode(
     106status_t Radeon_SetMode(
    98107    accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params )
    99108{
    100109    virtual_card *vc = ai->vc;
    … …  
    126135    // is determined by the physical resolution;
    127136    // also, all timing is fixed
    128137    if( (disp_devices & (dd_lvds | dd_dvi | dd_dvi_ext)) != 0 ) {
     138        SHOW_FLOW0( 0, "requested resolution higher than native panel" );
    129139        if( mode->timing.h_display > fp_info->panel_xres )
    130140            mode->timing.h_display = fp_info->panel_xres;
    131141        if( mode->timing.v_display > fp_info->panel_yres )
    132142            mode->timing.v_display = fp_info->panel_yres;
    133143       
     144        if( (disp_devices & dd_dvi_ext) != 0 ) {
     145            SHOW_FLOW0( 0, "requested resolution less than second native panel" );
     146            if( mode->timing.h_display < fp_info->panel_xres )
     147                mode->timing.h_display = fp_info->panel_xres;
     148            if( mode->timing.v_display < fp_info->panel_yres )
     149                mode->timing.v_display = fp_info->panel_yres;
     150
     151            //TODO at this point we know we are going to do centered timing
     152            //need to set flags to a. blank the unused memory, b.center screen
     153            //for now it's in the top corner, and surrounded by garbage.
     154            // although if the DVI panels are the same size and we are cloning
     155            // we can switch the FP2 source to RMX, and drive both screens from
     156            // the RMX unit.
     157        }
    134158        mode->timing.h_total = mode->timing.h_display + fp_info->h_blank;
    135159        mode->timing.h_sync_start = mode->timing.h_display + fp_info->h_over_plus;
    136160        mode->timing.h_sync_end = mode->timing.h_sync_start + fp_info->h_sync_width;
    … …  
    254278            Radeon_TheatreProgramTVRegisters( ai, &impactv_values );
    255279    }
    256280
     281    // spit out some debug stuff in a radeontool stylee
     282    SHOW_FLOW0( 0, "" );
     283    SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
     284    SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 ));
     285    SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL ));
     286    SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL ));
     287    SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL ));
     288    SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL ));
     289    SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL ));
     290    SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));
     291    SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL ));
     292    SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( regs, RADEON_FP_GEN_CNTL ));
     293    SHOW_FLOW( 0, "RADEON_FP2_GEN_CNTL %08X ", INREG( regs, RADEON_FP2_GEN_CNTL ));
     294    SHOW_FLOW( 0, "RADEON_LVDS_GEN_CNTL %08X ", INREG( regs, RADEON_LVDS_GEN_CNTL ));
     295    SHOW_FLOW( 0, "RADEON_TMDS_PLL_CNTL %08X ", INREG( regs, RADEON_TMDS_PLL_CNTL ));
     296    SHOW_FLOW( 0, "RADEON_TMDS_TRANSMITTER_CNTL %08X ", INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL ));
     297    SHOW_FLOW( 0, "RADEON_FP_H_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H_SYNC_STRT_WID ));
     298    SHOW_FLOW( 0, "RADEON_FP_V_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V_SYNC_STRT_WID ));
     299    SHOW_FLOW( 0, "RADEON_FP_H2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ));
     300    SHOW_FLOW( 0, "RADEON_FP_V2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ));
     301    // spit end
     302
    257303    crtc->active_displays = disp_devices;
    258304   
    259305    // programming is over, so hardware can be used again
    … …  
    263309    // TBD: this won't work if another virtual card was using it,
    264310    // but currently, virtual cards don't work anyway...
    265311    si->active_overlay.crtc_idx = -1;
     312
     313    return B_OK;
    266314}
    267315
    268316
    … …  
    432480    {
    433481        routing_regs routing_values;
    434482        impactv_params tv_params;
     483        status_t err1 , err2;
     484        err1 = err2 = B_OK;
    435485   
    436486        // we first switch off all output, so the monitor(s) won't get invalid signals
    437487        if( vc->assigned_crtc[0] ) {
    … …  
    451501   
    452502        // then change the mode
    453503        if( vc->used_crtc[0] )
    454             Radeon_SetMode( ai, &si->crtc[0], &mode, &tv_params );
     504            err1 = Radeon_SetMode( ai, &si->crtc[0], &mode, &tv_params );
    455505        if( vc->used_crtc[1] )
    456             Radeon_SetMode( ai, &si->crtc[1], &mode, &tv_params );
     506            err2 = Radeon_SetMode( ai, &si->crtc[1], &mode, &tv_params );
    457507           
     508       
     509        SHOW_FLOW( 2, "SetModes 1=%s, 2=%s",
     510            (err1 == B_OK) ? "OK" : "FAIL", (err2 == B_OK) ? "OK" : "FAIL");
     511
    458512        // setup signal routing
    459513        Radeon_ReadMonitorRoutingRegs( ai, &routing_values );
    460514        Radeon_CalcMonitorRouting( ai, &tv_params, &routing_values );
    … …  
    462516       
    463517        // finally, switch display(s) on
    464518        if( vc->used_crtc[0] )
    465             Radeon_SetDPMS( ai, 0, B_DPMS_ON );
     519            Radeon_SetDPMS( ai, 0, (err1 == B_OK) ? B_DPMS_ON : B_DPMS_SUSPEND );
    466520        if( vc->used_crtc[1] )
    467             Radeon_SetDPMS( ai, 1, B_DPMS_ON );
     521            Radeon_SetDPMS( ai, 1, (err2 == B_OK) ? B_DPMS_ON : B_DPMS_SUSPEND );
    468522           
    469523        OUTREGP( ai->regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );
    470524    }

  • src/add-ons/accelerants/radeon/monitor_routing.c

     
    634634        else if( ai->si->num_crtc > 1 && (crtc2_displays & ~(dd_stv | dd_ctv)) == 0 && vc->assigned_crtc[1] )
    635635            crtc2_displays |= dd_tv_crt;
    636636    }
     637
     638    if( (display_devices & dd_dvi_ext) != 0 )
     639        crtc2_displays |= dd_dvi_ext;
     640
     641    SHOW_FLOW( 2, "CRTC1: 0x%x, CRTC2: 0x%x", crtc1_displays, crtc2_displays );
    637642   
    638     SHOW_FLOW( 3, "CRTC1: 0x%x, CRTC2: 0x%x", crtc1_displays, crtc2_displays );
    639    
    640643    *crtc1 = crtc1_displays;
    641644    *crtc2 = crtc2_displays;
    642645}
    … …  
    651654    shared_info *si = ai->si;
    652655    display_device_e display_devices = vc->connected_displays;
    653656
    654     if (ai->si->settings.force_lcd) {   
     657    if (ai->si->settings.force_lcd) {
    655658        use_laptop_panel = true;
    656659        SHOW_FLOW0( 2,  "LCD Forced Used by Kernel Settings");
    657660    }

  • src/add-ons/accelerants/radeon/set_mode.h

     
    9898typedef struct {
    9999    uint32      fp_gen_cntl;
    100100    uint32      fp_panel_cntl;
    101     uint32      lvds_gen_cntl;
     101    uint32      lvds_gen_cntl;
     102    uint32      tmds_pll_cntl;
     103    uint32      tmds_trans_cntl;
    102104    uint32      fp_h_sync_strt_wid;
    103105    uint32      fp_v_sync_strt_wid;
    104106    uint32      fp2_gen_cntl;
    105107   
    106     uint32      fp2_h_sync_strt_wid;
     108    uint32      fp2_h_sync_strt_wid;
    107109    uint32      fp2_v_sync_strt_wid;
    108110   
    109111    // RMX registers
    110112    uint32      fp_horz_stretch;
    111     uint32      fp_vert_stretch;
     113    uint32      fp_vert_stretch;
    112114
    113115    // Bios values used by Mobility Asics
    114116    uint32      bios_4_scratch;

  • src/add-ons/accelerants/radeon/flat_panel.c

     
    108108    accelerator_info *ai, fp_regs *values )
    109109{
    110110    vuint8 *regs = ai->regs;
    111 
     111    SHOW_FLOW0( 2, "" );
    112112    OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );
    113113    OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );
    114114}
    … …  
    119119{
    120120    vuint8 *regs = ai->regs;
    121121
    122     values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
    123     values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
    124     values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
     122    values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
     123    values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
     124    values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
     125    values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );
     126    values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );
    125127    values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
    126128    values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
    127129    values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID );
    … …  
    130132    values->bios_5_scratch =  INREG( regs, RADEON_BIOS_5_SCRATCH );
    131133    values->bios_6_scratch =  INREG( regs, RADEON_BIOS_6_SCRATCH );
    132134
    133     SHOW_FLOW( 2, "before: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
    134         values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
    135         values->lvds_gen_cntl );
     135    if (ai->si->asic == rt_rv280) {
     136        // bit 22 of TMDS_PLL_CNTL is read-back inverted
     137        values->tmds_pll_cntl ^= (1 << 22);
     138    }
     139
     140    SHOW_FLOW( 2, "before: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
     141            values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
     142            values->lvds_gen_cntl );
    136143}
    137144
    138145// calculcate flat panel crtc registers;
    … …  
    141148    accelerator_info *ai, crtc_info *crtc,
    142149    fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values )
    143150{
     151    int i;
     152    uint32 tmp = values->tmds_pll_cntl & 0xfffff;
     153
    144154    // setup synchronization position
    145155    // (most values are ignored according to fp_gen_cntl, but at least polarity
    146156    //  and pixel precise horizontal sync position are always used)
    147157    if( fp_port->is_fp2 ) {
     158        SHOW_FLOW0( 2, "is_fp2" );
    148159        values->fp2_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid;
    149160        values->fp2_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid;
    150161    } else {
     162        SHOW_FLOW0( 2, "fp1" );
    151163        values->fp_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid;
    152164        values->fp_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid;
    153165    }
    154166
    155     if( fp_port->is_fp2 )
    156         values->fp2_gen_cntl = 0;
    157     else {
     167    if( fp_port->is_fp2 ) {
     168        // should retain POST values (esp bit 28)
     169        values->fp2_gen_cntl &= (0xFFFF0000);
     170
     171    } else {
    158172        // setup magic CRTC shadowing   
    159173        values->fp_gen_cntl &=
    160174            ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
    … …  
    169183            RADEON_FP_CRTC_DONT_SHADOW_HEND;
    170184    }
    171185   
     186    for (i = 0; i < 4; i++) {
     187        if (ai->si->tmds_pll[i].freq == 0)
     188            break;
     189        if ((uint32)(fp_port->dot_clock) < ai->si->tmds_pll[i].freq) {
     190            tmp = ai->si->tmds_pll[i].value ;
     191            break;
     192        }
     193    }
     194
     195    if (IS_R300_VARIANT || (ai->si->asic == rt_rv280)) {
     196        if (tmp & 0xfff00000) {
     197            values->tmds_pll_cntl = tmp;
     198        } else {
     199            values->tmds_pll_cntl = ai->si->tmds_pll_cntl & 0xfff00000;
     200            values->tmds_pll_cntl |= tmp;
     201        }
     202    } else {
     203        values->tmds_pll_cntl = tmp;
     204    }
     205
     206    values->tmds_trans_cntl = ai->si->tmds_transmitter_cntl
     207        & ~(RADEON_TMDS_TRANSMITTER_PLLRST);
     208
     209    if (IS_R300_VARIANT || (ai->si->asic == rt_r200) || (ai->si->num_crtc == 1))
     210        values->tmds_trans_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
     211    else // weird, RV chips got this bit reversed?
     212        values->tmds_trans_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
     213
     214
    172215    // enable proper transmitter   
    173216    if( (crtc->chosen_displays & dd_lvds) != 0 ) {
    174217        // using LVDS means there cannot be a DVI monitor
     218        SHOW_FLOW0( 2, "lvds" );
    175219        values->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
    176220        values->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
    177221       
    178222    } else if( !fp_port->is_fp2 ) {
    179223        // DVI on internal transmitter
     224        SHOW_FLOW0( 2, "DVI INT" );
    180225        values->fp_gen_cntl |= RADEON_FP_FPON | RADEON_FP_TMDS_EN;
    181226        // enabling 8 bit data may be dangerous; BIOS should have taken care of that
    182227        values->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;
    183228       
    184229    } else {
    185230        // DVI on external transmitter
     231        SHOW_FLOW0( 2, "DVI EXT" );
    186232        values->fp2_gen_cntl |= RADEON_FP2_FPON | RADEON_FP_PANEL_FORMAT;
    187233        values->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
    188234       
     235        //hack in missing bits test...
     236        //values->fp2_gen_cntl |= (1 << 22) | (1 << 28);
     237
    189238        if( ai->si->asic >= rt_r200 )
    190239            values->fp2_gen_cntl |= RADEON_FP2_DV0_EN;
    191240    }
    192241       
    193     SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
    194         values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
     242    SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, fp2_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
     243        values->fp_gen_cntl, values->fp2_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
    195244        values->lvds_gen_cntl );
    196245}
    197246
    … …  
    209258    OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 );
    210259
    211260    if( fp_port->is_fp2 ) {
     261        SHOW_FLOW0( 2, "is_fp2" );
    212262        OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
     263            ~(RADEON_FP2_SOURCE_SEL_MASK | RADEON_FP2_SRC_SEL_MASK));
     264        OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
    213265            RADEON_FP2_SOURCE_SEL_CRTC2 | RADEON_FP2_SRC_SEL_CRTC2 );
    214266        OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid );
    215267        OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid );
    216268    } else {
     269        SHOW_FLOW0( 2, "is_fp1" );
    217270        OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid );
    218271        OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid );
    219272    }

  • headers/private/graphics/radeon/fp_regs.h

     
    3535#       define RADEON_FP2_PANEL_FORMAT          (1 <<  3)
    3636#       define RADEON_FP2_SOURCE_SEL_MASK       (3 << 10)
    3737#       define RADEON_FP2_SOURCE_SEL_CRTC2      (1 << 10)
     38#       define RADEON_FP2_SOURCE_SEL_RMX        (2 << 10)
    3839#       define RADEON_FP2_SRC_SEL_MASK          (3 << 13)
    3940#       define RADEON_FP2_SRC_SEL_CRTC2         (1 << 13)
    4041#       define RADEON_FP2_FP_POL                (1 << 16)
    … …  
    6869#       define RADEON_VERT_STRETCH_BLEND       (1     << 26)
    6970#       define RADEON_VERT_AUTO_RATIO_EN       (1     << 27)
    7071#       define RADEON_VERT_STRETCH_RESERVED    0xf1000000
     72
     73#define RADEON_TMDS_PLL_CNTL                0x02a8
     74#define RADEON_TMDS_TRANSMITTER_CNTL        0x02a4
     75#       define RADEON_TMDS_TRANSMITTER_PLLEN  1
     76#       define RADEON_TMDS_TRANSMITTER_PLLRST 2
     77
    7178#define RADEON_FP_H_SYNC_STRT_WID           0x02c4
    7279#define RADEON_FP_V_SYNC_STRT_WID           0x02c8
    7380
    … …  
    8087#       define RADEON_LVDS_DIGON            (1   << 18)
    8188#       define RADEON_LVDS_BLON             (1   << 19)
    8289#       define RADEON_LVDS_SEL_CRTC2        (1   << 23)
     90#define RADEON_LVDS_PLL_CNTL                0x02d4
     91#       define RADEON_HSYNC_DELAY_SHIFT     28
     92#       define RADEON_HSYNC_DELAY_MASK      (0xf << 28)
    8393
    8494#define RADEON_FP_CRTC2_H_TOTAL_DISP        0x0350
    8595#define RADEON_FP_CRTC2_V_TOTAL_DISP        0x0354

  • headers/private/graphics/radeon/radeon_interface.h

     
    348348    uint32 best_vco;            // preferred VCO frequency (0 for don't care)
    349349} pll_info;
    350350
     351// info for ext tmds pll
     352typedef struct {
     353    uint32 freq;
     354    uint32 value;
     355} tmds_pll_info;
    351356
    352357// one overlay buffer
    353358typedef struct overlay_buffer_node {
    … …  
    520525    uint16      device_id;      // PCI device id
    521526    uint8       revision;       // PCI device revision
    522527   
    523     //bool      has_crtc2;      // has second CRTC
    524528    radeon_type asic;           // ASIC version
    525     bool        is_mobility;    // mobility version
    526     bool        is_igp;         //  might need to know if it's an integrated chip
     529    bool        is_mobility;        // mobility version
     530    bool        is_igp;         // might need to know if it's an integrated chip
    527531    bool        is_atombios;
    528     tv_chip_type tv_chip;       // type of TV-Out encoder
     532
     533    tv_chip_type    tv_chip;        // type of TV-Out encoder
    529534    bool        new_pll;        // r300 style PLL
    530     bool        has_no_i2c;     // I2C is broken
    531     uint16      panel_pwr_delay;// delay for LCD backlight to stabilise
    532     uint8       theatre_channel;// VIP channel of Rage Theatre (if applicable)
     535    bool        has_no_i2c;         // I2C is broken
     536    uint16      panel_pwr_delay;    // delay for LCD backlight to stabilise
     537    uint8       theatre_channel;    // VIP channel of Rage Theatre (if applicable)
    533538       
    534539    general_pll_info    pll;
    535    
     540    tmds_pll_info       tmds_pll[4];
     541
    536542    area_id     regs_area;      // area of memory mapped registers
    537543    area_id     ROM_area;       // area of ROM
    538     //area_id       fb_area;    // area of frame buffer
    539544    void        *framebuffer_pci;   // physical address of frame buffer (aka local memory)
    540                                 // this is a hack needed by BeOS
     545                            // this is a hack needed by BeOS
    541546
    542547    crtc_info   crtc[2];        // info about each crtc
    543548    uint8       num_crtc;       // number of physical heads
    … …  
    557562    uint32  active_vc;          // currently selected virtual card in terms of 2D acceleration
    558563       
    559564    uint32  dac_cntl2;          // content of dac_cntl2 register
     565    uint32  tmds_pll_cntl;          // undocumented here be dragons
     566    uint32  tmds_transmitter_cntl;      // undocumented here be dragons
    560567
    561568    overlay_info    pending_overlay;    // overlay to be shown
    562569    overlay_info    active_overlay;     // overlay shown