| 1 | Kernel name: kernel_x86_64 built on: Oct 2 2019 10:44:56 version 0x1
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| 2 | 4 Intel Core™ i7-4600U, revision 40651 running at 2693MHz
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| 3 |
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| 4 | CPU #0: "Intel(R) Core(TM) i7-4600U CPU @ 2.10GHz"
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| 5 | Signature: 0x040651; Type 0, family 6, model 69, stepping 1
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| 6 | Features: 0xbfebfbff
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| 7 | FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT
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| 8 | PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE
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| 9 | Extended Features (0x00000001): 0x77fafbff
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| 10 | SSE3 PCLMULDQ DTES64 MONITOR DS-CPL VMX SMX EST TM2 SSSE3 SDBG FMA CX16 xTPR PDCM PCID
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| 11 | SSE4.1 SSE4.2 x2APIC MOVEB POPCNT TSC-DEADLINE AES XSAVE AVX F16C RDRND
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| 12 | Extended Features (0x80000001): 0x2c100800
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| 13 | SCE NX GBPAGES RDTSCP 64
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| 14 |
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| 15 | L2 Data cache fully associative, 1 lines/tag, 64 bytes/line
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| 16 | L2 cache: 256 KB, 8-way set associative, 0 lines/tag, 64 bytes/line
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| 17 |
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| 18 | Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries
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| 19 | Data TLB: 4k-byte pages, 4-way set associative, 64 entries
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| 20 | Code TLB: 2M/4M pages, fully associative, 8 entries
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| 21 | Code TLB: 4K-bytes pages, 8-way set associative, 64 entries
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| 22 | 64-byte Prefetching
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| 23 | L2 cache: 4K/2M bytes pages, 8-way set associative, 1024 entries
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| 24 |
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| 25 | CPU #1: "Intel(R) Core(TM) i7-4600U CPU @ 2.10GHz"
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| 26 | Signature: 0x040651; Type 0, family 6, model 69, stepping 1
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| 27 | Features: 0xbfebfbff
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| 28 | FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT
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| 29 | PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE
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| 30 | Extended Features (0x00000001): 0x77fafbff
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| 31 | SSE3 PCLMULDQ DTES64 MONITOR DS-CPL VMX SMX EST TM2 SSSE3 SDBG FMA CX16 xTPR PDCM PCID
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| 32 | SSE4.1 SSE4.2 x2APIC MOVEB POPCNT TSC-DEADLINE AES XSAVE AVX F16C RDRND
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| 33 | Extended Features (0x80000001): 0x2c100800
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| 34 | SCE NX GBPAGES RDTSCP 64
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| 35 |
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| 36 | L2 Data cache fully associative, 1 lines/tag, 64 bytes/line
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| 37 | L2 cache: 256 KB, 8-way set associative, 0 lines/tag, 64 bytes/line
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| 38 |
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| 39 | Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries
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| 40 | Data TLB: 4k-byte pages, 4-way set associative, 64 entries
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| 41 | Code TLB: 2M/4M pages, fully associative, 8 entries
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| 42 | Code TLB: 4K-bytes pages, 8-way set associative, 64 entries
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| 43 | 64-byte Prefetching
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| 44 | L2 cache: 4K/2M bytes pages, 8-way set associative, 1024 entries
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| 45 |
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| 46 | CPU #2: "Intel(R) Core(TM) i7-4600U CPU @ 2.10GHz"
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| 47 | Signature: 0x040651; Type 0, family 6, model 69, stepping 1
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| 48 | Features: 0xbfebfbff
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| 49 | FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT
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| 50 | PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE
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| 51 | Extended Features (0x00000001): 0x77fafbff
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| 52 | SSE3 PCLMULDQ DTES64 MONITOR DS-CPL VMX SMX EST TM2 SSSE3 SDBG FMA CX16 xTPR PDCM PCID
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| 53 | SSE4.1 SSE4.2 x2APIC MOVEB POPCNT TSC-DEADLINE AES XSAVE AVX F16C RDRND
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| 54 | Extended Features (0x80000001): 0x2c100800
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| 55 | SCE NX GBPAGES RDTSCP 64
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| 56 |
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| 57 | L2 Data cache fully associative, 1 lines/tag, 64 bytes/line
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| 58 | L2 cache: 256 KB, 8-way set associative, 0 lines/tag, 64 bytes/line
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| 59 |
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| 60 | Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries
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| 61 | Data TLB: 4k-byte pages, 4-way set associative, 64 entries
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| 62 | Code TLB: 2M/4M pages, fully associative, 8 entries
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| 63 | Code TLB: 4K-bytes pages, 8-way set associative, 64 entries
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| 64 | 64-byte Prefetching
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| 65 | L2 cache: 4K/2M bytes pages, 8-way set associative, 1024 entries
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| 66 |
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| 67 | CPU #3: "Intel(R) Core(TM) i7-4600U CPU @ 2.10GHz"
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| 68 | Signature: 0x040651; Type 0, family 6, model 69, stepping 1
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| 69 | Features: 0xbfebfbff
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| 70 | FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT
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| 71 | PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE
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|---|
| 72 | Extended Features (0x00000001): 0x77fafbff
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| 73 | SSE3 PCLMULDQ DTES64 MONITOR DS-CPL VMX SMX EST TM2 SSSE3 SDBG FMA CX16 xTPR PDCM PCID
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| 74 | SSE4.1 SSE4.2 x2APIC MOVEB POPCNT TSC-DEADLINE AES XSAVE AVX F16C RDRND
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| 75 | Extended Features (0x80000001): 0x2c100800
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| 76 | SCE NX GBPAGES RDTSCP 64
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| 77 |
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| 78 | L2 Data cache fully associative, 1 lines/tag, 64 bytes/line
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| 79 | L2 cache: 256 KB, 8-way set associative, 0 lines/tag, 64 bytes/line
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| 80 |
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| 81 | Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries
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| 82 | Data TLB: 4k-byte pages, 4-way set associative, 64 entries
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| 83 | Code TLB: 2M/4M pages, fully associative, 8 entries
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| 84 | Code TLB: 4K-bytes pages, 8-way set associative, 64 entries
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| 85 | 64-byte Prefetching
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| 86 | L2 cache: 4K/2M bytes pages, 8-way set associative, 1024 entries
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| 87 |
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| 88 | 7640719360 bytes free (used/max 601305088 / 8242024448)
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| 89 | (cached 566226944)
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| 90 | 64265 semaphores free (used/max 1271 / 65536)
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| 91 | 3916 ports free (used/max 180 / 4096)
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| 92 | 3928 threads free (used/max 168 / 4096)
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| 93 | 2025 teams free (used/max 23 / 2048)
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