Ticket #6686: atheros-port-fbsd-r211330-to-haiku-r38867.diff
File atheros-port-fbsd-r211330-to-haiku-r38867.diff, 64.3 KB (added by , 14 years ago) |
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src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416phy.h
111 111 112 112 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 113 113 114 #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 115 #define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 116 114 117 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 115 118 #define AR_PHY_REFCLKDLY 0x99f4 116 119 #define AR_PHY_REFCLKPD 0x99f8 -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar9160.ini
1 1 /* 2 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-200 8Atheros Communications, Inc.3 * Copyright (c) 2002-2009 Atheros Communications, Inc. 4 4 * 5 5 * Permission to use, copy, modify, and/or distribute this software for any 6 6 * purpose with or without fee is hereby granted, provided that the above … … 35 35 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 36 36 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 37 37 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 38 { 0x00009850, 0x6 d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },38 { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 }, 39 39 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, 40 { 0x0000985c, 0x3139 605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },40 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e }, 41 41 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, 42 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 42 43 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 43 44 { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 }, 44 45 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, 45 { 0x00009914, 0x000007d0, 0x00000 7d0, 0x00000898, 0x00000898, 0x000007d0 },46 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 46 47 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 47 48 { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, 48 { 0x00009944, 0x dfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },49 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 }, 49 50 { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, 50 51 { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, 51 52 { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, 52 53 { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 }, 53 54 { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce }, 55 { 0x000099bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 }, 54 56 { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 }, 55 57 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, 56 58 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, … … 212 214 { 0x00008134, 0x00000000 }, 213 215 { 0x00008138, 0x00000000 }, 214 216 { 0x0000813c, 0x00000000 }, 215 { 0x00008144, 0x 00000000},217 { 0x00008144, 0xffffffff }, 216 218 { 0x00008168, 0x00000000 }, 217 219 { 0x0000816c, 0x00000000 }, 218 220 { 0x00008170, 0x32143320 }, … … 271 273 { 0x0000832c, 0x00000007 }, 272 274 { 0x00008330, 0x00000302 }, 273 275 { 0x00008334, 0x00000e00 }, 274 { 0x00008338, 0x00 000000 },276 { 0x00008338, 0x00ff0000 }, 275 277 { 0x0000833c, 0x00000000 }, 276 278 { 0x00008340, 0x000107ff }, 277 279 { 0x00009808, 0x00000000 }, … … 326 328 { 0x000099e4, 0xaaaaaaaa }, 327 329 { 0x000099e8, 0x3c466478 }, 328 330 { 0x000099ec, 0x0cc80caa }, 331 { 0x000099f0, 0x00000000 }, /* XXX adrian's addition: AR_PHY_CALMODE == 0 */ 329 332 { 0x000099fc, 0x00001042 }, 330 333 { 0x00009b00, 0x00000000 }, 331 334 { 0x00009b04, 0x00000001 }, … … 405 408 { 0x0000a244, 0x00007bb6 }, 406 409 { 0x0000a248, 0x0fff3ffc }, 407 410 { 0x0000a24c, 0x00000001 }, 408 { 0x0000a250, 0x0000 a000 },411 { 0x0000a250, 0x0000e000 }, 409 412 { 0x0000a254, 0x00000000 }, 410 413 { 0x0000a258, 0x0cc75380 }, 411 414 { 0x0000a25c, 0x0f0f0f01 }, … … 425 428 { 0x0000a34c, 0x3fffffff }, 426 429 { 0x0000a350, 0x3fffffff }, 427 430 { 0x0000a354, 0x0003ffff }, 428 { 0x0000a358, 0x79 a8aa33 },431 { 0x0000a358, 0x79bfaa03 }, 429 432 { 0x0000d35c, 0x07ffffef }, 430 433 { 0x0000d360, 0x0fffffe7 }, 431 434 { 0x0000d364, 0x17ffffe5 }, -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416reg.h
127 127 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 128 128 #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 129 129 #define AR_PCU_TXBUF_CTRL 0x8340 130 #define AR_PCU_MISC_MODE2 0x8344 130 131 131 132 /* DMA & PCI Registers in PCI space (usable during sleep)*/ 132 133 #define AR_RC_AHB 0x00000001 /* AHB reset */ … … 244 245 #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 245 246 #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 246 247 248 #define AR_ISR_S5 0x0098 249 #define AR_ISR_S5_S 0x00d8 250 #define AR_ISR_S5_TIM_TIMER 0x00000010 251 247 252 #define AR_INTR_SPURIOUS 0xffffffff 248 253 #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 249 254 #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ … … 495 500 #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 496 501 #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 497 502 503 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 504 498 505 /* GPIO Interrupt */ 499 506 #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 500 507 #define AR_INTR_GPIO_S 20 … … 521 528 #define AR_GPIO_INTR_POL_VAL 0x1FFF 522 529 #define AR_GPIO_INTR_POL_VAL_S 0 523 530 531 #define AR_GPIO_JTAG_DISABLE 0x00020000 532 524 533 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 525 534 526 535 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF … … 603 612 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20) 604 613 #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 605 614 (AR_SREV_MERLIN_20(_ah) || \ 606 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)615 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 607 616 608 617 #define AR_SREV_KITE(_ah) \ 609 618 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar9285_reset.c
245 245 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 246 246 const struct ar5416eeprom_4k *eep = &ee->ee_base; 247 247 const MODAL_EEP4K_HEADER *pModal; 248 int i, regChainOffset; 249 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 248 uint8_t txRxAttenLocal = 23; 250 249 251 250 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 252 251 pModal = &eep->modalHeader; 253 252 254 /* NB: workaround for eeprom versions <= 14.2 */255 txRxAttenLocal = 23;256 257 253 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 258 for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) { 259 if (AR_SREV_MERLIN(ah)) { 260 if (i >= 2) break; 261 } 262 if (AR_SREV_OWL_20_OR_LATER(ah) && 263 (AH5416(ah)->ah_rx_chainmask == 0x5 || 264 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) { 265 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 266 * only chains 0 and 2 populated 267 */ 268 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 269 } else { 270 regChainOffset = i * 0x1000; 271 } 272 273 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 274 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 275 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 254 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]); 255 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, 256 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & 276 257 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 277 SM(pModal->iqCalICh[ i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |278 SM(pModal->iqCalQCh[ i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));258 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 259 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 279 260 280 /* 281 * Large signal upgrade. 282 * XXX update 283 */ 261 if (IS_EEP_MINOR_V3(ah)) { 262 if (IEEE80211_IS_CHAN_HT40(chan)) { 263 /* Overwrite switch settling with HT40 value */ 264 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 265 pModal->swSettleHt40); 266 } 267 txRxAttenLocal = pModal->txRxAttenCh[0]; 284 268 285 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 286 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 287 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) | 288 SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal, 289 AR_PHY_RXGAIN_TXRX_ATTEN)); 269 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 270 pModal->bswMargin[0]); 271 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 272 pModal->bswAtten[0]); 273 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 274 pModal->xatten2Margin[0]); 275 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 276 pModal->xatten2Db[0]); 290 277 291 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 292 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | 293 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); 294 } 278 /* block 1 has the same values as block 0 */ 279 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 280 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 281 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 282 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 283 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 284 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 285 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 286 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 287 295 288 } 289 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 290 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 291 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 292 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 296 293 297 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 298 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 299 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 300 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 301 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 302 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 303 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 304 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 294 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 295 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 296 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 297 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 305 298 306 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 299 if (AR_SREV_KITE_11(ah)) 300 OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 307 301 308 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,309 pModal->thresh62);310 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,311 pModal->thresh62);312 313 /* Minor Version Specific application */314 if (IS_EEP_MINOR_V2(ah)) {315 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);316 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);317 }318 319 if (IS_EEP_MINOR_V3(ah)) {320 if (IEEE80211_IS_CHAN_HT40(chan)) {321 /* Overwrite switch settling with HT40 value */322 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);323 }324 325 if ((AR_SREV_OWL_20_OR_LATER(ah)) &&326 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){327 /* Reg Offsets are swapped for logical mapping */328 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |329 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));330 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |331 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));332 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |333 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));334 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |335 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));336 } else {337 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |338 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));339 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |340 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));341 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |342 SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));343 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |344 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));345 }346 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);347 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);348 }349 302 return AH_TRUE; 350 303 } 351 304 … … 634 587 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 635 588 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 636 589 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 637 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM( xpdGainValues[2],AR_PHY_TPCRG1_PD_GAIN_3));590 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(0, AR_PHY_TPCRG1_PD_GAIN_3)); 638 591 639 592 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 640 593 … … 839 792 * for last gain, pdGainBoundary == Pmax_t2, so will 840 793 * have to extrapolate 841 794 */ 842 if (tgtIndex > maxIndex) { /* need to extrapolate above */795 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 843 796 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 844 797 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 845 798 (ss - maxIndex +1) * vpdStep)); -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_cal.c
24 24 25 25 #include "ah_eeprom_v14.h" 26 26 27 #include "ar5212/ar5212.h" /* for NF cal related declarations */ 28 27 29 #include "ar5416/ar5416.h" 28 30 #include "ar5416/ar5416reg.h" 29 31 #include "ar5416/ar5416phy.h" … … 219 221 * higher than normal value if DC offset and noise floor cal are 220 222 * triggered at the same time. 221 223 */ 224 /* XXX this actually kicks off a NF calibration -adrian */ 222 225 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 226 /* 227 * Try to make sure the above NF cal completes, just so 228 * it doesn't clash with subsequent percals -adrian 229 */ 230 if (! ar5212WaitNFCalComplete(ah, 10000)) { 231 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: initial NF calibration did " 232 "not complete in time; noisy environment?\n", __func__); 233 return AH_FALSE; 234 } 223 235 224 236 /* Initialize list pointers */ 225 237 cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL; … … 396 408 397 409 *isCalDone = AH_TRUE; 398 410 411 /* 412 * Since ath_hal calls the PerCal method with rxchainmask=0x1; 413 * override it with the current chainmask. The upper levels currently 414 * doesn't know about the chainmask. 415 */ 416 rxchainmask = AH5416(ah)->ah_rx_chainmask; 417 399 418 /* Invalid channel check */ 400 419 ichan = ath_hal_checkchannel(ah, chan); 401 420 if (ichan == AH_NULL) { … … 509 528 AR_PHY_CH2_EXT_CCA 510 529 }; 511 530 struct ar5212NfCalHist *h; 512 int i , j;531 int i; 513 532 int32_t val; 514 533 uint8_t chainmask; 515 534 … … 545 564 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 546 565 547 566 /* Wait for load to complete, should be fast, a few 10s of us. */ 548 for (j = 0; j < 1000; j++) { 549 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) 550 break; 551 OS_DELAY(10); 567 if (! ar5212WaitNFCalComplete(ah, 1000)) { 568 /* 569 * We timed out waiting for the noisefloor to load, probably due to an 570 * in-progress rx. Simply return here and allow the load plenty of time 571 * to complete before the next calibration interval. We need to avoid 572 * trying to load -50 (which happens below) while the previous load is 573 * still in progress as this can cause rx deafness. Instead by returning 574 * here, the baseband nf cal will just be capped by our present 575 * noisefloor until the next calibration timer. 576 */ 577 HALDEBUG(ah, HAL_DEBUG_ANY, "Timeout while waiting for nf " 578 "to load: AR_PHY_AGC_CONTROL=0x%x\n", 579 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 580 return; 552 581 } 553 582 554 583 /* … … 614 643 { 615 644 int16_t nf, nfThresh; 616 645 617 if ( OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {646 if (ar5212IsNFCalInProgress(ah)) { 618 647 HALDEBUG(ah, HAL_DEBUG_ANY, 619 648 "%s: NF didn't complete in calibration window\n", __func__); 620 649 nf = 0; -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar9285_attach.c
121 121 AH5416(ah)->ah_writeIni = ar9285WriteIni; 122 122 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; 123 123 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; 124 125 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1; 124 126 125 127 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 126 128 /* reset chip */ … … 314 316 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 315 317 1, regWrites); 316 318 319 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 320 321 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 322 uint32_t val; 323 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2) & 324 (~AR_PCU_MISC_MODE2_HWWAR1); 325 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 326 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 327 } 328 317 329 } 318 330 319 331 /* … … 376 388 case HAL_ANT_VARIABLE: 377 389 /* Restore original chainmask settings */ 378 390 /* XXX */ 379 ahp->ah_tx_chainmask = AR 5416_DEFAULT_TXCHAINMASK;380 ahp->ah_rx_chainmask = AR 5416_DEFAULT_RXCHAINMASK;391 ahp->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; 392 ahp->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; 381 393 break; 382 394 } 383 395 return AH_TRUE; -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416.ini
1 1 /* 2 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 200 2-2008 Atheros Communications,Inc.3 * Copyright (c) 2008-2009 Atheros Communications Inc. 4 4 * 5 5 * Permission to use, copy, modify, and/or distribute this software for any 6 6 * purpose with or without fee is hereby granted, provided that the above … … 24 24 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 25 25 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 26 26 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, 27 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801 080, 0x08400840, 0x06e006e0 },27 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, 28 28 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, 29 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 }, 30 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a }, 29 31 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 30 32 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 31 33 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 32 34 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 33 35 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 34 36 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 35 { 0x00009844, 0x1372161e, 0x13721 c1e, 0x13721c30, 0x137216a4, 0x13721c25},37 { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 }, 36 38 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 37 39 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 38 40 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 39 { 0x00009850, 0x6c 28b4e0, 0x6c28b4e0, 0x6d68b0de, 0x6d68b0de, 0x6c28b0de },41 { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de }, 40 42 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, 41 { 0x0000985c, 0x313 a5d5e, 0x313a5d5e, 0x313a605e, 0x313a605e, 0x313a5d5e },42 { 0x00009860, 0x00049d1 0, 0x00049d10, 0x00049d20, 0x00049d20, 0x00049d10},43 { 0x0000 c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },43 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e }, 44 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 }, 45 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 44 46 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 }, 45 47 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, 46 { 0x00009914, 0x000007d0, 0x00000 7d0, 0x00000898, 0x00000898, 0x000007d0 },47 { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000 370},48 { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a 19, 0xd0058a13, 0xd0058a0b },49 { 0x00009944, 0x dfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },48 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 49 { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 }, 50 { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b }, 51 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 }, 50 52 #ifdef TB243 51 53 { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 }, 52 54 { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 }, … … 63 65 #endif 64 66 #endif 65 67 { 0x0000c9bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 }, 68 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 }, 69 { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 }, 66 70 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, 67 71 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 68 { 0x000099c8, 0x6 0f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },72 { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c }, 69 73 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 70 74 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 71 75 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 72 76 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 73 { 0x0000a204, 0x00000 440, 0x00000440, 0x00000440, 0x00000440, 0x00000440 },77 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 }, 74 78 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 }, 75 79 { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 }, 76 80 { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 }, … … 219 223 { 0x00008110, 0x00000168 }, 220 224 { 0x00008118, 0x000100aa }, 221 225 { 0x0000811c, 0x00003210 }, 222 { 0x00008120, 0x08f04800 },223 226 { 0x00008124, 0x00000000 }, 224 227 { 0x00008128, 0x00000000 }, 225 228 { 0x0000812c, 0x00000000 }, … … 227 230 { 0x00008134, 0x00000000 }, 228 231 { 0x00008138, 0x00000000 }, 229 232 { 0x0000813c, 0x00000000 }, 230 { 0x00008144, 0x 00000000},233 { 0x00008144, 0xffffffff }, 231 234 { 0x00008168, 0x00000000 }, 232 235 { 0x0000816c, 0x00000000 }, 233 236 { 0x00008170, 0x32143320 }, … … 235 238 { 0x00008178, 0x00000100 }, 236 239 { 0x0000817c, 0x00000000 }, 237 240 { 0x000081c4, 0x00000000 }, 238 { 0x000081d0, 0x00003210 },239 241 { 0x000081ec, 0x00000000 }, 240 242 { 0x000081f0, 0x00000000 }, 241 243 { 0x000081f4, 0x00000000 }, … … 266 268 { 0x00008258, 0x00000000 }, 267 269 { 0x0000825c, 0x400000ff }, 268 270 { 0x00008260, 0x00080922 }, 271 { 0x00008264, 0xa8000010 }, 269 272 { 0x00008270, 0x00000000 }, 270 273 { 0x00008274, 0x40000000 }, 271 274 { 0x00008278, 0x003e4180 }, … … 286 289 { 0x0000832c, 0x00000007 }, 287 290 { 0x00008330, 0x00000302 }, 288 291 { 0x00008334, 0x00000e00 }, 289 { 0x00008338, 0x000 00000 },292 { 0x00008338, 0x00070000 }, 290 293 { 0x0000833c, 0x00000000 }, 291 294 { 0x00008340, 0x000107ff }, 292 295 { 0x00009808, 0x00000000 }, … … 297 300 { 0x0000982c, 0x0000a000 }, 298 301 { 0x00009830, 0x00000000 }, 299 302 { 0x0000983c, 0x00200400 }, 300 { 0x00009840, 0x206a0 16e },303 { 0x00009840, 0x206a002e }, 301 304 { 0x0000984c, 0x1284233c }, 302 305 { 0x00009854, 0x00000859 }, 303 306 { 0x00009900, 0x00000000 }, … … 319 322 { 0x00009958, 0x00081fff }, 320 323 { 0x0000c95c, 0x004b6a8e }, 321 324 { 0x0000c968, 0x000003ce }, 322 { 0x00009970, 0x190 c0514},325 { 0x00009970, 0x190fb515 }, 323 326 { 0x00009974, 0x00000000 }, 324 327 { 0x00009978, 0x00000001 }, 325 328 { 0x0000997c, 0x00000000 }, … … 334 337 { 0x000099a0, 0x00000000 }, 335 338 { 0x000099a4, 0x00000001 }, 336 339 { 0x000099a8, 0x001fff00 }, 337 { 0x000099ac, 0x000000 c4},340 { 0x000099ac, 0x00000000 }, 338 341 { 0x000099b0, 0x03051000 }, 339 342 { 0x000099dc, 0x00000000 }, 340 343 { 0x000099e0, 0x00000200 }, … … 426 429 { 0x0000a25c, 0x0f0f0f01 }, 427 430 { 0x0000a260, 0xdfa91f01 }, 428 431 { 0x0000a268, 0x00000000 }, 429 { 0x0000a26c, 0x0e bae9c6 },430 { 0x0000b26c, 0x0e bae9c6 },431 { 0x0000c26c, 0x0e bae9c6 },432 { 0x0000a26c, 0x0e79e5c6 }, 433 { 0x0000b26c, 0x0e79e5c6 }, 434 { 0x0000c26c, 0x0e79e5c6 }, 432 435 { 0x0000d270, 0x00820820 }, 433 436 { 0x0000a278, 0x1ce739ce }, 434 437 { 0x0000a27c, 0x051701ce }, … … 441 444 { 0x0000a350, 0x3fffffff }, 442 445 { 0x0000a354, 0x0003ffff }, 443 446 { 0x0000a358, 0x79a8aa1f }, 444 { 0x0000d35c, 0x0 66c420f },445 { 0x0000d360, 0x0f 282207 },446 { 0x0000d364, 0x17 601685 },447 { 0x0000d368, 0x1f 801104 },448 { 0x0000d36c, 0x37 a00c03 },449 { 0x0000d370, 0x3f c40883 },450 { 0x0000d374, 0x57 c00803 },451 { 0x0000d378, 0x5f d80682 },452 { 0x0000d37c, 0x7f e00482 },447 { 0x0000d35c, 0x07ffffef }, 448 { 0x0000d360, 0x0fffffe7 }, 449 { 0x0000d364, 0x17ffffe5 }, 450 { 0x0000d368, 0x1fffffe4 }, 451 { 0x0000d36c, 0x37ffffe3 }, 452 { 0x0000d370, 0x3fffffe3 }, 453 { 0x0000d374, 0x57ffffe3 }, 454 { 0x0000d378, 0x5fffffe2 }, 455 { 0x0000d37c, 0x7fffffe2 }, 453 456 { 0x0000d380, 0x7f3c7bba }, 454 457 { 0x0000d384, 0xf3307ff0 }, 455 458 { 0x0000a388, 0x08000000 }, … … 625 628 { 0x0000989c, 0x00dc0000, 0x00dc0000 }, 626 629 { 0x0000989c, 0x00110000, 0x00110000 }, 627 630 { 0x0000989c, 0x006100a8, 0x006100a8 }, 628 { 0x0000989c, 0x0042 1022, 0x00421022 },629 { 0x0000989c, 0x 001400df, 0x001400df },631 { 0x0000989c, 0x00423022, 0x00423022 }, 632 { 0x0000989c, 0x201400df, 0x201400df }, 630 633 { 0x0000989c, 0x00c40002, 0x00c40002 }, 631 634 { 0x0000989c, 0x003000f2, 0x003000f2 }, 632 635 { 0x0000989c, 0x00440016, 0x00440016 }, … … 634 637 { 0x0000989c, 0x0001805e, 0x0001805e }, 635 638 { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, 636 639 { 0x0000989c, 0x000000e1, 0x000000e1 }, 637 { 0x0000989c, 0x0000 2081, 0x00002081 },640 { 0x0000989c, 0x00007081, 0x00007081 }, 638 641 { 0x0000989c, 0x000000d4, 0x000000d4 }, 639 642 { 0x000098d0, 0x0000000f, 0x0010000f }, 640 643 }; … … 648 651 }; 649 652 650 653 static const uint32_t ar5416Addac[][2] = { 651 {0x0 989c, 0x00000000 },652 {0x0 989c, 0x00000003 },653 {0x0 989c, 0x00000000 },654 {0x0 989c, 0x0000000c },655 {0x0 989c, 0x00000000 },656 {0x0 989c, 0x00000030 },657 {0x0 989c, 0x00000000 },658 {0x0 989c, 0x00000000 },659 {0x0 989c, 0x00000000 },660 {0x0 989c, 0x00000000 },661 {0x0 989c, 0x00000000 },662 {0x0 989c, 0x00000000 },663 {0x0 989c, 0x00000000 },664 {0x0 989c, 0x00000000 },665 {0x0 989c, 0x00000000 },666 {0x0 989c, 0x00000000 },667 {0x0 989c, 0x00000000 },668 {0x0 989c, 0x00000000 },669 {0x0 989c, 0x00000060 },670 {0x0 989c, 0x00000000 },671 {0x0 989c, 0x00000000 },672 {0x0 989c, 0x00000000 },673 {0x0 989c, 0x00000000 },674 {0x0 989c, 0x00000000 },675 {0x0 989c, 0x00000000 },676 {0x0 989c, 0x00000000 },677 {0x0 989c, 0x00000000 },678 {0x0 989c, 0x00000000 },679 {0x0 989c, 0x00000000 },680 {0x0 989c, 0x00000000 },681 {0x0 989c, 0x00000000 },682 {0x0 989c, 0x00000058 },683 {0x0 989c, 0x00000000 },684 {0x0 989c, 0x00000000 },685 {0x0 989c, 0x00000000 },686 {0x0 989c, 0x00000000 },687 {0x0 98c4, 0x00000000 },654 {0x0000989c, 0x00000000 }, 655 {0x0000989c, 0x00000003 }, 656 {0x0000989c, 0x00000000 }, 657 {0x0000989c, 0x0000000c }, 658 {0x0000989c, 0x00000000 }, 659 {0x0000989c, 0x00000030 }, 660 {0x0000989c, 0x00000000 }, 661 {0x0000989c, 0x00000000 }, 662 {0x0000989c, 0x00000000 }, 663 {0x0000989c, 0x00000000 }, 664 {0x0000989c, 0x00000000 }, 665 {0x0000989c, 0x00000000 }, 666 {0x0000989c, 0x00000000 }, 667 {0x0000989c, 0x00000000 }, 668 {0x0000989c, 0x00000000 }, 669 {0x0000989c, 0x00000000 }, 670 {0x0000989c, 0x00000000 }, 671 {0x0000989c, 0x00000000 }, 672 {0x0000989c, 0x00000060 }, 673 {0x0000989c, 0x00000000 }, 674 {0x0000989c, 0x00000000 }, 675 {0x0000989c, 0x00000000 }, 676 {0x0000989c, 0x00000000 }, 677 {0x0000989c, 0x00000000 }, 678 {0x0000989c, 0x00000000 }, 679 {0x0000989c, 0x00000000 }, 680 {0x0000989c, 0x00000000 }, 681 {0x0000989c, 0x00000000 }, 682 {0x0000989c, 0x00000000 }, 683 {0x0000989c, 0x00000000 }, 684 {0x0000989c, 0x00000000 }, 685 {0x0000989c, 0x00000058 }, 686 {0x0000989c, 0x00000000 }, 687 {0x0000989c, 0x00000000 }, 688 {0x0000989c, 0x00000000 }, 689 {0x0000989c, 0x00000000 }, 690 {0x000098cc, 0x00000000 }, 688 691 }; 689 692 690 693 /* hand-crafted from code that does explicit register writes */ -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
120 120 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 121 121 } 122 122 123 if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) { 124 uint32_t isr5; 125 isr5 = OS_REG_READ(ah, AR_ISR_S5_S); 126 if (isr5 & AR_ISR_S5_TIM_TIMER) 127 *masked |= HAL_INT_TIM_TIMER; 128 } 129 123 130 /* Interrupt Mitigation on AR5416 */ 124 131 #ifdef AR5416_INT_MITIGATION 125 132 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_reset.c
170 170 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 171 171 172 172 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 173 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 174 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 173 175 176 if (AR_SREV_KITE(ah)) { 177 uint32_t val; 178 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 179 val &= ~AR_PHY_RIFS_INIT_DELAY; 180 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 181 } 182 174 183 AH5416(ah)->ah_writeIni(ah, chan); 175 184 176 185 /* Setup 11n MAC/Phy mode registers */ … … 436 445 static void 437 446 ar5416InitDMA(struct ath_hal *ah) 438 447 { 448 struct ath_hal_5212 *ahp = AH5212(ah); 439 449 440 450 /* 441 451 * set AHB_MODE not to do cacheline prefetches … … 454 464 OS_REG_WRITE(ah, AR_RXCFG, 455 465 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 456 466 457 /* XXX restore TX trigger level */ 467 /* restore TX trigger level */ 468 OS_REG_WRITE(ah, AR_TXCFG, 469 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | 470 SM(ahp->ah_txTrigLev, AR_FTRIG)); 458 471 459 472 /* 460 473 * Setup receive FIFO threshold to hold off TX activities … … 1015 1028 /* 1016 1029 * RTC reset and clear 1017 1030 */ 1031 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1018 1032 OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1019 1033 OS_DELAY(20); 1034 OS_REG_WRITE(ah, AR_RC, 0); 1035 1020 1036 OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1021 1037 1022 1038 /* … … 1992 2008 * for last gain, pdGainBoundary == Pmax_t2, so will 1993 2009 * have to extrapolate 1994 2010 */ 1995 if (tgtIndex > maxIndex) { /* need to extrapolate above */2011 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 1996 2012 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 1997 2013 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 1998 2014 (ss - maxIndex +1) * vpdStep)); -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_cal_iq.c
115 115 if (qCoff > 15) 116 116 qCoff = 15; 117 117 else if (qCoff <= -16) 118 qCoff = 16;118 qCoff = -16; 119 119 HALDEBUG(ah, HAL_DEBUG_PERCAL, 120 120 " : iCoff = 0x%x qCoff = 0x%x\n", iCoff, qCoff); 121 121 -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v1.c
112 112 { 113 113 HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; 114 114 uint16_t athvals[AR_EEPROM_ATHEROS_MAX]; /* XXX off stack */ 115 uint16_t protect, version, eeval;115 uint16_t protect, eeprom_version, eeval; 116 116 uint32_t sum; 117 117 int i, loc; 118 118 … … 138 138 HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", protect); 139 139 /* XXX check proper access before continuing */ 140 140 141 if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, & version)) {141 if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &eeprom_version)) { 142 142 HALDEBUG(ah, HAL_DEBUG_ANY, 143 143 "%s: unable to read EEPROM version\n", __func__); 144 144 return HAL_EEREAD; 145 145 } 146 if ((( version>>12) & 0xf) != 1) {146 if (((eeprom_version>>12) & 0xf) != 1) { 147 147 /* 148 148 * This code only groks the version 1 EEPROM layout. 149 149 */ 150 150 HALDEBUG(ah, HAL_DEBUG_ANY, 151 151 "%s: unsupported EEPROM version 0x%x found\n", 152 __func__, version);152 __func__, eeprom_version); 153 153 return HAL_EEVERSION; 154 154 } 155 155 … … 183 183 return HAL_ENOMEM; 184 184 } 185 185 186 ee->ee_version = version;186 ee->ee_version = eeprom_version; 187 187 ee->ee_protect = protect; 188 188 ee->ee_antenna = athvals[2]; 189 189 ee->ee_biasCurrents = athvals[3]; … … 243 243 } 244 244 245 245 AH_PRIVATE(ah)->ah_eeprom = ee; 246 AH_PRIVATE(ah)->ah_eeversion = version;246 AH_PRIVATE(ah)->ah_eeversion = eeprom_version; 247 247 AH_PRIVATE(ah)->ah_eepromDetach = v1EepromDetach; 248 248 AH_PRIVATE(ah)->ah_eepromGet = v1EepromGet; 249 249 AH_PRIVATE(ah)->ah_eepromSet = v1EepromSet; -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c
38 38 int i; 39 39 40 40 switch (param) { 41 case AR_EEP_NFTHRESH_5:42 *(int16_t *)val = pModal[0].noiseFloorThreshCh[0];43 return HAL_OK;44 41 case AR_EEP_NFTHRESH_2: 45 *(int16_t *)val = pModal [1].noiseFloorThreshCh[0];42 *(int16_t *)val = pModal->noiseFloorThreshCh[0]; 46 43 return HAL_OK; 47 44 case AR_EEP_MACADDR: /* Get MAC Address */ 48 45 sum = 0; … … 67 64 return pBase->opCapFlags; 68 65 case AR_EEP_RFSILENT: 69 66 return pBase->rfSilent; 70 case AR_EEP_OB_5:71 return pModal[CHAN_A_IDX].ob;72 case AR_EEP_DB_5:73 return pModal[CHAN_A_IDX].db;74 67 case AR_EEP_OB_2: 75 return pModal [CHAN_B_IDX].ob;68 return pModal->ob; 76 69 case AR_EEP_DB_2: 77 return pModal [CHAN_B_IDX].db;70 return pModal->db; 78 71 case AR_EEP_TXMASK: 79 72 return pBase->txMask; 80 73 case AR_EEP_RXMASK: … … 84 77 case AR_EEP_TXGAIN_TYPE: 85 78 return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ? 86 79 pBase->txGainType : AR5416_EEP_TXGAIN_ORIG; 87 #if 088 80 case AR_EEP_OL_PWRCTRL: 89 81 HALASSERT(val == AH_NULL); 90 return pBase->openLoopPwrCntl ? HAL_OK : HAL_EIO; 91 #endif 82 return HAL_EIO; 92 83 case AR_EEP_AMODE: 93 84 HALASSERT(val == AH_NULL); 94 85 return pBase->opCapFlags & AR5416_OPFLAGS_11A ? … … 110 101 case AR_EEP_AES: 111 102 case AR_EEP_BURST: 112 103 case AR_EEP_RFKILL: 113 case AR_EEP_TURBO5DISABLE:114 104 case AR_EEP_TURBO2DISABLE: 115 105 HALASSERT(val == AH_NULL); 116 106 return HAL_OK; 117 107 case AR_EEP_ANTGAINMAX_2: 118 *(int8_t *) val = ee->ee_antennaGainMax [1];108 *(int8_t *) val = ee->ee_antennaGainMax; 119 109 return HAL_OK; 120 case AR_EEP_ANTGAINMAX_5:121 *(int8_t *) val = ee->ee_antennaGainMax[0];122 return HAL_OK;123 110 default: 124 111 HALASSERT(0); 125 112 return HAL_EINVAL; … … 136 123 137 124 switch (param) { 138 125 case AR_EEP_ANTGAINMAX_2: 139 ee->ee_antennaGainMax [1]= (int8_t) v;126 ee->ee_antennaGainMax = (int8_t) v; 140 127 return HAL_OK; 141 case AR_EEP_ANTGAINMAX_5:142 ee->ee_antennaGainMax[0] = (int8_t) v;143 return HAL_OK;144 128 } 145 129 return HAL_EINVAL; 146 130 } … … 252 236 RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; 253 237 int i, j; 254 238 255 HALASSERT(AR5416_ NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES);239 HALASSERT(AR5416_4K_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); 256 240 257 241 for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) { 258 242 for (j = 0; j < NUM_EDGES; j ++) { -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.h
23 23 #include "ah_eeprom.h" 24 24 #include "ah_eeprom_v14.h" 25 25 26 #define AR9285_RDEXT_DEFAULT 0x1F 27 26 28 #undef owl_eep_start_loc 27 29 #ifdef __LINUX_ARM_ARCH__ /* AP71 */ 28 30 #define owl_eep_start_loc 0 … … 150 152 uint16_t ee_numCtls; 151 153 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS]; 152 154 /* XXX these are dynamically calculated for use by shared code */ 153 int8_t ee_antennaGainMax [2];155 int8_t ee_antennaGainMax; 154 156 } HAL_EEPROM_v4k; 155 157 #endif /* _AH_EEPROM_V4K_H_ */ -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_reset.c
526 526 /* AGC calibration (this was added to make the NF threshold check work) */ 527 527 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 528 528 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL); 529 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) 529 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) { 530 530 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n", 531 531 __func__); 532 } 532 533 533 534 /* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */ 534 535 OS_REG_WRITE(ah, 0x9858, reg9858); -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_internal.h
334 334 (_ah)->ah_configPCIE(_ah, _reset) 335 335 #define ath_hal_disablePCIE(_ah) \ 336 336 (_ah)->ah_disablePCIE(_ah) 337 #define ath_hal_setInterrupts(_ah, _mask) \ 338 (_ah)->ah_setInterrupts(_ah, _mask) 337 339 338 340 #define ath_hal_eepromDetach(_ah) do { \ 339 341 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_reset.c
46 46 } CHAN_INFO_2GHZ; 47 47 48 48 #define CI_2GHZ_INDEX_CORRECTION 19 49 const staticCHAN_INFO_2GHZ chan2GHzData[] = {49 static const CHAN_INFO_2GHZ chan2GHzData[] = { 50 50 { 1, 0x46, 96 }, /* 2312 -19 */ 51 51 { 1, 0x46, 97 }, /* 2317 -18 */ 52 52 { 1, 0x46, 98 }, /* 2322 -17 */ … … 926 926 927 927 if (!getNoiseFloorThresh(ah, chan, &nfThresh)) 928 928 return AH_FALSE; 929 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) 929 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 930 930 HALDEBUG(ah, HAL_DEBUG_ANY, 931 931 "%s: NF did not complete in calibration window\n", __func__); 932 } 932 933 nf = ar5211GetNoiseFloor(ah); 933 934 if (nf > nfThresh) { 934 935 HALDEBUG(ah, HAL_DEBUG_ANY, -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_attach.c
248 248 ahp->ah_acktimeout = (u_int) -1; 249 249 ahp->ah_ctstimeout = (u_int) -1; 250 250 ahp->ah_sifstime = (u_int) -1; 251 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 252 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 253 251 254 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 252 255 #undef N 253 256 } -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_xmit.c
48 48 uint32_t txcfg, curLevel, newLevel; 49 49 HAL_INT omask; 50 50 51 if (ahp->ah_txTrigLev >= ahp->ah_maxTxTrigLev) 52 return AH_FALSE; 53 51 54 /* 52 55 * Disable interrupts while futzing with the fifo level. 53 56 */ 54 omask = a r5212SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);57 omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL); 55 58 56 59 txcfg = OS_REG_READ(ah, AR_TXCFG); 57 60 curLevel = MS(txcfg, AR_FTRIG); 58 61 newLevel = curLevel; 59 62 if (bIncTrigLevel) { /* increase the trigger level */ 60 if (curLevel < MAX_TX_FIFO_THRESHOLD)63 if (curLevel < ahp->ah_maxTxTrigLev) 61 64 newLevel++; 62 65 } else if (curLevel > MIN_TX_FIFO_THRESHOLD) 63 66 newLevel--; … … 66 69 OS_REG_WRITE(ah, AR_TXCFG, 67 70 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); 68 71 72 ahp->ah_txTrigLev = newLevel; 73 69 74 /* re-enable chip interrupts */ 70 a r5212SetInterrupts(ah, omask);75 ath_hal_setInterrupts(ah, omask); 71 76 72 77 return (newLevel != curLevel); 73 78 } -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_reset.c
283 283 regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 284 284 regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 285 285 regWrites); 286 #ifdef AH_RXCFG_SDMAMW_4BYTES 287 /* 288 * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx), 289 * use 4 instead. Enabling it on all platforms would hurt performance, 290 * so we only enable it on the ones that are affected by it. 291 */ 292 OS_REG_WRITE(ah, AR_RXCFG, 0); 293 #endif 286 294 ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 287 295 288 296 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h
327 327 uint16_t *ah_pcdacTable; 328 328 u_int ah_pcdacTableSize; 329 329 uint16_t ah_ratesArray[16]; 330 331 uint8_t ah_txTrigLev; /* current Tx trigger level */ 332 uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 330 333 }; 331 334 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 332 335 … … 605 608 const struct ieee80211_channel *); 606 609 extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 607 610 HAL_OPMODE, int); 611 612 extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 613 extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 614 608 615 #endif /* _ATH_AR5212_H_ */ -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_misc.c
1071 1071 } 1072 1072 return AH_FALSE; 1073 1073 } 1074 1075 /* 1076 * Check whether there's an in-progress NF completion. 1077 * 1078 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE 1079 * otherwise. 1080 */ 1081 HAL_BOOL 1082 ar5212IsNFCalInProgress(struct ath_hal *ah) 1083 { 1084 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) 1085 return AH_TRUE; 1086 return AH_FALSE; 1087 } 1088 1089 /* 1090 * Wait for an in-progress NF calibration to complete. 1091 * 1092 * The completion function waits "i" times 10uS. 1093 * It returns AH_TRUE if the NF calibration completed (or was never 1094 * in progress); AH_FALSE if it was still in progress after "i" checks. 1095 */ 1096 HAL_BOOL 1097 ar5212WaitNFCalComplete(struct ath_hal *ah, int i) 1098 { 1099 int j; 1100 if (i <= 0) 1101 i = 1; /* it should run at least once */ 1102 for (j = 0; j < i; j++) { 1103 if (! ar5212IsNFCalInProgress(ah)) 1104 return AH_TRUE; 1105 OS_DELAY(10); 1106 } 1107 return AH_FALSE; 1108 } -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
324 324 HAL_INT_RXORN = 0x00000020, 325 325 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 326 326 HAL_INT_TXDESC = 0x00000080, 327 HAL_INT_TIM_TIMER= 0x00000100, 327 328 HAL_INT_TXURN = 0x00000800, 328 329 HAL_INT_MIB = 0x00001000, 329 330 HAL_INT_RXPHY = 0x00004000, -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_athvar.h
306 306 u_int sc_txqsetup; /* h/w queues setup */ 307 307 u_int sc_txintrperiod;/* tx interrupt batching */ 308 308 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 309 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 309 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 310 310 struct task sc_txtask; /* tx int processing */ 311 311 int sc_wd_timer; /* count down for wd timer */ 312 312 struct callout sc_wd_ch; /* tx watchdog timer */ -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath.c
215 215 static int ath_raw_xmit(struct ieee80211_node *, 216 216 struct mbuf *, const struct ieee80211_bpf_params *); 217 217 static void ath_announce(struct ath_softc *); 218 static void ath_sysctl_stats_attach(struct ath_softc *sc); 218 219 219 220 #ifdef IEEE80211_SUPPORT_TDMA 220 221 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, … … 314 315 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 315 316 ATH_DEBUG_ANY = 0xffffffff 316 317 }; 317 static 318 static int ath_debug = ATH_DEBUG_INTR | 318 319 ATH_DEBUG_STATE | 319 320 ATH_DEBUG_REGDOMAIN; 320 321 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, … … 326 327 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 327 328 #define DPRINTF(sc, m, fmt, ...) do { \ 328 329 if (sc->sc_debug & (m)) \ 329 printf(fmt, __VA_ARGS__);\330 device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 330 331 } while (0) 331 332 #define KEYPRINTF(sc, ix, hk, mac) do { \ 332 333 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ … … 735 736 * regdomain are available from the hal. 736 737 */ 737 738 ath_sysctlattach(sc); 739 ath_sysctl_stats_attach(sc); 738 740 739 741 if (bootverbose) 740 742 ieee80211_announce(ic); … … 2832 2834 */ 2833 2835 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2834 2836 sc->sc_bmisscount++; 2837 sc->sc_stats.ast_be_missed++; 2835 2838 DPRINTF(sc, ATH_DEBUG_BEACON, 2836 2839 "%s: missed %u consecutive beacons\n", 2837 2840 __func__, sc->sc_bmisscount); … … 3663 3666 if (vap->iv_opmode == IEEE80211_M_IBSS && 3664 3667 vap->iv_state == IEEE80211_S_RUN) { 3665 3668 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3666 u _int64_t tsf = ath_extend_tsf(rstamp,3669 uint64_t tsf = ath_extend_tsf(rstamp, 3667 3670 ath_hal_gettsf64(sc->sc_ah)); 3668 3671 /* 3669 3672 * Handle ibss merge as needed; check the tsf on the … … 4004 4007 mtod(m, const struct ieee80211_frame_min *), 4005 4008 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4006 4009 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4010 sc->sc_lastrs = rs; 4007 4011 if (ni != NULL) { 4008 4012 /* 4009 4013 * Sending station is known, dispatch directly. 4010 4014 */ 4011 sc->sc_lastrs = rs;4012 4015 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 4013 4016 ieee80211_free_node(ni); 4014 4017 /* … … 5426 5429 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5427 5430 if (longCal) { 5428 5431 sc->sc_stats.ast_per_cal++; 5432 sc->sc_lastlongcal = ticks; 5429 5433 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5430 5434 /* 5431 5435 * Rfgain is out of bounds, reset the chip … … 5474 5478 nextcal *= 10; 5475 5479 } else { 5476 5480 nextcal = ath_longcalinterval*hz; 5477 sc->sc_lastlongcal = ticks;5478 5481 if (sc->sc_lastcalreset == 0) 5479 5482 sc->sc_lastcalreset = sc->sc_lastlongcal; 5480 5483 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) … … 7335 7338 } 7336 7339 } 7337 7340 #endif /* IEEE80211_SUPPORT_TDMA */ 7341 7342 static int 7343 ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS) 7344 { 7345 struct ath_softc *sc = arg1; 7346 int val = 0; 7347 int error; 7348 7349 error = sysctl_handle_int(oidp, &val, 0, req); 7350 if (error || !req->newptr) 7351 return error; 7352 if (val == 0) 7353 return 0; /* Not clearing the stats is still valid */ 7354 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 7355 val = 0; 7356 return 0; 7357 } 7358 7359 static void 7360 ath_sysctl_stats_attach(struct ath_softc *sc) 7361 { 7362 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 7363 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 7364 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 7365 7366 /* Create "clear" node */ 7367 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 7368 "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 7369 ath_sysctl_clearstats, "I", "clear stats"); 7370 7371 /* Create stats node */ 7372 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 7373 NULL, "Statistics"); 7374 child = SYSCTL_CHILDREN(tree); 7375 7376 /* This was generated from if_athioctl.h */ 7377 7378 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD, 7379 &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog"); 7380 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD, 7381 &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts"); 7382 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD, 7383 &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts"); 7384 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD, 7385 &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts"); 7386 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD, 7387 &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts"); 7388 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD, 7389 &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts"); 7390 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD, 7391 &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts"); 7392 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD, 7393 &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts"); 7394 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD, 7395 &sc->sc_stats.ast_mib, 0, "mib interrupts"); 7396 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD, 7397 &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced"); 7398 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD, 7399 &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface"); 7400 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD, 7401 &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted"); 7402 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD, 7403 &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc"); 7404 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD, 7405 &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer"); 7406 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD, 7407 &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed"); 7408 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD, 7409 &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node"); 7410 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD, 7411 &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf"); 7412 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD, 7413 &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster"); 7414 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD, 7415 &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster"); 7416 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD, 7417 &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame"); 7418 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD, 7419 &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs"); 7420 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD, 7421 &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries"); 7422 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD, 7423 &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun"); 7424 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD, 7425 &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered"); 7426 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD, 7427 &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)"); 7428 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD, 7429 &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)"); 7430 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD, 7431 &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate"); 7432 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD, 7433 &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked"); 7434 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD, 7435 &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled"); 7436 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD, 7437 &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled"); 7438 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD, 7439 &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble"); 7440 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD, 7441 &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate"); 7442 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD, 7443 &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection"); 7444 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD, 7445 &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting"); 7446 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD, 7447 &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension"); 7448 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD, 7449 &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf"); 7450 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD, 7451 &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs"); 7452 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD, 7453 &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun"); 7454 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD, 7455 &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC"); 7456 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD, 7457 &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun"); 7458 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD, 7459 &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption"); 7460 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD, 7461 &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure"); 7462 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD, 7463 &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err"); 7464 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD, 7465 &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short"); 7466 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD, 7467 &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large"); 7468 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD, 7469 &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface"); 7470 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD, 7471 &sc->sc_stats.ast_rx_mgt, 0, "management frames received"); 7472 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD, 7473 &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame"); 7474 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD, 7475 &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted"); 7476 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD, 7477 &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf"); 7478 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD, 7479 &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls"); 7480 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD, 7481 &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed"); 7482 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD, 7483 &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset"); 7484 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD, 7485 &sc->sc_stats.ast_rate_calls, 0, "rate control checks"); 7486 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD, 7487 &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate"); 7488 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD, 7489 &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate"); 7490 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD, 7491 &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches"); 7492 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD, 7493 &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches"); 7494 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD, 7495 &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted"); 7496 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD, 7497 &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy"); 7498 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD, 7499 &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api"); 7500 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD, 7501 &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully"); 7502 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD, 7503 &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error"); 7504 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD, 7505 &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd"); 7506 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD, 7507 &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q"); 7508 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD, 7509 &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit"); 7510 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD, 7511 &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer"); 7512 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD, 7513 &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates"); 7514 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD, 7515 &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers"); 7516 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD, 7517 &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF"); 7518 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD, 7519 &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required"); 7520 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD, 7521 &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down"); 7522 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD, 7523 &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer"); 7524 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD, 7525 &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons"); 7526 } -
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_athioctl.h
118 118 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 119 119 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 120 120 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 121 u_int32_t ast_pad[14]; 121 u_int32_t ast_be_missed; /* missed beacons */ 122 u_int32_t ast_pad[13]; 122 123 }; 123 124 124 125 #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)