| 1 | /*
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| 2 | * Copyright 2012-2013, Haiku, Inc. All Rights Reserved.
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| 3 | * Distributed under the terms of the MIT License.
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| 4 | *
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| 5 | * Authors:
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| 6 | * Alexander von Gluck IV, kallisti5@unixzen.com
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| 7 | */
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| 8 |
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| 9 |
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| 10 | #include "accelerant_protos.h"
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| 11 | #include "accelerant.h"
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| 12 |
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| 13 | #include <string.h>
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| 14 |
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| 15 |
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| 16 | status_t
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| 17 | intel_pm_downclock(bool enable)
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| 18 | {
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| 19 | if (!gInfo->shared_info->device_type.InGroup(GEN6_TYPE_SNB)
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| 20 | && !gInfo->shared_info->device_type.InGroup(GEN6_TYPE_IVB)) {
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| 21 | TRACE("%s: Downclocking not supported on this chipset.\n", __func__);
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| 22 | return B_ERROR;
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| 23 | }
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| 24 |
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| 25 | // TODO: Check for deep RC6
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| 26 | // IvyBridge, SandyBridge, and Haswell can do depth 1 atm
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| 27 | // Some chipsets can go deeper... but this is safe for now
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| 28 | // Haswell should *NOT* do over depth 1;
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| 29 | int depth = 1;
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| 30 |
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| 31 | /* Magical sequence of register writes to enable
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| 32 | * downclocking from the fine folks at Xorg
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| 33 | */
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| 34 | write32(GEN6_RC_STATE, 0);
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| 35 | // TODO: We may need grab rps states here
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| 36 | write32(GEN6_RC_CONTROL, 0);
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| 37 |
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| 38 | write32(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
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| 39 | write32(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
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| 40 | write32(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
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| 41 | write32(GEN6_RC_EVALUATION_INTERVAL, 125000);
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| 42 | write32(GEN6_RC_IDLE_HYSTERSIS, 25);
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| 43 |
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| 44 | // TODO: Idle each ring
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| 45 |
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| 46 | write32(GEN6_RC_SLEEP, 0);
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| 47 | write32(GEN6_RC1e_THRESHOLD, 1000);
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| 48 | write32(GEN6_RC6_THRESHOLD, 50000);
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| 49 | write32(GEN6_RC6p_THRESHOLD, 100000);
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| 50 | write32(GEN6_RC6pp_THRESHOLD, 64000);
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| 51 |
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| 52 | uint32 rc6Mask = GEN6_RC_CTL_RC6_ENABLE;
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| 53 |
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| 54 | if (depth > 1)
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| 55 | rc6Mask |= GEN6_RC_CTL_RC6p_ENABLE;
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| 56 | if (depth > 2)
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| 57 | rc6Mask |= GEN6_RC_CTL_RC6pp_ENABLE;
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| 58 |
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| 59 | write32(GEN6_RC_CONTROL, rc6Mask |
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| 60 | write32(GEN6_RPNSWREQ,
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| 61 | write32(GEN6_RC_VIDEO_FREQ,
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| 62 |
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| 63 | write32(GEN6_RP_DOWN_TIMEOUT, 1000000);
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| 64 | write32(GEN6_RP_INTERRUPT_LIMITS,
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| 65 | maxDelay << 24 | minDelay << 16);
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| 66 |
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| 67 | write32(GEN6_RP_UP_THRESHOLD, 59400);
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| 68 | write32(GEN6_RP_DOWN_THRESHOLD, 245000);
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| 69 | write32(GEN6_RP_UP_EI, 66000);
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| 70 | write32(GEN6_RP_DOWN_EI, 350000);
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| 71 |
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| 72 | write32(GEN6_RP_IDLE_HYSTERSIS, 10);
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| 73 | write32(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO
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| 74 | | GEN6_RP_MEDIA_HW_NORMAL_MODE | GEN6_RP_MEDIA_IS_GFX
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| 75 | | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG
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| 76 | | GEN6_RP_DOWN_IDLE_CONT);
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| 77 | // TODO: | (HASWELL ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
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| 78 |
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| 79 | // TODO: wait for (read32(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
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| 80 |
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| 81 | write32(GEN6_PCODE_DATA, 0);
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| 82 | write32(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY
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| 83 | | GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
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| 84 |
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| 85 | // TODO: wait for (read32(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
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| 86 |
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| 87 | // TODO: check for overclock support and set.
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| 88 |
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| 89 | }
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