diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp
index a817ec0..a6b33c4 100644
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b
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arch_cpu_init_post_modules(kernel_args* args)
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898 | 898 | void |
899 | 899 | arch_cpu_user_TLB_invalidate(void) |
900 | 900 | { |
| 901 | ktrace_printf("TLB invalidate all (non-global) on CPU %" B_PRId32, smp_get_current_cpu()); |
901 | 902 | x86_write_cr3(x86_read_cr3()); |
902 | 903 | } |
903 | 904 | |
… |
… |
arch_cpu_global_TLB_invalidate(void)
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910 | 911 | if (flags & IA32_CR4_GLOBAL_PAGES) { |
911 | 912 | // disable and reenable the global pages to flush all TLBs regardless |
912 | 913 | // of the global page bit |
| 914 | ktrace_printf("TLB invalidate all on CPU %" B_PRId32, smp_get_current_cpu()); |
913 | 915 | x86_write_cr4(flags & ~IA32_CR4_GLOBAL_PAGES); |
914 | 916 | x86_write_cr4(flags | IA32_CR4_GLOBAL_PAGES); |
915 | 917 | } else { |
… |
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arch_cpu_invalidate_TLB_range(addr_t start, addr_t end)
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925 | 927 | { |
926 | 928 | int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE; |
927 | 929 | while (num_pages-- >= 0) { |
| 930 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, start, smp_get_current_cpu()); |
928 | 931 | invalidate_TLB(start); |
929 | 932 | start += B_PAGE_SIZE; |
930 | 933 | } |
… |
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arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)
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936 | 939 | { |
937 | 940 | int i; |
938 | 941 | for (i = 0; i < num_pages; i++) { |
| 942 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, pages[i], smp_get_current_cpu()); |
939 | 943 | invalidate_TLB(pages[i]); |
940 | 944 | } |
941 | 945 | } |
diff --git a/src/system/kernel/arch/x86/arch_debug.cpp b/src/system/kernel/arch/x86/arch_debug.cpp
index ea84e5c..2ee0117 100644
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b
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arch_debug_gdb_get_registers(char* buffer, size_t bufferSize)
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1348 | 1348 | } |
1349 | 1349 | |
1350 | 1350 | |
| 1351 | static int |
| 1352 | command_invalid_tlb(int argc, char** argv) |
| 1353 | { |
| 1354 | arch_cpu_global_TLB_invalidate(); |
| 1355 | return 0; |
| 1356 | } |
| 1357 | |
| 1358 | |
1351 | 1359 | status_t |
1352 | 1360 | arch_debug_init(kernel_args* args) |
1353 | 1361 | { |
… |
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arch_debug_init(kernel_args* args)
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1367 | 1375 | "<thread ID> <command> ...\n" |
1368 | 1376 | "Executes a command in the context of a given thread.\n", |
1369 | 1377 | B_KDEBUG_DONT_PARSE_ARGUMENTS); |
| 1378 | add_debugger_command("tlb", &command_invalid_tlb, "Invalidate the TLB"); |
1370 | 1379 | |
1371 | 1380 | return B_NO_ERROR; |
1372 | 1381 | } |
diff --git a/src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp b/src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp
index e4ee9bc..c77c1b5 100644
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X86PagingMethodPAE::PhysicalPageSlotPool::Map(phys_addr_t physicalAddress,
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488 | 488 | pte = (physicalAddress & X86_PAE_PTE_ADDRESS_MASK) |
489 | 489 | | X86_PAE_PTE_WRITABLE | X86_PAE_PTE_GLOBAL | X86_PAE_PTE_PRESENT; |
490 | 490 | |
| 491 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, virtualAddress, smp_get_current_cpu()); |
491 | 492 | invalidate_TLB(virtualAddress); |
492 | 493 | } |
493 | 494 | |
… |
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X86PagingMethodPAE::InitPostArea(kernel_args* args)
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624 | 625 | // The early physical page mapping mechanism is no longer needed. Unmap the |
625 | 626 | // slot. |
626 | 627 | *fFreeVirtualSlotPTE = 0; |
| 628 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, fFreeVirtualSlot, smp_get_current_cpu()); |
627 | 629 | invalidate_TLB(fFreeVirtualSlot); |
628 | 630 | |
629 | 631 | fFreeVirtualSlotPTE = NULL; |
… |
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X86PagingMethodPAE::_EarlyGetPageTable(phys_addr_t address)
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914 | 916 | *fFreeVirtualSlotPTE = (address & X86_PAE_PTE_ADDRESS_MASK) |
915 | 917 | | X86_PAE_PTE_PRESENT | X86_PAE_PTE_WRITABLE | X86_PAE_PTE_GLOBAL; |
916 | 918 | |
| 919 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, fFreeVirtualSlot, smp_get_current_cpu()); |
917 | 920 | invalidate_TLB(fFreeVirtualSlot); |
918 | 921 | |
919 | 922 | return (pae_page_table_entry*)fFreeVirtualSlot; |
diff --git a/src/system/kernel/arch/x86/paging/x86_physical_page_mapper_large_memory.cpp b/src/system/kernel/arch/x86/paging/x86_physical_page_mapper_large_memory.cpp
index b317f92..a17fbb2 100644
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LargeMemoryTranslationMapPhysicalPageMapper::GetPageTableAt(
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396 | 396 | fNextSlot = (i + 1) & (fSlotCount - 1); |
397 | 397 | if ((slot.valid & (1 << currentCPU)) == 0) { |
398 | 398 | // not valid on this CPU -- invalidate the TLB entry |
| 399 | ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, slot.slot->address, smp_get_current_cpu()); |
399 | 400 | invalidate_TLB(slot.slot->address); |
400 | 401 | slot.valid |= 1 << currentCPU; |
401 | 402 | } |