Ticket #10249: tlb-debugging.diff

File tlb-debugging.diff, 4.3 KB (added by bonefish, 7 years ago)

Patch adding additional TLB invalidation tracing

  • src/system/kernel/arch/x86/arch_cpu.cpp

    diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp
    index a817ec0..a6b33c4 100644
    a b arch_cpu_init_post_modules(kernel_args* args)  
    898898void
    899899arch_cpu_user_TLB_invalidate(void)
    900900{
     901ktrace_printf("TLB invalidate all (non-global) on CPU %" B_PRId32, smp_get_current_cpu());
    901902    x86_write_cr3(x86_read_cr3());
    902903}
    903904
    arch_cpu_global_TLB_invalidate(void)  
    910911    if (flags & IA32_CR4_GLOBAL_PAGES) {
    911912        // disable and reenable the global pages to flush all TLBs regardless
    912913        // of the global page bit
     914ktrace_printf("TLB invalidate all on CPU %" B_PRId32, smp_get_current_cpu());
    913915        x86_write_cr4(flags & ~IA32_CR4_GLOBAL_PAGES);
    914916        x86_write_cr4(flags | IA32_CR4_GLOBAL_PAGES);
    915917    } else {
    arch_cpu_invalidate_TLB_range(addr_t start, addr_t end)  
    925927{
    926928    int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE;
    927929    while (num_pages-- >= 0) {
     930ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, start, smp_get_current_cpu());
    928931        invalidate_TLB(start);
    929932        start += B_PAGE_SIZE;
    930933    }
    arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)  
    936939{
    937940    int i;
    938941    for (i = 0; i < num_pages; i++) {
     942ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, pages[i], smp_get_current_cpu());
    939943        invalidate_TLB(pages[i]);
    940944    }
    941945}
  • src/system/kernel/arch/x86/arch_debug.cpp

    diff --git a/src/system/kernel/arch/x86/arch_debug.cpp b/src/system/kernel/arch/x86/arch_debug.cpp
    index ea84e5c..2ee0117 100644
    a b arch_debug_gdb_get_registers(char* buffer, size_t bufferSize)  
    13481348}
    13491349
    13501350
     1351static int
     1352command_invalid_tlb(int argc, char** argv)
     1353{
     1354    arch_cpu_global_TLB_invalidate();
     1355    return 0;
     1356}
     1357
     1358
    13511359status_t
    13521360arch_debug_init(kernel_args* args)
    13531361{
    arch_debug_init(kernel_args* args)  
    13671375        "<thread ID> <command> ...\n"
    13681376        "Executes a command in the context of a given thread.\n",
    13691377        B_KDEBUG_DONT_PARSE_ARGUMENTS);
     1378    add_debugger_command("tlb", &command_invalid_tlb, "Invalidate the TLB");
    13701379
    13711380    return B_NO_ERROR;
    13721381}
  • src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp

    diff --git a/src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp b/src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp
    index e4ee9bc..c77c1b5 100644
    a b X86PagingMethodPAE::PhysicalPageSlotPool::Map(phys_addr_t physicalAddress,  
    488488    pte = (physicalAddress & X86_PAE_PTE_ADDRESS_MASK)
    489489        | X86_PAE_PTE_WRITABLE | X86_PAE_PTE_GLOBAL | X86_PAE_PTE_PRESENT;
    490490
     491ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, virtualAddress, smp_get_current_cpu());
    491492    invalidate_TLB(virtualAddress);
    492493}
    493494
    X86PagingMethodPAE::InitPostArea(kernel_args* args)  
    624625    // The early physical page mapping mechanism is no longer needed. Unmap the
    625626    // slot.
    626627    *fFreeVirtualSlotPTE = 0;
     628ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, fFreeVirtualSlot, smp_get_current_cpu());
    627629    invalidate_TLB(fFreeVirtualSlot);
    628630
    629631    fFreeVirtualSlotPTE = NULL;
    X86PagingMethodPAE::_EarlyGetPageTable(phys_addr_t address)  
    914916    *fFreeVirtualSlotPTE = (address & X86_PAE_PTE_ADDRESS_MASK)
    915917        | X86_PAE_PTE_PRESENT | X86_PAE_PTE_WRITABLE | X86_PAE_PTE_GLOBAL;
    916918
     919ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, fFreeVirtualSlot, smp_get_current_cpu());
    917920    invalidate_TLB(fFreeVirtualSlot);
    918921
    919922    return (pae_page_table_entry*)fFreeVirtualSlot;
  • src/system/kernel/arch/x86/paging/x86_physical_page_mapper_large_memory.cpp

    diff --git a/src/system/kernel/arch/x86/paging/x86_physical_page_mapper_large_memory.cpp b/src/system/kernel/arch/x86/paging/x86_physical_page_mapper_large_memory.cpp
    index b317f92..a17fbb2 100644
    a b LargeMemoryTranslationMapPhysicalPageMapper::GetPageTableAt(  
    396396            fNextSlot = (i + 1) & (fSlotCount - 1);
    397397            if ((slot.valid & (1 << currentCPU)) == 0) {
    398398                // not valid on this CPU -- invalidate the TLB entry
     399ktrace_printf("TLB invalidate %#" B_PRIxADDR " on CPU %" B_PRId32, slot.slot->address, smp_get_current_cpu());
    399400                invalidate_TLB(slot.slot->address);
    400401                slot.valid |= 1 << currentCPU;
    401402            }