Ticket #10729: iwn.2.patch
File iwn.2.patch, 96.6 KB (added by , 10 years ago) |
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src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c
diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c index 8cd5a48..d3f234e 100644
a b 1 1 /*- 2 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 3 * Copyright (c) 2011 Intel Corporation 2 4 * Copyright (c) 2007-2009 3 5 * Damien Bergamini <damien.bergamini@free.fr> 4 6 * Copyright (c) 2008 … … 26 28 #include <sys/cdefs.h> 27 29 __FBSDID("$FreeBSD$"); 28 30 31 #include "opt_wlan.h" 32 #include "opt_iwn.h" 33 29 34 #include <sys/param.h> 30 35 #include <sys/sockio.h> 31 36 #include <sys/sysctl.h> … … __FBSDID("$FreeBSD$"); 71 76 72 77 #include <dev/iwn/if_iwnreg.h> 73 78 #include <dev/iwn/if_iwnvar.h> 79 #include <dev/iwn/if_iwn_devid.h> 74 80 75 81 struct iwn_ident { 76 82 uint16_t vendor; … … struct iwn_ident { 79 85 }; 80 86 81 87 static const struct iwn_ident iwn_ident_table[] = { 82 { 0x8086, 0x0082, "Intel Centrino Advanced-N 6205" }, 83 { 0x8086, 0x0083, "Intel Centrino Wireless-N 1000" }, 84 { 0x8086, 0x0084, "Intel Centrino Wireless-N 1000" }, 85 { 0x8086, 0x0085, "Intel Centrino Advanced-N 6205" }, 86 { 0x8086, 0x0087, "Intel Centrino Advanced-N + WiMAX 6250" }, 87 { 0x8086, 0x0089, "Intel Centrino Advanced-N + WiMAX 6250" }, 88 { 0x8086, 0x008a, "Intel Centrino Wireless-N 1030" }, 89 { 0x8086, 0x008b, "Intel Centrino Wireless-N 1030" }, 90 { 0x8086, 0x0090, "Intel Centrino Advanced-N 6230" }, 91 { 0x8086, 0x0091, "Intel Centrino Advanced-N 6230" }, 92 #ifdef __HAIKU__ 93 { 0x8086, 0x088e, "Intel Centrino Advanced-N 6235" }, 94 #endif 95 { 0x8086, 0x0885, "Intel Centrino Wireless-N + WiMAX 6150" }, 96 { 0x8086, 0x0886, "Intel Centrino Wireless-N + WiMAX 6150" }, 97 { 0x8086, 0x0896, "Intel Centrino Wireless-N 130" }, 98 { 0x8086, 0x0887, "Intel Centrino Wireless-N 130" }, 99 { 0x8086, 0x08ae, "Intel Centrino Wireless-N 100" }, 100 { 0x8086, 0x08af, "Intel Centrino Wireless-N 100" }, 101 { 0x8086, 0x4229, "Intel Wireless WiFi Link 4965" }, 102 { 0x8086, 0x422b, "Intel Centrino Ultimate-N 6300" }, 103 { 0x8086, 0x422c, "Intel Centrino Advanced-N 6200" }, 104 { 0x8086, 0x422d, "Intel Wireless WiFi Link 4965" }, 105 { 0x8086, 0x4230, "Intel Wireless WiFi Link 4965" }, 106 { 0x8086, 0x4232, "Intel WiFi Link 5100" }, 107 { 0x8086, 0x4233, "Intel Wireless WiFi Link 4965" }, 108 { 0x8086, 0x4235, "Intel Ultimate N WiFi Link 5300" }, 109 { 0x8086, 0x4236, "Intel Ultimate N WiFi Link 5300" }, 110 { 0x8086, 0x4237, "Intel WiFi Link 5100" }, 111 { 0x8086, 0x4238, "Intel Centrino Ultimate-N 6300" }, 112 { 0x8086, 0x4239, "Intel Centrino Advanced-N 6200" }, 113 { 0x8086, 0x423a, "Intel WiMAX/WiFi Link 5350" }, 114 { 0x8086, 0x423b, "Intel WiMAX/WiFi Link 5350" }, 115 { 0x8086, 0x423c, "Intel WiMAX/WiFi Link 5150" }, 116 { 0x8086, 0x423d, "Intel WiMAX/WiFi Link 5150" }, 88 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 89 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 90 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 91 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 92 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 93 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 94 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 95 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 96 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 97 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 98 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 99 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 100 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 101 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 102 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 103 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 104 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 105 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 106 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 107 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 108 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 109 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 110 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 111 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 112 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 113 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 114 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 115 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 116 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 117 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 118 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 119 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 120 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 121 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 117 122 { 0, 0, NULL } 118 123 }; 119 124 … … static void iwn5000_ict_reset(struct iwn_softc *); 159 164 static int iwn_read_eeprom(struct iwn_softc *, 160 165 uint8_t macaddr[IEEE80211_ADDR_LEN]); 161 166 static void iwn4965_read_eeprom(struct iwn_softc *); 167 #ifdef IWN_DEBUG 162 168 static void iwn4965_print_power_group(struct iwn_softc *, int); 169 #endif 163 170 static void iwn5000_read_eeprom(struct iwn_softc *); 164 171 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 165 172 static void iwn_read_eeprom_band(struct iwn_softc *, int); … … static void iwn_set_channel(struct ieee80211com *); 319 326 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 320 327 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 321 328 static void iwn_hw_reset(void *, int); 329 #ifdef IWN_DEBUG 330 static char *iwn_get_csr_string(int); 331 static void iwn_debug_register(struct iwn_softc *); 332 #endif 322 333 323 #define IWN_DEBUG 324 #ifdef IWN_DEBUG 334 #ifdef IWN_DEBUG 325 335 enum { 326 336 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 327 337 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ … … enum { 336 346 IWN_DEBUG_NODE = 0x00000400, /* node management */ 337 347 IWN_DEBUG_LED = 0x00000800, /* led management */ 338 348 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 349 IWN_DEBUG_TXRATE = 0x00002000, /* TX rate debugging */ 350 IWN_DEBUG_PWRSAVE = 0x00004000, /* Power save operations */ 351 IWN_DEBUG_REGISTER = 0x20000000, /* print chipset register */ 352 IWN_DEBUG_TRACE = 0x40000000, /* Print begin and start driver function */ 339 353 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 340 354 IWN_DEBUG_ANY = 0xffffffff 341 355 }; … … static device_method_t iwn_methods[] = { 399 413 DEVMETHOD(device_shutdown, iwn_shutdown), 400 414 DEVMETHOD(device_suspend, iwn_suspend), 401 415 DEVMETHOD(device_resume, iwn_resume), 402 403 DEVMETHOD_END 416 { 0, 0 } 404 417 }; 405 418 406 419 static driver_t iwn_driver = { … … static driver_t iwn_driver = { 410 423 }; 411 424 static devclass_t iwn_devclass; 412 425 413 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL);426 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 414 427 415 428 MODULE_VERSION(iwn, 1); 416 429 … … iwn_probe(device_t dev) 427 440 if (pci_get_vendor(dev) == ident->vendor && 428 441 pci_get_device(dev) == ident->device) { 429 442 device_set_desc(dev, ident->name); 430 return (BUS_PROBE_DEFAULT);443 return 0; 431 444 } 432 445 } 433 446 return ENXIO; … … iwn_attach(device_t dev) 439 452 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 440 453 struct ieee80211com *ic; 441 454 struct ifnet *ifp; 442 int i, error, rid; 455 uint32_t reg; 456 int i, error, result; 443 457 uint8_t macaddr[IEEE80211_ADDR_LEN]; 444 458 445 459 sc->sc_dev = dev; 446 460 461 #ifdef IWN_DEBUG 462 error = resource_int_value(device_get_name(sc->sc_dev), 463 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 464 if (error != 0) 465 sc->sc_debug = 0; 466 #else 467 sc->sc_debug = 0; 468 #endif 469 470 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 471 447 472 /* 448 473 * Get the offset of the PCI Express Capability Structure in PCI 449 474 * Configuration Space. … … iwn_attach(device_t dev) 457 482 /* Clear device-specific "PCI retry timeout" register (41h). */ 458 483 pci_write_config(dev, 0x41, 0, 1); 459 484 485 /* Hardware bug workaround. */ 486 reg = pci_read_config(dev, PCIR_COMMAND, 2); 487 if (reg & PCIM_CMD_INTxDIS) { 488 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 489 __func__); 490 reg &= ~PCIM_CMD_INTxDIS; 491 pci_write_config(dev, PCIR_COMMAND, reg, 2); 492 } 493 460 494 /* Enable bus-mastering. */ 461 495 pci_enable_busmaster(dev); 462 496 463 rid = PCIR_BAR(0);464 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, & rid,497 sc->mem_rid = PCIR_BAR(0); 498 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 465 499 RF_ACTIVE); 466 500 if (sc->mem == NULL) { 467 501 device_printf(dev, "can't map mem space\n"); … … iwn_attach(device_t dev) 471 505 sc->sc_st = rman_get_bustag(sc->mem); 472 506 sc->sc_sh = rman_get_bushandle(sc->mem); 473 507 474 i = 1;475 rid = 0;476 if (pci_alloc_msi(dev, &i) == 0)477 rid = 1;508 sc->irq_rid = 0; 509 if ((result = pci_msi_count(dev)) == 1 && 510 pci_alloc_msi(dev, &result) == 0) 511 sc->irq_rid = 1; 478 512 /* Install interrupt handler. */ 479 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, & rid, RF_ACTIVE |480 (rid != 0 ? 0 : RF_SHAREABLE));513 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 514 RF_ACTIVE | RF_SHAREABLE); 481 515 if (sc->irq == NULL) { 482 516 device_printf(dev, "can't map interrupt\n"); 483 517 error = ENOMEM; … … iwn_attach(device_t dev) 487 521 IWN_LOCK_INIT(sc); 488 522 489 523 /* Read hardware revision and attach. */ 490 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 524 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 525 & IWN_HW_REV_TYPE_MASK; 526 sc->subdevice_id = pci_get_subdevice(dev); 491 527 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 492 528 error = iwn4965_attach(sc, pci_get_device(dev)); 493 529 else … … iwn_attach(device_t dev) 577 613 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 578 614 #endif 579 615 | IEEE80211_C_WME /* WME */ 616 | IEEE80211_C_PMGT /* Station-side power mgmt */ 580 617 ; 581 618 582 619 /* Read MAC address, channels, etc from EEPROM. */ … … iwn_attach(device_t dev) 604 641 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 605 642 ic->ic_rxstream = sc->nrxchains; 606 643 ic->ic_txstream = sc->ntxchains; 644 645 /* 646 * The NICs we currently support cap out at 2x2 support 647 * separate from the chains being used. 648 * 649 * This is a total hack to work around that until some 650 * per-device method is implemented to return the 651 * actual stream support. 652 */ 653 if (ic->ic_rxstream > 2) 654 ic->ic_rxstream = 2; 655 if (ic->ic_txstream > 2) 656 ic->ic_txstream = 2; 657 607 658 ic->ic_htcaps = 608 659 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 609 660 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ … … iwn_attach(device_t dev) 684 735 685 736 if (bootverbose) 686 737 ieee80211_announce(ic); 738 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 687 739 return 0; 688 740 fail: 689 741 iwn_detach(dev); 742 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 690 743 return error; 691 744 } 692 745 … … iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 695 748 { 696 749 struct iwn_ops *ops = &sc->ops; 697 750 751 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 698 752 ops->load_firmware = iwn4965_load_firmware; 699 753 ops->read_eeprom = iwn4965_read_eeprom; 700 754 ops->post_alive = iwn4965_post_alive; … … iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 725 779 sc->txchainmask = IWN_ANT_AB; 726 780 sc->rxchainmask = IWN_ANT_ABC; 727 781 782 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 783 728 784 return 0; 729 785 } 730 786 … … iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 733 789 { 734 790 struct iwn_ops *ops = &sc->ops; 735 791 792 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 793 736 794 ops->load_firmware = iwn5000_load_firmware; 737 795 ops->read_eeprom = iwn5000_read_eeprom; 738 796 ops->post_alive = iwn5000_post_alive; … … iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 809 867 default: 810 868 device_printf(sc->sc_dev, "adapter type %d not supported\n", 811 869 sc->hw_type); 870 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 812 871 return ENOTSUP; 813 872 } 814 873 return 0; … … iwn_radiotap_attach(struct iwn_softc *sc) 822 881 { 823 882 struct ifnet *ifp = sc->sc_ifp; 824 883 struct ieee80211com *ic = ifp->if_l2com; 825 884 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 826 885 ieee80211_radiotap_attach(ic, 827 886 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 828 887 IWN_TX_RADIOTAP_PRESENT, 829 888 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 830 889 IWN_RX_RADIOTAP_PRESENT); 890 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 831 891 } 832 892 833 893 static void 834 894 iwn_sysctlattach(struct iwn_softc *sc) 835 895 { 896 #ifdef IWN_DEBUG 836 897 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 837 898 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 838 899 839 #ifdef IWN_DEBUG840 sc->sc_debug = 0;841 900 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 842 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 901 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 902 "control debugging printfs"); 843 903 #endif 844 904 } 845 905 … … iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 851 911 { 852 912 struct iwn_vap *ivp; 853 913 struct ieee80211vap *vap; 914 uint8_t mac1[IEEE80211_ADDR_LEN]; 915 struct iwn_softc *sc = ic->ic_ifp->if_softc; 854 916 855 917 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 856 918 return NULL; 919 920 IEEE80211_ADDR_COPY(mac1, mac); 921 857 922 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 858 923 M_80211_VAP, M_NOWAIT | M_ZERO); 859 924 if (ivp == NULL) 860 925 return NULL; 861 926 vap = &ivp->iv_vap; 862 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 927 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac1); 928 ivp->ctx = IWN_RXON_BSS_CTX; 929 IEEE80211_ADDR_COPY(ivp->macaddr, mac1); 863 930 vap->iv_bmissthreshold = 10; /* override default */ 864 931 /* Override with driver methods. */ 865 932 ivp->iv_newstate = vap->iv_newstate; 866 933 vap->iv_newstate = iwn_newstate; 934 sc->ivap[IWN_RXON_BSS_CTX] = vap; 867 935 868 936 ieee80211_ratectl_init(vap); 869 937 /* Complete setup. */ … … iwn_detach(device_t dev) 890 958 struct ieee80211com *ic; 891 959 int qid; 892 960 961 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 962 893 963 if (ifp != NULL) { 894 964 ic = ifp->if_l2com; 895 965 … … iwn_detach(device_t dev) 906 976 /* Uninstall interrupt handler. */ 907 977 if (sc->irq != NULL) { 908 978 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 909 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq),910 sc->irq);911 pci_release_msi(dev);979 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 980 if (sc->irq_rid == 1) 981 pci_release_msi(dev); 912 982 } 913 983 914 984 /* Free DMA resources. */ … … iwn_detach(device_t dev) 922 992 iwn_free_fwmem(sc); 923 993 924 994 if (sc->mem != NULL) 925 bus_release_resource(dev, SYS_RES_MEMORY, 926 rman_get_rid(sc->mem), sc->mem); 995 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 927 996 928 997 if (ifp != NULL) 929 998 if_free(ifp); 930 999 1000 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 931 1001 IWN_LOCK_DESTROY(sc); 932 1002 return 0; 933 1003 } … … iwn_eeprom_lock(struct iwn_softc *sc) 1088 1158 DELAY(10); 1089 1159 } 1090 1160 } 1161 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1091 1162 return ETIMEDOUT; 1092 1163 } 1093 1164 … … iwn_init_otprom(struct iwn_softc *sc) 1107 1178 uint16_t prev, base, next; 1108 1179 int count, error; 1109 1180 1181 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1182 1110 1183 /* Wait for clock stabilization before accessing prph. */ 1111 1184 if ((error = iwn_clock_wait(sc)) != 0) 1112 1185 return error; … … iwn_init_otprom(struct iwn_softc *sc) 1150 1223 /* Skip "next" word. */ 1151 1224 sc->prom_base = prev + 1; 1152 1225 } 1226 1227 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1228 1153 1229 return 0; 1154 1230 } 1155 1231 … … iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1160 1236 uint32_t val, tmp; 1161 1237 int ntries; 1162 1238 1239 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1240 1163 1241 addr += sc->prom_base; 1164 1242 for (; count > 0; count -= 2, addr++) { 1165 1243 IWN_WRITE(sc, IWN_EEPROM, addr << 2); … … iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1192 1270 if (count > 1) 1193 1271 *out++ = val >> 24; 1194 1272 } 1273 1274 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1275 1195 1276 return 0; 1196 1277 } 1197 1278 … … iwn_dma_contig_free(struct iwn_dma_info *dma) 1248 1329 bus_dmamap_sync(dma->tag, dma->map, 1249 1330 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1250 1331 bus_dmamap_unload(dma->tag, dma->map); 1251 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map);1332 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1252 1333 dma->vaddr = NULL; 1253 1334 } 1254 1335 bus_dmamap_destroy(dma->tag, dma->map); … … iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1322 1403 1323 1404 ring->cur = 0; 1324 1405 1406 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1407 1325 1408 /* Allocate RX descriptors (256-byte aligned). */ 1326 1409 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1327 1410 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, … … iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1396 1479 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1397 1480 BUS_DMASYNC_PREWRITE); 1398 1481 1482 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1483 1399 1484 return 0; 1400 1485 1401 1486 fail: iwn_free_rx_ring(sc, ring); 1487 1488 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1489 1402 1490 return error; 1403 1491 } 1404 1492 … … iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1407 1495 { 1408 1496 int ntries; 1409 1497 1498 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1499 1410 1500 if (iwn_nic_lock(sc) == 0) { 1411 1501 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1412 1502 for (ntries = 0; ntries < 1000; ntries++) { … … iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1426 1516 { 1427 1517 int i; 1428 1518 1519 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1520 1429 1521 iwn_dma_contig_free(&ring->desc_dma); 1430 1522 iwn_dma_contig_free(&ring->stat_dma); 1431 1523 … … iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1459 1551 ring->queued = 0; 1460 1552 ring->cur = 0; 1461 1553 1554 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1555 1462 1556 /* Allocate TX descriptors (256-byte aligned). */ 1463 1557 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1464 1558 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, … … iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1507 1601 goto fail; 1508 1602 } 1509 1603 } 1604 1605 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1606 1510 1607 return 0; 1511 1608 1512 1609 fail: iwn_free_tx_ring(sc, ring); 1610 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 1513 1611 return error; 1514 1612 } 1515 1613 … … iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1518 1616 { 1519 1617 int i; 1520 1618 1619 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 1620 1521 1621 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1522 1622 struct iwn_tx_data *data = &ring->data[i]; 1523 1623 … … iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1543 1643 { 1544 1644 int i; 1545 1645 1646 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1647 1546 1648 iwn_dma_contig_free(&ring->desc_dma); 1547 1649 iwn_dma_contig_free(&ring->cmd_dma); 1548 1650 … … iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1596 1698 uint16_t val; 1597 1699 int error; 1598 1700 1701 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1702 1599 1703 /* Check whether adapter has an EEPROM or an OTPROM. */ 1600 1704 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1601 1705 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) … … iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1653 1757 iwn_apm_stop(sc); /* Power OFF adapter. */ 1654 1758 1655 1759 iwn_eeprom_unlock(sc); 1760 1761 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1762 1656 1763 return 0; 1657 1764 } 1658 1765 … … iwn4965_read_eeprom(struct iwn_softc *sc) 1663 1770 uint16_t val; 1664 1771 int i; 1665 1772 1773 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1774 1666 1775 /* Read regulatory domain (4 ASCII characters). */ 1667 1776 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1668 1777 … … iwn4965_read_eeprom(struct iwn_softc *sc) 1701 1810 iwn4965_print_power_group(sc, i); 1702 1811 } 1703 1812 #endif 1813 1814 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1704 1815 } 1705 1816 1706 1817 #ifdef IWN_DEBUG … … iwn5000_read_eeprom(struct iwn_softc *sc) 1747 1858 uint16_t val; 1748 1859 int i; 1749 1860 1861 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1862 1750 1863 /* Read regulatory domain (4 ASCII characters). */ 1751 1864 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1752 1865 base = le16toh(val); … … iwn5000_read_eeprom(struct iwn_softc *sc) 1790 1903 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1791 1904 le32toh(sc->eeprom_crystal)); 1792 1905 } 1906 1907 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1908 1793 1909 } 1794 1910 1795 1911 /* … … iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1825 1941 uint8_t chan; 1826 1942 int i, nflags; 1827 1943 1944 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1945 1828 1946 for (i = 0; i < band->nchan; i++) { 1829 1947 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1830 1948 DPRINTF(sc, IWN_DEBUG_RESET, … … iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1867 1985 c->ic_flags |= IEEE80211_CHAN_HT20; 1868 1986 } 1869 1987 } 1988 1989 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1990 1870 1991 } 1871 1992 1872 1993 static void … … iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1880 2001 uint8_t chan; 1881 2002 int i, nflags; 1882 2003 1883 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) 2004 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2005 2006 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2007 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 1884 2008 return; 2009 } 1885 2010 1886 2011 for (i = 0; i < band->nchan; i++) { 1887 2012 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { … … iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1929 2054 c->ic_flags &= ~IEEE80211_CHAN_HT; 1930 2055 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 1931 2056 } 2057 2058 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2059 1932 2060 } 1933 2061 1934 2062 static void … … iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2012 2140 uint8_t flags; 2013 2141 int i, j; 2014 2142 2143 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2144 2015 2145 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2016 2146 base = le16toh(val); 2017 2147 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, … … iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2062 2192 c->ic_maxpower = maxpwr; 2063 2193 } 2064 2194 } 2195 2196 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2197 2065 2198 } 2066 2199 2067 2200 static struct ieee80211_node * … … rate2plcp(int rate) 2090 2223 return 0; 2091 2224 } 2092 2225 2093 static void 2094 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2226 /* 2227 * Calculate the required PLCP value from the given rate, 2228 * to the given node. 2229 * 2230 * This will take the node configuration (eg 11n, rate table 2231 * setup, etc) into consideration. 2232 */ 2233 static uint32_t 2234 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2235 uint8_t rate) 2095 2236 { 2096 2237 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2097 2238 struct ieee80211com *ic = ni->ni_ic; 2098 struct iwn_softc *sc = ic->ic_ifp->if_softc;2099 struct iwn_node *wn = (void *)ni;2100 2239 uint8_t txant1, txant2; 2101 int i, plcp, rate, ridx; 2240 uint32_t plcp = 0; 2241 int ridx; 2102 2242 2103 2243 /* Use the first valid TX antenna. */ 2104 2244 txant1 = IWN_LSB(sc->txchainmask); 2105 2245 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2106 2246 2247 /* 2248 * If it's an MCS rate, let's set the plcp correctly 2249 * and set the relevant flags based on the node config. 2250 */ 2107 2251 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 2108 ridx = ni->ni_rates.rs_nrates - 1; 2109 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) { 2110 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS; 2111 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2112 plcp |= IWN_RFLAG_HT40; 2113 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2114 plcp |= IWN_RFLAG_SGI; 2115 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) 2252 /* 2253 * Set the initial PLCP value to be between 0->31 for 2254 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2255 * flag. 2256 */ 2257 plcp = RV(rate) | IWN_RFLAG_MCS; 2258 2259 /* 2260 * XXX the following should only occur if both 2261 * the local configuration _and_ the remote node 2262 * advertise these capabilities. Thus this code 2263 * may need fixing! 2264 */ 2265 2266 /* 2267 * Set the channel width and guard interval. 2268 */ 2269 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2270 plcp |= IWN_RFLAG_HT40; 2271 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2116 2272 plcp |= IWN_RFLAG_SGI; 2117 if (RV(ni->ni_htrates.rs_rates[i]) > 7) 2118 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2119 else 2120 plcp |= IWN_RFLAG_ANT(txant1); 2121 if (ridx >= 0) { 2122 rate = RV(ni->ni_rates.rs_rates[ridx]); 2123 wn->ridx[rate] = plcp; 2124 } 2125 wn->ridx[IEEE80211_RATE_MCS | i] = plcp; 2126 ridx--; 2273 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2274 plcp |= IWN_RFLAG_SGI; 2127 2275 } 2128 } else { 2129 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2130 rate = RV(ni->ni_rates.rs_rates[i]); 2131 plcp = rate2plcp(rate); 2132 ridx = ic->ic_rt->rateCodeToIndex[rate]; 2133 if (ridx < IWN_RIDX_OFDM6 && 2134 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2135 plcp |= IWN_RFLAG_CCK; 2276 2277 /* 2278 * If it's a two stream rate, enable TX on both 2279 * antennas. 2280 * 2281 * XXX three stream rates? 2282 */ 2283 if (rate > 0x87) 2284 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2285 else 2136 2286 plcp |= IWN_RFLAG_ANT(txant1); 2137 wn->ridx[rate] = htole32(plcp); 2138 } 2287 } else { 2288 /* 2289 * Set the initial PLCP - fine for both 2290 * OFDM and CCK rates. 2291 */ 2292 plcp = rate2plcp(rate); 2293 2294 /* Set CCK flag if it's CCK */ 2295 2296 /* XXX It would be nice to have a method 2297 * to map the ridx -> phy table entry 2298 * so we could just query that, rather than 2299 * this hack to check against IWN_RIDX_OFDM6. 2300 */ 2301 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2302 rate & IEEE80211_RATE_VAL); 2303 if (ridx < IWN_RIDX_OFDM6 && 2304 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2305 plcp |= IWN_RFLAG_CCK; 2306 2307 /* Set antenna configuration */ 2308 plcp |= IWN_RFLAG_ANT(txant1); 2139 2309 } 2310 2311 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2312 __func__, 2313 rate, 2314 plcp); 2315 2316 return (htole32(plcp)); 2140 2317 #undef RV 2141 2318 } 2142 2319 2320 static void 2321 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2322 { 2323 /* Doesn't do anything at the moment */ 2324 } 2325 2143 2326 static int 2144 2327 iwn_media_change(struct ifnet *ifp) 2145 2328 { … … iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2158 2341 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2159 2342 int error = 0; 2160 2343 2344 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2345 2161 2346 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2162 2347 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2163 2348 … … iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2165 2350 IWN_LOCK(sc); 2166 2351 callout_stop(&sc->calib_to); 2167 2352 2353 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2354 2168 2355 switch (nstate) { 2169 2356 case IEEE80211_S_ASSOC: 2170 2357 if (vap->iv_state != IEEE80211_S_RUN) … … iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2178 2365 * !AUTH -> AUTH transition requires state reset to handle 2179 2366 * reassociations correctly. 2180 2367 */ 2181 sc->rxon .associd = 0;2182 sc->rxon .filter &= ~htole32(IWN_FILTER_BSS);2368 sc->rxon->associd = 0; 2369 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2183 2370 sc->calib.state = IWN_CALIB_STATE_INIT; 2184 2371 2185 2372 if ((error = iwn_auth(sc, vap)) != 0) { … … iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2217 2404 } 2218 2405 IWN_UNLOCK(sc); 2219 2406 IEEE80211_LOCK(ic); 2220 if (error != 0) 2407 if (error != 0){ 2408 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2221 2409 return error; 2410 } 2411 2412 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2413 2222 2414 return ivp->iv_newstate(vap, nstate, arg); 2223 2415 } 2224 2416 … … iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2282 2474 uint32_t flags; 2283 2475 int error, len, rssi, nf; 2284 2476 2477 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2478 2285 2479 if (desc->type == IWN_MPDU_RX_DONE) { 2286 2480 /* Check for prior RX_PHY notification. */ 2287 2481 if (!sc->last_rx_valid) { … … iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2420 2614 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2421 2615 2422 2616 IWN_LOCK(sc); 2617 2618 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2619 2423 2620 } 2424 2621 2425 2622 /* Process an incoming Compressed BlockAck. */ … … iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2441 2638 uint8_t tid; 2442 2639 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 2443 2640 2641 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2642 2444 2643 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2445 2644 2446 2645 qid = le16toh(ba->qid); 2447 2646 txq = &sc->txq[ba->qid]; 2448 2647 tap = sc->qid2tap[ba->qid]; 2449 tid = WME_AC_TO_TID(tap->txa_ac);2648 tid = tap->txa_ac; // FreeBSD 10.0.0: tap->txa_tid; 2450 2649 wn = (void *)tap->txa_ni; 2451 2650 2452 2651 res = NULL; … … iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2469 2668 KASSERT(ni != NULL, ("no node")); 2470 2669 KASSERT(m != NULL, ("no mbuf")); 2471 2670 2472 if (m->m_flags & M_TXCB) 2473 ieee80211_process_callback(ni, m, 1); 2474 2475 m_freem(m); 2476 ieee80211_free_node(ni); 2671 ieee80211_tx_complete(ni, m, 1); 2477 2672 2478 2673 txq->queued--; 2479 2674 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; … … iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2512 2707 } 2513 2708 bitmap >>= 1; 2514 2709 } 2710 2711 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2712 2515 2713 } 2516 2714 2517 2715 /* … … iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2525 2723 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2526 2724 int len, idx = -1; 2527 2725 2726 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2727 2528 2728 /* Runtime firmware should not send such a notification. */ 2529 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2729 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 2730 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 2731 __func__); 2530 2732 return; 2531 2733 } 2532 2734 len = (le32toh(desc->len) & 0x3fff) - 4; 2533 2735 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2534 2736 … … iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2590 2792 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2591 2793 int temp; 2592 2794 2795 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2796 2593 2797 /* Ignore statistics received during a scan. */ 2594 2798 if (vap->iv_state != IEEE80211_S_RUN || 2595 (ic->ic_flags & IEEE80211_F_SCAN)) 2799 (ic->ic_flags & IEEE80211_F_SCAN)){ 2800 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 2801 __func__); 2596 2802 return; 2803 } 2597 2804 2598 2805 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2599 2806 … … iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2631 2838 iwn_collect_noise(sc, &stats->rx.general); 2632 2839 else if (calib->state == IWN_CALIB_STATE_RUN) 2633 2840 iwn_tune_sensitivity(sc, &stats->rx); 2841 2842 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2634 2843 } 2635 2844 2636 2845 /* … … iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2712 2921 2713 2922 KASSERT(data->ni != NULL, ("no node")); 2714 2923 2924 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2925 2715 2926 /* Unmap and free mbuf. */ 2716 2927 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2717 2928 bus_dmamap_unload(ring->data_dmat, data->map); … … iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2719 2930 ni = data->ni, data->ni = NULL; 2720 2931 vap = ni->ni_vap; 2721 2932 2722 if (m->m_flags & M_TXCB) {2723 /*2724 * Channels marked for "radar" require traffic to be received2725 * to unlock before we can transmit. Until traffic is seen2726 * any attempt to transmit is returned immediately with status2727 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily2728 * happen on first authenticate after scanning. To workaround2729 * this we ignore a failure of this sort in AUTH state so the2730 * 802.11 layer will fall back to using a timeout to wait for2731 * the AUTH reply. This allows the firmware time to see2732 * traffic so a subsequent retry of AUTH succeeds. It's2733 * unclear why the firmware does not maintain state for2734 * channels recently visited as this would allow immediate2735 * use of the channel after a scan (where we see traffic).2736 */2737 if (status == IWN_TX_FAIL_TX_LOCKED &&2738 ni->ni_vap->iv_state == IEEE80211_S_AUTH)2739 ieee80211_process_callback(ni, m, 0);2740 else2741 ieee80211_process_callback(ni, m,2742 (status & IWN_TX_FAIL) != 0);2743 }2744 2745 2933 /* 2746 2934 * Update rate control statistics for the node. 2747 2935 */ … … iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2754 2942 ieee80211_ratectl_tx_complete(vap, ni, 2755 2943 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2756 2944 } 2757 m_freem(m); 2758 ieee80211_free_node(ni); 2945 2946 /* 2947 * Channels marked for "radar" require traffic to be received 2948 * to unlock before we can transmit. Until traffic is seen 2949 * any attempt to transmit is returned immediately with status 2950 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2951 * happen on first authenticate after scanning. To workaround 2952 * this we ignore a failure of this sort in AUTH state so the 2953 * 802.11 layer will fall back to using a timeout to wait for 2954 * the AUTH reply. This allows the firmware time to see 2955 * traffic so a subsequent retry of AUTH succeeds. It's 2956 * unclear why the firmware does not maintain state for 2957 * channels recently visited as this would allow immediate 2958 * use of the channel after a scan (where we see traffic). 2959 */ 2960 if (status == IWN_TX_FAIL_TX_LOCKED && 2961 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2962 ieee80211_tx_complete(ni, m, 0); 2963 else 2964 ieee80211_tx_complete(ni, m, 2965 (status & IWN_TX_FAIL) != 0); 2759 2966 2760 2967 sc->sc_tx_timer = 0; 2761 2968 if (--ring->queued < IWN_TX_RING_LOMARK) { … … iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2766 2973 iwn_start_locked(ifp); 2767 2974 } 2768 2975 } 2976 2977 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2978 2769 2979 } 2770 2980 2771 2981 /* … … iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2813 3023 uint8_t tid; 2814 3024 int bit, i, lastidx, *res, seqno, shift, start; 2815 3025 3026 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3027 2816 3028 #ifdef NOT_YET 2817 3029 if (nframes == 1) { 2818 3030 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) … … iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2844 3056 bitmap |= 1ULL << bit; 2845 3057 } 2846 3058 tap = sc->qid2tap[qid]; 2847 tid = WME_AC_TO_TID(tap->txa_ac);3059 tid = tap->txa_ac; // FreeBSD 10.0.0: tap->txa_tid; 2848 3060 wn = (void *)tap->txa_ni; 2849 3061 wn->agg[tid].bitmap = bitmap; 2850 3062 wn->agg[tid].startidx = start; … … iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2871 3083 KASSERT(ni != NULL, ("no node")); 2872 3084 KASSERT(m != NULL, ("no mbuf")); 2873 3085 2874 if (m->m_flags & M_TXCB) 2875 ieee80211_process_callback(ni, m, 1); 2876 2877 m_freem(m); 2878 ieee80211_free_node(ni); 3086 ieee80211_tx_complete(ni, m, 1); 2879 3087 2880 3088 ring->queued--; 2881 3089 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; … … iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2899 3107 iwn_start_locked(ifp); 2900 3108 } 2901 3109 } 3110 3111 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3112 2902 3113 } 2903 3114 2904 3115 /* … … iwn_notif_intr(struct iwn_softc *sc) 3017 3228 } 3018 3229 case IWN_STATE_CHANGED: 3019 3230 { 3020 uint32_t *status = (uint32_t *)(desc + 1);3021 3022 3231 /* 3023 3232 * State change allows hardware switch change to be 3024 3233 * noted. However, we handle this in iwn_intr as we … … iwn_notif_intr(struct iwn_softc *sc) 3026 3235 */ 3027 3236 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3028 3237 BUS_DMASYNC_POSTREAD); 3238 #ifdef IWN_DEBUG 3239 uint32_t *status = (uint32_t *)(desc + 1); 3029 3240 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 3030 3241 le32toh(*status)); 3242 #endif 3031 3243 break; 3032 3244 } 3033 3245 case IWN_START_SCAN: 3034 3246 { 3035 struct iwn_start_scan *scan =3036 (struct iwn_start_scan *)(desc + 1);3037 3038 3247 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3039 3248 BUS_DMASYNC_POSTREAD); 3249 #ifdef IWN_DEBUG 3250 struct iwn_start_scan *scan = 3251 (struct iwn_start_scan *)(desc + 1); 3040 3252 DPRINTF(sc, IWN_DEBUG_ANY, 3041 3253 "%s: scanning channel %d status %x\n", 3042 3254 __func__, scan->chan, le32toh(scan->status)); 3255 #endif 3043 3256 break; 3044 3257 } 3045 3258 case IWN_STOP_SCAN: 3046 3259 { 3047 struct iwn_stop_scan *scan =3048 (struct iwn_stop_scan *)(desc + 1);3049 3050 3260 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3051 3261 BUS_DMASYNC_POSTREAD); 3262 #ifdef IWN_DEBUG 3263 struct iwn_stop_scan *scan = 3264 (struct iwn_stop_scan *)(desc + 1); 3052 3265 DPRINTF(sc, IWN_DEBUG_STATE, 3053 3266 "scan finished nchan=%d status=%d chan=%d\n", 3054 3267 scan->nchan, scan->status, scan->chan); 3268 #endif 3055 3269 3056 3270 IWN_UNLOCK(sc); 3057 3271 ieee80211_scan_next(vap); … … iwn_intr(void *arg) 3184 3398 3185 3399 IWN_LOCK(sc); 3186 3400 3187 #if !defined(__HAIKU__)3188 3401 /* Disable interrupts. */ 3189 3402 IWN_WRITE(sc, IWN_INT_MASK, 0); 3190 3403 … … iwn_intr(void *arg) 3209 3422 return; /* Hardware gone! */ 3210 3423 r2 = IWN_READ(sc, IWN_FH_INT); 3211 3424 } 3212 #else3213 r1 = atomic_get((int32 *)&sc->sc_intr_status_1);3214 r2 = atomic_get((int32 *)&sc->sc_intr_status_2);3215 #endif3216 3425 3217 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 3426 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 3427 , r1, r2); 3218 3428 3219 3429 if (r1 == 0 && r2 == 0) 3220 3430 goto done; /* Interrupt not for us. */ … … iwn_intr(void *arg) 3235 3445 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3236 3446 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 3237 3447 __func__); 3448 #ifdef IWN_DEBUG 3449 iwn_debug_register(sc); 3450 #endif 3238 3451 /* Dump firmware error log and stop. */ 3239 3452 iwn_fatal_intr(sc); 3240 3453 ifp->if_flags &= ~IFF_UP; … … iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3287 3500 { 3288 3501 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3289 3502 3503 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 3504 3290 3505 *w = htole16(len + 8); 3291 3506 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3292 3507 BUS_DMASYNC_PREWRITE); … … iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3303 3518 { 3304 3519 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3305 3520 3521 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 3522 3306 3523 *w = htole16(id << 12 | (len + 8)); 3307 3524 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3308 3525 BUS_DMASYNC_PREWRITE); … … iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3319 3536 { 3320 3537 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3321 3538 3539 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 3540 3322 3541 *w = (*w & htole16(0xf000)) | htole16(1); 3323 3542 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3324 3543 BUS_DMASYNC_PREWRITE); … … iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3353 3572 uint8_t tid, ridx, txant, type; 3354 3573 int ac, i, totlen, error, pad, nsegs = 0, rate; 3355 3574 3575 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3576 3356 3577 IWN_LOCK_ASSERT(sc); 3357 3578 3358 3579 wh = mtod(m, struct ieee80211_frame *); … … iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3398 3619 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3399 3620 rate = ni->ni_txrate; 3400 3621 } 3401 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3622 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 3623 rate & IEEE80211_RATE_VAL); 3402 3624 3403 3625 /* Encrypt the frame if need be. */ 3404 3626 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { … … iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3504 3726 tx->rts_ntries = 60; 3505 3727 tx->data_ntries = 15; 3506 3728 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3507 tx->rate = wn->ridx[rate];3729 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 3508 3730 if (tx->id == sc->broadcast_id) { 3509 3731 /* Group or management frame. */ 3510 3732 tx->linkq = 0; … … iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3597 3819 if (++ring->queued > IWN_TX_RING_HIMARK) 3598 3820 sc->qfullmsk |= 1 << ring->qid; 3599 3821 3822 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3823 3600 3824 return 0; 3601 3825 } 3602 3826 … … iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3621 3845 int ac, totlen, error, pad, nsegs = 0, i, rate; 3622 3846 uint8_t ridx, type, txant; 3623 3847 3848 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3849 3624 3850 IWN_LOCK_ASSERT(sc); 3625 3851 3626 3852 wh = mtod(m, struct ieee80211_frame *); … … iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3635 3861 3636 3862 /* Choose a TX rate index. */ 3637 3863 rate = params->ibp_rate0; 3638 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3864 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 3865 rate & IEEE80211_RATE_VAL); 3639 3866 if (ridx == (uint8_t)-1) { 3640 3867 /* XXX fall back to mcast/mgmt rate? */ 3641 3868 m_freem(m); … … iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3711 3938 tx->rts_ntries = params->ibp_try1; 3712 3939 tx->data_ntries = params->ibp_try0; 3713 3940 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3941 3942 /* XXX should just use iwn_rate_to_plcp() */ 3714 3943 tx->rate = htole32(rate2plcp(rate)); 3715 3944 if (ridx < IWN_RIDX_OFDM6 && 3716 3945 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 3717 3946 tx->rate |= htole32(IWN_RFLAG_CCK); 3947 3718 3948 /* Group or management frame. */ 3719 3949 tx->linkq = 0; 3720 3950 txant = IWN_LSB(sc->txchainmask); 3721 3951 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3952 3722 3953 /* Set physical address of "scratch area". */ 3723 3954 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3724 3955 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); … … iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3801 4032 if (++ring->queued > IWN_TX_RING_HIMARK) 3802 4033 sc->qfullmsk |= 1 << ring->qid; 3803 4034 4035 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4036 3804 4037 return 0; 3805 4038 } 3806 4039 … … iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3813 4046 struct iwn_softc *sc = ifp->if_softc; 3814 4047 int error = 0; 3815 4048 4049 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4050 3816 4051 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3817 4052 ieee80211_free_node(ni); 3818 4053 m_freem(m); … … iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3841 4076 sc->sc_tx_timer = 5; 3842 4077 3843 4078 IWN_UNLOCK(sc); 4079 4080 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4081 3844 4082 return error; 3845 4083 } 3846 4084 … … iwn_watchdog(void *arg) 3896 4134 3897 4135 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3898 4136 4137 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4138 3899 4139 if (sc->sc_tx_timer > 0) { 3900 4140 if (--sc->sc_tx_timer == 0) { 3901 4141 if_printf(ifp, "device timeout\n"); … … iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3963 4203 bus_addr_t paddr; 3964 4204 int totlen, error; 3965 4205 4206 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4207 3966 4208 if (async == 0) 3967 4209 IWN_LOCK_ASSERT(sc); 3968 4210 … … iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 4018 4260 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4019 4261 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4020 4262 4263 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4264 4021 4265 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 4022 4266 } 4023 4267 … … iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4027 4271 struct iwn4965_node_info hnode; 4028 4272 caddr_t src, dst; 4029 4273 4274 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4275 4030 4276 /* 4031 4277 * We use the node structure for 5000 Series internally (it is 4032 4278 * a superset of the one for 4965AGN). We thus copy the common … … iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4043 4289 static int 4044 4290 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4045 4291 { 4292 4293 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4294 4046 4295 /* Direct mapping. */ 4047 4296 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 4048 4297 } … … iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 4057 4306 uint8_t txant; 4058 4307 int i, rate, txrate; 4059 4308 4309 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4310 4060 4311 /* Use the first valid TX antenna. */ 4061 4312 txant = IWN_LSB(sc->txchainmask); 4062 4313 … … iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 4074 4325 else 4075 4326 txrate = rs->rs_nrates - 1; 4076 4327 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 4328 uint32_t plcp; 4329 4077 4330 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4078 4331 rate = IEEE80211_RATE_MCS | txrate; 4079 4332 else 4080 4333 rate = RV(rs->rs_rates[txrate]); 4081 linkq.retry[i] = wn->ridx[rate];4082 4334 4083 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) && 4084 RV(le32toh(wn->ridx[rate])) > 7) 4335 /* Do rate -> PLCP config mapping */ 4336 plcp = iwn_rate_to_plcp(sc, ni, rate); 4337 linkq.retry[i] = plcp; 4338 4339 /* Special case for dual-stream rates? */ 4340 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 4341 RV(le32toh(plcp)) > 7) 4085 4342 linkq.mimo = i + 1; 4086 4343 4087 4344 /* Next retry at immediate lower bit-rate. */ 4088 4345 if (txrate > 0) 4089 4346 txrate--; 4090 4347 } 4348 4349 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4350 4091 4351 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 4092 4352 #undef RV 4093 4353 } … … iwn_add_broadcast_node(struct iwn_softc *sc, int async) 4106 4366 uint8_t txant; 4107 4367 int i, error; 4108 4368 4369 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4370 4371 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 4372 4109 4373 memset(&node, 0, sizeof node); 4110 4374 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 4111 4375 node.id = sc->broadcast_id; … … iwn_add_broadcast_node(struct iwn_softc *sc, int async) 4134 4398 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4135 4399 linkq.retry[i] = linkq.retry[0]; 4136 4400 } 4401 4402 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4403 4137 4404 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4138 4405 } 4139 4406 … … iwn_updateedca(struct ieee80211com *ic) 4145 4412 struct iwn_edca_params cmd; 4146 4413 int aci; 4147 4414 4415 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4416 4148 4417 memset(&cmd, 0, sizeof cmd); 4149 4418 cmd.flags = htole32(IWN_EDCA_UPDATE); 4150 4419 for (aci = 0; aci < WME_NUM_AC; aci++) { … … iwn_updateedca(struct ieee80211com *ic) 4161 4430 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4162 4431 IWN_UNLOCK(sc); 4163 4432 IEEE80211_LOCK(ic); 4433 4434 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4435 4164 4436 return 0; 4165 4437 #undef IWN_EXP2 4166 4438 } … … iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4176 4448 { 4177 4449 struct iwn_cmd_led led; 4178 4450 4451 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4452 4179 4453 /* Clear microcode LED ownership. */ 4180 4454 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4181 4455 … … iwn_set_critical_temp(struct iwn_softc *sc) 4196 4470 struct iwn_critical_temp crit; 4197 4471 int32_t temp; 4198 4472 4473 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4474 4199 4475 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4200 4476 4201 4477 if (sc->hw_type == IWN_HW_REV_TYPE_5150) … … iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4216 4492 struct iwn_cmd_timing cmd; 4217 4493 uint64_t val, mod; 4218 4494 4495 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4496 4219 4497 memset(&cmd, 0, sizeof cmd); 4220 4498 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 4221 4499 cmd.bintval = htole16(ni->ni_intval); … … iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4238 4516 struct ifnet *ifp = sc->sc_ifp; 4239 4517 struct ieee80211com *ic = ifp->if_l2com; 4240 4518 4519 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4520 4241 4521 /* Adjust TX power if need be (delta >= 3 degC). */ 4242 4522 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 4243 4523 __func__, sc->temp, temp); … … iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4273 4553 int i, c, grp, maxpwr; 4274 4554 uint8_t chan; 4275 4555 4556 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 4276 4557 /* Retrieve current channel from last RXON. */ 4277 chan = sc->rxon .chan;4558 chan = sc->rxon->chan; 4278 4559 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4279 4560 chan); 4280 4561 … … iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4409 4690 { 4410 4691 struct iwn5000_cmd_txpower cmd; 4411 4692 4693 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4694 4412 4695 /* 4413 4696 * TX power calibration is handled automatically by the firmware 4414 4697 * for 5000 Series. … … iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4431 4714 uint8_t mask, agc; 4432 4715 int rssi; 4433 4716 4717 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4718 4434 4719 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4435 4720 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4436 4721 … … iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4456 4741 uint8_t agc; 4457 4742 int rssi; 4458 4743 4744 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4745 4459 4746 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4460 4747 4461 4748 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, … … iwn4965_get_temperature(struct iwn_softc *sc) 4497 4784 struct iwn_ucode_info *uc = &sc->ucode_info; 4498 4785 int32_t r1, r2, r3, r4, temp; 4499 4786 4787 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4788 4500 4789 r1 = le32toh(uc->temp[0].chan20MHz); 4501 4790 r2 = le32toh(uc->temp[1].chan20MHz); 4502 4791 r3 = le32toh(uc->temp[2].chan20MHz); … … iwn5000_get_temperature(struct iwn_softc *sc) 4521 4810 { 4522 4811 int32_t temp; 4523 4812 4813 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4814 4524 4815 /* 4525 4816 * Temperature is not used by the driver for 5000 Series because 4526 4817 * TX power calibration is handled by firmware. … … iwn_init_sensitivity(struct iwn_softc *sc) 4544 4835 uint32_t flags; 4545 4836 int error; 4546 4837 4838 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4839 4547 4840 /* Reset calibration state machine. */ 4548 4841 memset(calib, 0, sizeof (*calib)); 4549 4842 calib->state = IWN_CALIB_STATE_INIT; … … iwn_collect_noise(struct iwn_softc *sc, 4583 4876 { 4584 4877 struct iwn_ops *ops = &sc->ops; 4585 4878 struct iwn_calib_state *calib = &sc->calib; 4879 struct ifnet *ifp = sc->sc_ifp; 4880 struct ieee80211com *ic = ifp->if_l2com; 4586 4881 uint32_t val; 4587 4882 int i; 4588 4883 4884 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4885 4589 4886 /* Accumulate RSSI and noise for all 3 antennas. */ 4590 4887 for (i = 0; i < 3; i++) { 4591 4888 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; … … iwn_collect_noise(struct iwn_softc *sc, 4617 4914 4618 4915 #ifdef notyet 4619 4916 /* XXX Disable RX chains with no antennas connected. */ 4620 sc->rxon .rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));4621 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);4917 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4918 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 4622 4919 #endif 4623 4920 4624 #if 04625 /* XXX: not yet */4626 4921 /* Enable power-saving mode if requested by user. */ 4627 if ( sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)4922 if (ic->ic_flags & IEEE80211_F_PMGTON) 4628 4923 (void)iwn_set_pslevel(sc, 0, 3, 1); 4629 #endif 4924 4925 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4926 4630 4927 } 4631 4928 4632 4929 static int … … iwn4965_init_gains(struct iwn_softc *sc) 4634 4931 { 4635 4932 struct iwn_phy_calib_gain cmd; 4636 4933 4934 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4935 4637 4936 memset(&cmd, 0, sizeof cmd); 4638 4937 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4639 4938 /* Differential gains initially set to 0 for all 3 antennas. */ … … iwn5000_init_gains(struct iwn_softc *sc) 4647 4946 { 4648 4947 struct iwn_phy_calib cmd; 4649 4948 4949 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4950 4650 4951 memset(&cmd, 0, sizeof cmd); 4651 4952 cmd.code = sc->reset_noise_gain; 4652 4953 cmd.ngroups = 1; … … iwn4965_set_gains(struct iwn_softc *sc) 4663 4964 struct iwn_phy_calib_gain cmd; 4664 4965 int i, delta, noise; 4665 4966 4967 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4968 4666 4969 /* Get minimal noise among connected antennas. */ 4667 4970 noise = INT_MAX; /* NB: There's at least one antenna. */ 4668 4971 for (i = 0; i < 3; i++) … … iwn5000_set_gains(struct iwn_softc *sc) 4696 4999 struct iwn_phy_calib_gain cmd; 4697 5000 int i, ant, div, delta; 4698 5001 5002 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5003 4699 5004 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4700 5005 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4701 5006 … … iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4754 5059 uint8_t noise[3], noise_ref; 4755 5060 int i, needs_update = 0; 4756 5061 5062 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5063 4757 5064 /* Check that we've been enabled long enough. */ 4758 if ((rxena = le32toh(stats->general.load)) == 0) 5065 if ((rxena = le32toh(stats->general.load)) == 0){ 5066 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 4759 5067 return; 5068 } 4760 5069 4761 5070 /* Compute number of false alarms since last call for OFDM. */ 4762 5071 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; … … iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4874 5183 4875 5184 if (needs_update) 4876 5185 (void)iwn_send_sensitivity(sc); 5186 5187 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5188 4877 5189 #undef dec 4878 5190 #undef inc 4879 5191 } … … iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4938 5250 uint32_t reg; 4939 5251 int i; 4940 5252 5253 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 5254 "%s: dtim=%d, level=%d, async=%d\n", 5255 __func__, 5256 dtim, 5257 level, 5258 async); 5259 4941 5260 /* Select which PS parameters to use. */ 4942 5261 if (dtim <= 2) 4943 5262 pmgt = &iwn_pmgt[0][level]; … … iwn_send_advanced_btcoex(struct iwn_softc *sc) 5041 5360 return error; 5042 5361 5043 5362 /* Force BT state machine change. */ 5044 memset(&btprot, 0, sizeof btpr io);5363 memset(&btprot, 0, sizeof btprot); 5045 5364 btprot.open = 1; 5046 5365 btprot.type = 1; 5047 5366 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); … … iwn_config(struct iwn_softc *sc) 5074 5393 uint16_t rxchain; 5075 5394 int error; 5076 5395 5396 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5397 5077 5398 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 5078 5399 /* Set radio temperature sensor offset. */ 5079 5400 error = iwn5000_temp_offset_calib(sc); … … iwn_config(struct iwn_softc *sc) 5123 5444 } 5124 5445 5125 5446 /* Set mode, channel, RX filter and enable RX. */ 5126 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5127 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 5128 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 5129 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 5130 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5447 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5448 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 5449 IEEE80211_ADDR_COPY(sc->rxon->myaddr, IF_LLADDR(ifp)); 5450 IEEE80211_ADDR_COPY(sc->rxon->wlap, IF_LLADDR(ifp)); 5451 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 5452 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5131 5453 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 5132 sc->rxon .flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);5454 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5133 5455 switch (ic->ic_opmode) { 5134 5456 case IEEE80211_M_STA: 5135 sc->rxon .mode = IWN_MODE_STA;5136 sc->rxon .filter = htole32(IWN_FILTER_MULTICAST);5457 sc->rxon->mode = IWN_MODE_STA; 5458 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 5137 5459 break; 5138 5460 case IEEE80211_M_MONITOR: 5139 sc->rxon .mode = IWN_MODE_MONITOR;5140 sc->rxon .filter = htole32(IWN_FILTER_MULTICAST |5461 sc->rxon->mode = IWN_MODE_MONITOR; 5462 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 5141 5463 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5142 5464 break; 5143 5465 default: 5144 5466 /* Should not get there. */ 5145 5467 break; 5146 5468 } 5147 sc->rxon .cck_mask = 0x0f; /* not yet negotiated */5148 sc->rxon .ofdm_mask = 0xff; /* not yet negotiated */5149 sc->rxon .ht_single_mask = 0xff;5150 sc->rxon .ht_dual_mask = 0xff;5151 sc->rxon .ht_triple_mask = 0xff;5469 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 5470 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 5471 sc->rxon->ht_single_mask = 0xff; 5472 sc->rxon->ht_dual_mask = 0xff; 5473 sc->rxon->ht_triple_mask = 0xff; 5152 5474 rxchain = 5153 5475 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5154 5476 IWN_RXCHAIN_MIMO_COUNT(2) | 5155 5477 IWN_RXCHAIN_IDLE_COUNT(2); 5156 sc->rxon .rxchain = htole16(rxchain);5478 sc->rxon->rxchain = htole16(rxchain); 5157 5479 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 5158 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0);5480 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 5159 5481 if (error != 0) { 5160 5482 device_printf(sc->sc_dev, "%s: RXON command failed\n", 5161 5483 __func__); … … iwn_config(struct iwn_softc *sc) 5187 5509 "%s: could not set power saving level\n", __func__); 5188 5510 return error; 5189 5511 } 5512 5513 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5514 5190 5515 return 0; 5191 5516 } 5192 5517 … … iwn_scan(struct iwn_softc *sc) 5221 5546 uint8_t txant; 5222 5547 int buflen, error; 5223 5548 5549 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5550 5551 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5224 5552 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5225 5553 if (buf == NULL) { 5226 5554 device_printf(sc->sc_dev, … … iwn_scan(struct iwn_softc *sc) 5262 5590 } else { 5263 5591 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5264 5592 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 5265 sc->rxon .associd && sc->rxon.chan > 14)5593 sc->rxon->associd && sc->rxon->chan > 14) 5266 5594 tx->rate = htole32(0xd); 5267 5595 else { 5268 5596 /* Send probe requests at 1Mbps. */ … … iwn_scan(struct iwn_softc *sc) 5321 5649 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5322 5650 chan->rf_gain = 0x3b; 5323 5651 chan->active = htole16(24); 5324 if (sc->rxon .associd)5652 if (sc->rxon->associd) 5325 5653 chan->passive = htole16(78); 5326 5654 else 5327 5655 chan->passive = htole16(110); … … iwn_scan(struct iwn_softc *sc) 5334 5662 } else { 5335 5663 chan->rf_gain = 0x28; 5336 5664 chan->active = htole16(36); 5337 if (sc->rxon .associd)5665 if (sc->rxon->associd) 5338 5666 chan->passive = htole16(88); 5339 5667 else 5340 5668 chan->passive = htole16(120); … … iwn_scan(struct iwn_softc *sc) 5356 5684 hdr->nchan); 5357 5685 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5358 5686 free(buf, M_DEVBUF); 5687 5688 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5689 5359 5690 return error; 5360 5691 } 5361 5692 … … iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5368 5699 struct ieee80211_node *ni = vap->iv_bss; 5369 5700 int error; 5370 5701 5702 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5703 5704 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5371 5705 /* Update adapter configuration. */ 5372 IEEE80211_ADDR_COPY(sc->rxon .bssid, ni->ni_bssid);5373 sc->rxon .chan = ieee80211_chan2ieee(ic, ni->ni_chan);5374 sc->rxon .flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);5706 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 5707 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5708 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5375 5709 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5376 sc->rxon .flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);5710 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5377 5711 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5378 sc->rxon .flags |= htole32(IWN_RXON_SHSLOT);5712 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 5379 5713 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5380 sc->rxon .flags |= htole32(IWN_RXON_SHPREAMBLE);5714 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 5381 5715 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5382 sc->rxon .cck_mask = 0;5383 sc->rxon .ofdm_mask = 0x15;5716 sc->rxon->cck_mask = 0; 5717 sc->rxon->ofdm_mask = 0x15; 5384 5718 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5385 sc->rxon .cck_mask = 0x03;5386 sc->rxon .ofdm_mask = 0;5719 sc->rxon->cck_mask = 0x03; 5720 sc->rxon->ofdm_mask = 0; 5387 5721 } else { 5388 5722 /* Assume 802.11b/g. */ 5389 sc->rxon .cck_mask = 0x0f;5390 sc->rxon .ofdm_mask = 0x15;5723 sc->rxon->cck_mask = 0x0f; 5724 sc->rxon->ofdm_mask = 0x15; 5391 5725 } 5392 5726 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5393 sc->rxon .chan, sc->rxon.flags, sc->rxon.cck_mask,5394 sc->rxon .ofdm_mask);5395 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);5727 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 5728 sc->rxon->ofdm_mask); 5729 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5396 5730 if (error != 0) { 5397 5731 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5398 5732 __func__, error); … … iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5415 5749 error); 5416 5750 return error; 5417 5751 } 5752 5753 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5754 5418 5755 return 0; 5419 5756 } 5420 5757 … … iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5429 5766 uint32_t htflags = 0; 5430 5767 int error; 5431 5768 5769 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5770 5771 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5432 5772 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5433 5773 /* Link LED blinks while monitoring. */ 5434 5774 iwn_set_led(sc, IWN_LED_LINK, 5, 5); … … iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5441 5781 } 5442 5782 5443 5783 /* Update adapter configuration. */ 5444 IEEE80211_ADDR_COPY(sc->rxon .bssid, ni->ni_bssid);5445 sc->rxon .associd = htole16(IEEE80211_AID(ni->ni_associd));5446 sc->rxon .chan = ieee80211_chan2ieee(ic, ni->ni_chan);5447 sc->rxon .flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);5784 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 5785 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 5786 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5787 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5448 5788 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5449 sc->rxon .flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);5789 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5450 5790 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5451 sc->rxon .flags |= htole32(IWN_RXON_SHSLOT);5791 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 5452 5792 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5453 sc->rxon .flags |= htole32(IWN_RXON_SHPREAMBLE);5793 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 5454 5794 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5455 sc->rxon .cck_mask = 0;5456 sc->rxon .ofdm_mask = 0x15;5795 sc->rxon->cck_mask = 0; 5796 sc->rxon->ofdm_mask = 0x15; 5457 5797 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5458 sc->rxon .cck_mask = 0x03;5459 sc->rxon .ofdm_mask = 0;5798 sc->rxon->cck_mask = 0x03; 5799 sc->rxon->ofdm_mask = 0; 5460 5800 } else { 5461 5801 /* Assume 802.11b/g. */ 5462 sc->rxon .cck_mask = 0x0f;5463 sc->rxon .ofdm_mask = 0x15;5802 sc->rxon->cck_mask = 0x0f; 5803 sc->rxon->ofdm_mask = 0x15; 5464 5804 } 5465 5805 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5466 5806 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); … … iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5477 5817 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5478 5818 htflags |= IWN_RXON_HT_HT40MINUS; 5479 5819 } 5480 sc->rxon .flags |= htole32(htflags);5481 sc->rxon .filter |= htole32(IWN_FILTER_BSS);5820 sc->rxon->flags |= htole32(htflags); 5821 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 5482 5822 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5483 sc->rxon .chan, sc->rxon.flags);5484 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);5823 sc->rxon->chan, sc->rxon->flags); 5824 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5485 5825 if (error != 0) { 5486 5826 device_printf(sc->sc_dev, 5487 5827 "%s: could not update configuration, error %d\n", __func__, … … iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5548 5888 5549 5889 /* Link LED always on while associated. */ 5550 5890 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5891 5892 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5893 5551 5894 return 0; 5552 5895 } 5553 5896 … … iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 5568 5911 uint8_t tid; 5569 5912 int error; 5570 5913 5914 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5915 5571 5916 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 5572 5917 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 5573 5918 … … iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 5600 5945 struct iwn_node_info node; 5601 5946 uint8_t tid; 5602 5947 5948 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5949 5603 5950 /* XXX: tid as an argument */ 5604 5951 for (tid = 0; tid < WME_NUM_TID; tid++) { 5605 5952 if (&ni->ni_rx_ampdu[tid] == rap) … … iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5623 5970 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5624 5971 int qid; 5625 5972 5973 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5974 5626 5975 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 5627 5976 if (sc->qid2tap[qid] == NULL) 5628 5977 break; … … iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5650 5999 { 5651 6000 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5652 6001 int qid = *(int *)tap->txa_private; 5653 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);6002 uint8_t tid = tap->txa_ac; // FreeBSD 10.0.0: tap->txa_tid; 5654 6003 int ret; 5655 6004 6005 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6006 5656 6007 if (code == IEEE80211_STATUS_SUCCESS) { 5657 6008 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 5658 6009 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); … … static int 5674 6025 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5675 6026 uint8_t tid) 5676 6027 { 5677 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ TID_TO_WME_AC(tid)];6028 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 5678 6029 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5679 6030 struct iwn_ops *ops = &sc->ops; 5680 6031 struct iwn_node *wn = (void *)ni; 5681 6032 struct iwn_node_info node; 5682 6033 int error, qid; 5683 6034 6035 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6036 5684 6037 /* Enable TX for the specified RA/TID. */ 5685 6038 wn->disable_tid &= ~(1 << tid); 5686 6039 memset(&node, 0, sizeof node); … … iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5709 6062 { 5710 6063 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5711 6064 struct iwn_ops *ops = &sc->ops; 5712 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);6065 uint8_t tid = tap->txa_ac; // FreeBSD 10.0.0: tap->txa_tid; 5713 6066 int qid; 5714 6067 6068 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6069 5715 6070 sc->sc_addba_stop(ni, tap); 5716 6071 5717 6072 if (tap->txa_private == NULL) … … iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5735 6090 { 5736 6091 struct iwn_node *wn = (void *)ni; 5737 6092 6093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6094 5738 6095 /* Stop TX scheduler while we're changing its configuration. */ 5739 6096 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5740 6097 IWN4965_TXQ_STATUS_CHGACT); … … iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5770 6127 static void 5771 6128 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5772 6129 { 6130 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6131 5773 6132 /* Stop TX scheduler while we're changing its configuration. */ 5774 6133 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5775 6134 IWN4965_TXQ_STATUS_CHGACT); … … iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5792 6151 { 5793 6152 struct iwn_node *wn = (void *)ni; 5794 6153 6154 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6155 5795 6156 /* Stop TX scheduler while we're changing its configuration. */ 5796 6157 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5797 6158 IWN5000_TXQ_STATUS_CHGACT); … … iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5826 6187 static void 5827 6188 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5828 6189 { 6190 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6191 5829 6192 /* Stop TX scheduler while we're changing its configuration. */ 5830 6193 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5831 6194 IWN5000_TXQ_STATUS_CHGACT); … … iwn4965_post_alive(struct iwn_softc *sc) 5972 6335 if ((error = iwn_nic_lock(sc)) != 0) 5973 6336 return error; 5974 6337 6338 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6339 5975 6340 /* Clear TX scheduler state in SRAM. */ 5976 6341 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5977 6342 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, … … iwn5000_post_alive(struct iwn_softc *sc) 6022 6387 { 6023 6388 int error, qid; 6024 6389 6025 #ifndef __HAIKU__ 6390 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6391 6026 6392 /* Switch to using ICT interrupt mode. */ 6027 6393 iwn5000_ict_reset(sc); 6028 #endif6029 6394 6030 if ((error = iwn_nic_lock(sc)) != 0) 6395 if ((error = iwn_nic_lock(sc)) != 0){ 6396 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 6031 6397 return error; 6398 } 6032 6399 6033 6400 /* Clear TX scheduler state in SRAM. */ 6034 6401 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); … … iwn5000_post_alive(struct iwn_softc *sc) 6105 6472 /* Send calibration results to runtime firmware. */ 6106 6473 error = iwn5000_send_calibration(sc); 6107 6474 } 6475 6476 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6477 6108 6478 return error; 6109 6479 } 6110 6480 … … iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6228 6598 struct iwn_dma_info *dma = &sc->fw_dma; 6229 6599 int error; 6230 6600 6601 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6602 6231 6603 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6232 6604 memcpy(dma->vaddr, section, size); 6233 6605 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); … … iwn5000_load_firmware(struct iwn_softc *sc) 6264 6636 struct iwn_fw_part *fw; 6265 6637 int error; 6266 6638 6639 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6640 6267 6641 /* Load the initialization firmware on first boot only. */ 6268 6642 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6269 6643 &sc->fw.main : &sc->fw.init; … … iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6429 6803 sc->noise_gain = tmp + 1; 6430 6804 } 6431 6805 break; 6806 case IWN_FW_TLV_PAN: 6807 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 6808 DPRINTF(sc, IWN_DEBUG_RESET, 6809 "PAN Support found: %d\n", 1); 6810 break; 6811 case IWN_FW_TLV_FLAGS : 6812 sc->tlv_feature_flags = htole32(*ptr); 6813 break; 6814 case IWN_FW_TLV_PBREQ_MAXLEN: 6815 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 6816 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 6817 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 6818 case IWN_FW_TLV_INIT_EVTLOG_PTR: 6819 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 6820 case IWN_FW_TLV_INIT_ERRLOG_PTR: 6821 case IWN_FW_TLV_WOWLAN_INST: 6822 case IWN_FW_TLV_WOWLAN_DATA: 6823 DPRINTF(sc, IWN_DEBUG_RESET, 6824 "TLV type %d reconized but not handled\n", 6825 le16toh(tlv->type)); 6826 break; 6432 6827 default: 6433 6828 DPRINTF(sc, IWN_DEBUG_RESET, 6434 6829 "TLV type %d not handled\n", le16toh(tlv->type)); … … iwn_read_firmware(struct iwn_softc *sc) 6446 6841 struct iwn_fw_info *fw = &sc->fw; 6447 6842 int error; 6448 6843 6844 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6845 6449 6846 IWN_UNLOCK(sc); 6450 6847 6451 6848 memset(fw, 0, sizeof (*fw)); … … iwn_apm_init(struct iwn_softc *sc) 6527 6924 uint32_t reg; 6528 6925 int error; 6529 6926 6927 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6928 6530 6929 /* Disable L0s exit timer (NMI bug workaround). */ 6531 6930 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6532 6931 /* Don't wait for ICH L0s (ICH bug workaround). */ … … iwn_apm_stop(struct iwn_softc *sc) 6604 7003 static int 6605 7004 iwn4965_nic_config(struct iwn_softc *sc) 6606 7005 { 7006 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7007 6607 7008 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6608 7009 /* 6609 7010 * I don't believe this to be correct but this is what the … … iwn5000_nic_config(struct iwn_softc *sc) 6626 7027 uint32_t tmp; 6627 7028 int error; 6628 7029 7030 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7031 6629 7032 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6630 7033 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6631 7034 IWN_RFCFG_TYPE(sc->rfcfg) | … … iwn_hw_prepare(struct iwn_softc *sc) 6674 7077 { 6675 7078 int ntries; 6676 7079 7080 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7081 6677 7082 /* Check if hardware is ready. */ 6678 7083 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6679 7084 for (ntries = 0; ntries < 5; ntries++) { … … iwn_hw_init(struct iwn_softc *sc) 6711 7116 struct iwn_ops *ops = &sc->ops; 6712 7117 int error, chnl, qid; 6713 7118 7119 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7120 6714 7121 /* Clear pending interrupts. */ 6715 7122 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6716 7123 … … iwn_hw_init(struct iwn_softc *sc) 6810 7217 return error; 6811 7218 } 6812 7219 /* Do post-firmware initialization. */ 7220 7221 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7222 6813 7223 return ops->post_alive(sc); 6814 7224 } 6815 7225 … … iwn_hw_stop(struct iwn_softc *sc) 6818 7228 { 6819 7229 int chnl, qid, ntries; 6820 7230 7231 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7232 6821 7233 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6822 7234 6823 7235 /* Disable interrupts. */ … … iwn_radio_on(void *arg0, int pending) 6871 7283 struct ieee80211com *ic = ifp->if_l2com; 6872 7284 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6873 7285 7286 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7287 6874 7288 if (vap != NULL) { 6875 7289 iwn_init(sc); 6876 7290 ieee80211_init(vap); … … iwn_radio_off(void *arg0, int pending) 6885 7299 struct ieee80211com *ic = ifp->if_l2com; 6886 7300 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6887 7301 7302 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7303 6888 7304 iwn_stop(sc); 6889 7305 if (vap != NULL) 6890 7306 ieee80211_stop(vap); … … iwn_init_locked(struct iwn_softc *sc) 6902 7318 struct ifnet *ifp = sc->sc_ifp; 6903 7319 int error; 6904 7320 7321 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7322 6905 7323 IWN_LOCK_ASSERT(sc); 6906 7324 6907 7325 if ((error = iwn_hw_prepare(sc)) != 0) { … … iwn_init_locked(struct iwn_softc *sc) 6955 7373 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6956 7374 6957 7375 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 7376 7377 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7378 6958 7379 return; 6959 7380 6960 7381 fail: iwn_stop_locked(sc); 7382 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 6961 7383 } 6962 7384 6963 7385 static void … … iwn_set_channel(struct ieee80211com *ic) 7043 7465 struct iwn_softc *sc = ifp->if_softc; 7044 7466 int error; 7045 7467 7468 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7469 7046 7470 IWN_LOCK(sc); 7047 7471 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 7048 7472 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); … … iwn_hw_reset(void *arg0, int pending) 7097 7521 struct ifnet *ifp = sc->sc_ifp; 7098 7522 struct ieee80211com *ic = ifp->if_l2com; 7099 7523 7524 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7525 7100 7526 iwn_stop(sc); 7101 7527 iwn_init(sc); 7102 7528 ieee80211_notify_radio(ic, 1); 7103 7529 } 7530 #ifdef IWN_DEBUG 7531 #define IWN_DESC(x) case x: return #x 7532 #define COUNTOF(array) (sizeof(array) / sizeof(array[0])) 7533 7534 /* 7535 * Translate CSR code to string 7536 */ 7537 static char *iwn_get_csr_string(int csr) 7538 { 7539 switch (csr) { 7540 IWN_DESC(IWN_HW_IF_CONFIG); 7541 IWN_DESC(IWN_INT_COALESCING); 7542 IWN_DESC(IWN_INT); 7543 IWN_DESC(IWN_INT_MASK); 7544 IWN_DESC(IWN_FH_INT); 7545 IWN_DESC(IWN_GPIO_IN); 7546 IWN_DESC(IWN_RESET); 7547 IWN_DESC(IWN_GP_CNTRL); 7548 IWN_DESC(IWN_HW_REV); 7549 IWN_DESC(IWN_EEPROM); 7550 IWN_DESC(IWN_EEPROM_GP); 7551 IWN_DESC(IWN_OTP_GP); 7552 IWN_DESC(IWN_GIO); 7553 IWN_DESC(IWN_GP_UCODE); 7554 IWN_DESC(IWN_GP_DRIVER); 7555 IWN_DESC(IWN_UCODE_GP1); 7556 IWN_DESC(IWN_UCODE_GP2); 7557 IWN_DESC(IWN_LED); 7558 IWN_DESC(IWN_DRAM_INT_TBL); 7559 IWN_DESC(IWN_GIO_CHICKEN); 7560 IWN_DESC(IWN_ANA_PLL); 7561 IWN_DESC(IWN_HW_REV_WA); 7562 IWN_DESC(IWN_DBG_HPET_MEM); 7563 default: 7564 return "UNKNOWN CSR"; 7565 } 7566 } 7567 7568 /* 7569 * This function print firmware register 7570 */ 7571 static void 7572 iwn_debug_register(struct iwn_softc *sc) 7573 { 7574 int i; 7575 static const uint32_t csr_tbl[] = { 7576 IWN_HW_IF_CONFIG, 7577 IWN_INT_COALESCING, 7578 IWN_INT, 7579 IWN_INT_MASK, 7580 IWN_FH_INT, 7581 IWN_GPIO_IN, 7582 IWN_RESET, 7583 IWN_GP_CNTRL, 7584 IWN_HW_REV, 7585 IWN_EEPROM, 7586 IWN_EEPROM_GP, 7587 IWN_OTP_GP, 7588 IWN_GIO, 7589 IWN_GP_UCODE, 7590 IWN_GP_DRIVER, 7591 IWN_UCODE_GP1, 7592 IWN_UCODE_GP2, 7593 IWN_LED, 7594 IWN_DRAM_INT_TBL, 7595 IWN_GIO_CHICKEN, 7596 IWN_ANA_PLL, 7597 IWN_HW_REV_WA, 7598 IWN_DBG_HPET_MEM, 7599 }; 7600 DPRINTF(sc, IWN_DEBUG_REGISTER, 7601 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 7602 "\n"); 7603 for (i = 0; i < COUNTOF(csr_tbl); i++){ 7604 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 7605 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 7606 if ((i+1) % 3 == 0) 7607 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 7608 } 7609 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 7610 } 7611 #endif -
src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnreg.h
diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnreg.h b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnreg.h index 9aa0d66..911407b 100644
a b 18 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 19 */ 20 20 21 #define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 22 #define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 23 21 24 #define IWN_TX_RING_COUNT 256 22 25 #define IWN_TX_RING_LOMARK 192 23 26 #define IWN_TX_RING_HIMARK 224 … … 38 41 #define IWN_ICT_SIZE 4096 39 42 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 40 43 44 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 45 #define IWN_CMD_QUEUE_NUM 4 46 #define IWN_PAN_CMD_QUEUE 9 47 41 48 /* Maximum number of DMA segments for TX. */ 42 49 #define IWN_MAX_SCATTER 20 43 50 … … 62 69 #define IWN_INT 0x008 63 70 #define IWN_INT_MASK 0x00c 64 71 #define IWN_FH_INT 0x010 72 #define IWN_GPIO_IN 0x018 /* read external chip pins */ 65 73 #define IWN_RESET 0x020 66 74 #define IWN_GP_CNTRL 0x024 67 75 #define IWN_HW_REV 0x028 … … 69 77 #define IWN_EEPROM_GP 0x030 70 78 #define IWN_OTP_GP 0x034 71 79 #define IWN_GIO 0x03c 80 #define IWN_GP_UCODE 0x048 72 81 #define IWN_GP_DRIVER 0x050 82 #define IWN_UCODE_GP1 0x054 83 #define IWN_UCODE_GP1_SET 0x058 73 84 #define IWN_UCODE_GP1_CLR 0x05c 85 #define IWN_UCODE_GP2 0x060 74 86 #define IWN_LED 0x094 75 87 #define IWN_DRAM_INT_TBL 0x0a0 76 88 #define IWN_SHADOW_REG_CTRL 0x0a8 … … 79 91 #define IWN_HW_REV_WA 0x22c 80 92 #define IWN_DBG_HPET_MEM 0x240 81 93 #define IWN_DBG_LINK_PWR_MGMT 0x250 94 /* Need nic_lock for use above */ 82 95 #define IWN_MEM_RADDR 0x40c 83 96 #define IWN_MEM_WADDR 0x410 84 97 #define IWN_MEM_WDATA 0x418 85 98 #define IWN_MEM_RDATA 0x41c 99 #define IWN_TARG_MBX_C 0x430 86 100 #define IWN_PRPH_WADDR 0x444 87 101 #define IWN_PRPH_RADDR 0x448 88 102 #define IWN_PRPH_WDATA 0x44c … … 194 208 #define IWN_GP_CNTRL_SLEEP (1 << 4) 195 209 #define IWN_GP_CNTRL_RFKILL (1 << 27) 196 210 197 /* Possible flags for register IWN_HW_REV. */198 #define IWN_HW_REV_TYPE_SHIFT 4199 #define IWN_HW_REV_TYPE_MASK 0x000000f0200 #define IWN_HW_REV_TYPE_4965 0201 #define IWN_HW_REV_TYPE_5300 2202 #define IWN_HW_REV_TYPE_5350 3203 #define IWN_HW_REV_TYPE_5150 4204 #define IWN_HW_REV_TYPE_5100 5205 #define IWN_HW_REV_TYPE_1000 6206 #define IWN_HW_REV_TYPE_6000 7207 #define IWN_HW_REV_TYPE_6050 8208 #define IWN_HW_REV_TYPE_6005 11209 210 211 /* Possible flags for register IWN_GIO_CHICKEN. */ 211 212 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 212 213 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) … … 220 221 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 221 222 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 222 223 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 224 #define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 223 225 224 226 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 225 227 #define IWN_UCODE_GP1_RFKILL (1 << 1) 226 228 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 227 229 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 230 #define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 228 231 229 232 /* Possible flags/values for register IWN_LED. */ 230 233 #define IWN_LED_BSM_CTRL (1 << 5) 231 234 #define IWN_LED_OFF 0x00000038 232 235 #define IWN_LED_ON 0x00000078 233 236 237 #define IWN_MAX_BLINK_TBL 10 238 #define IWN_LED_STATIC_ON 0 239 #define IWN_LED_STATIC_OFF 1 240 #define IWN_LED_SLOW_BLINK 2 241 #define IWN_LED_INT_BLINK 3 242 #define IWN_LED_UNIT 0x1388 /* 5 ms */ 243 244 static const struct { 245 uint16_t tpt; /* Mb/s */ 246 uint8_t on_time; 247 uint8_t off_time; 248 } blink_tbl[] = 249 { 250 {300, 5, 5}, 251 {200, 8, 8}, 252 {100, 11, 11}, 253 {70, 13, 13}, 254 {50, 15, 15}, 255 {20, 17, 17}, 256 {10, 19, 19}, 257 {5, 22, 22}, 258 {1, 26, 26}, 259 {0, 33, 33}, 260 /* SOLID_ON */ 261 }; 262 234 263 /* Possible flags for register IWN_DRAM_INT_TBL. */ 235 264 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 236 265 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) … … struct iwn_rx_status { 377 406 } __packed; 378 407 379 408 struct iwn_rx_desc { 409 /* 410 * The first 4 bytes of the RX frame header contain both the RX frame 411 * size and some flags. 412 * Bit fields: 413 * 31: flag flush RB request 414 * 30: flag ignore TC (terminal counter) request 415 * 29: flag fast IRQ request 416 * 28-14: Reserved 417 * 13-00: RX frame size 418 */ 380 419 uint32_t len; 381 420 uint8_t type; 382 421 #define IWN_UC_READY 1 383 422 #define IWN_ADD_NODE_DONE 24 384 423 #define IWN_TX_DONE 28 424 #define IWN_REPLY_LED_CMD 72 385 425 #define IWN5000_CALIBRATION_RESULT 102 386 426 #define IWN5000_CALIBRATION_DONE 103 387 427 #define IWN_START_SCAN 130 428 #define IWN_NOTIF_SCAN_RESULT 131 388 429 #define IWN_STOP_SCAN 132 389 430 #define IWN_RX_STATISTICS 156 390 431 #define IWN_BEACON_STATISTICS 157 … … struct iwn_rx_desc { 395 436 #define IWN_RX_DONE 195 396 437 #define IWN_RX_COMPRESSED_BA 197 397 438 398 uint8_t flags; 399 uint8_t idx; 439 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 440 uint8_t idx; /* position within TX queue */ 400 441 uint8_t qid; 442 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 443 * or uCode-originated notification 444 */ 401 445 } __packed; 402 446 447 #define IWN_RX_DESC_QID_MSK 0x1F 448 #define IWN_UNSOLICITED_RX_NOTIF 0x80 449 450 /* CARD_STATE_NOTIFICATION */ 451 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 452 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 453 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 454 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 455 403 456 /* Possible RX status flags. */ 404 457 #define IWN_RX_NO_CRC_ERR (1 << 0) 405 458 #define IWN_RX_NO_OVFL_ERR (1 << 1) … … struct iwn_tx_cmd { 423 476 #define IWN_CMD_LINK_QUALITY 78 424 477 #define IWN_CMD_SET_LED 72 425 478 #define IWN5000_CMD_WIMAX_COEX 90 479 #define IWN_TEMP_NOTIFICATION 98 426 480 #define IWN5000_CMD_CALIB_CONFIG 101 427 481 #define IWN5000_CMD_CALIB_RESULT 102 428 482 #define IWN5000_CMD_CALIB_COMPLETE 103 … … struct iwn_tx_cmd { 439 493 #define IWN_CMD_PHY_CALIB 176 440 494 #define IWN_CMD_BT_COEX_PRIOTABLE 204 441 495 #define IWN_CMD_BT_COEX_PROT 205 496 #define IWN_CMD_BT_COEX_NOTIF 206 497 /* PAN commands */ 498 #define IWN_CMD_WIPAN_PARAMS 0xb2 499 #define IWN_CMD_WIPAN_RXON 0xb3 500 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4 501 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 502 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7 503 #define IWN_CMD_WIPAN_WEPKEY 0xb8 504 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 505 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 506 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 442 507 443 508 uint8_t flags; 444 509 uint8_t idx; … … struct iwn_tx_cmd { 446 511 uint8_t data[136]; 447 512 } __packed; 448 513 514 /* 515 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 516 * all devices identical. 517 * 518 * This command triggers an immediate response containing uCode statistics. 519 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 520 * 521 * If the CLEAR_STATS configuration flag is set, uCode will clear its 522 * internal copy of the statistics (counters) after issuing the response. 523 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 524 * 525 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 526 * IWN_BEACON_STATISTICS after received beacons. This flag 527 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 528 */ 529 struct iwn_statistics_cmd { 530 uint32_t configuration_flags; 531 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 532 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 533 } __packed; 534 449 535 /* Antenna flags, used in various commands. */ 450 536 #define IWN_ANT_A (1 << 0) 451 537 #define IWN_ANT_B (1 << 1) … … struct iwn_tx_cmd { 453 539 /* Shortcuts. */ 454 540 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 455 541 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 542 #define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 456 543 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 457 544 458 545 /* Structure for command IWN_CMD_RXON. */ … … struct iwn_rxon { 468 555 #define IWN_MODE_STA 3 469 556 #define IWN_MODE_IBSS 4 470 557 #define IWN_MODE_MONITOR 6 558 #define IWN_MODE_2STA 8 559 #define IWN_MODE_P2P 9 471 560 472 561 uint8_t air; 473 562 uint16_t rxchain; … … struct iwn_cmd_timing { 551 640 uint16_t atim; 552 641 uint32_t binitval; 553 642 uint16_t lintval; 554 uint16_t reserved; 643 uint8_t dtim_period; 644 uint8_t delta_cp_bss_tbtts; 555 645 } __packed; 556 646 557 647 /* Structure for command IWN_CMD_ADD_NODE. */ … … struct iwn_node_info { 565 655 uint16_t reserved2; 566 656 uint8_t id; 567 657 #define IWN_ID_BSS 0 658 #define IWN_STA_ID 1 659 660 #define IWN_PAN_ID_BCAST 14 568 661 #define IWN5000_ID_BROADCAST 15 569 662 #define IWN4965_ID_BROADCAST 31 570 663 … … struct iwn_pmgt_cmd { 766 859 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 767 860 #define IWN_PS_PCI_PMGT (1 << 3) 768 861 #define IWN_PS_FAST_PD (1 << 4) 862 #define IWN_PS_BEACON_FILTERING (1 << 5) 863 #define IWN_PS_SHADOW_REG (1 << 6) 864 #define IWN_PS_CT_KILL (1 << 7) 865 #define IWN_PS_BT_SCD (1 << 8) 866 #define IWN_PS_ADVANCED_PM (1 << 9) 769 867 770 868 uint8_t keepalive; 771 869 uint8_t debug; … … struct iwn_scan_hdr { 803 901 804 902 struct iwn_scan_chan { 805 903 uint32_t flags; 904 #define IWN_CHAN_PASSIVE (0 << 0) 806 905 #define IWN_CHAN_ACTIVE (1 << 0) 807 906 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 808 907 … … struct iwn_scan_chan { 813 912 uint16_t passive; /* msecs */ 814 913 } __packed; 815 914 915 #define IWN_SCAN_CRC_TH_DISABLED 0 916 #define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 917 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 918 816 919 /* Maximum size of a scan command. */ 817 920 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 818 921 922 #define IWN_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ 923 #define IWN_ACTIVE_DWELL_TIME_52 (20) 924 #define IWN_ACTIVE_DWELL_FACTOR_24 (3) 925 #define IWN_ACTIVE_DWELL_FACTOR_52 (2) 926 927 #define IWN_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ 928 #define IWN_PASSIVE_DWELL_TIME_52 (10) 929 #define IWN_PASSIVE_DWELL_BASE (100) 930 #define IWN_CHANNEL_TUNE_TIME (5) 931 932 #define IWN_SCAN_CHAN_TIMEOUT 2 933 819 934 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 820 935 #define IWN_RIDX_MAX 32 821 936 struct iwn4965_cmd_txpower { … … struct iwn_bluetooth { 862 977 863 978 struct iwn6000_btcoex_config { 864 979 uint8_t flags; 980 #define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 981 #define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 982 #define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 983 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 984 #define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 985 #define IWN_BT_FLAG_COEX6000_MODE_3W 2 986 #define IWN_BT_FLAG_COEX6000_MODE_4W 3 987 988 #define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 989 #define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 865 990 uint8_t lead_time; 866 991 uint8_t max_kill; 867 992 uint8_t bt3_t7_timer; … … struct iwn6000_btcoex_config { 878 1003 uint16_t rx_prio_boost; 879 1004 } __packed; 880 1005 1006 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1007 struct iwn2000_btcoex_config { 1008 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1009 uint8_t lead_time; 1010 uint8_t max_kill; 1011 uint8_t bt3_t7_timer; 1012 uint32_t kill_ack; 1013 uint32_t kill_cts; 1014 uint8_t sample_time; 1015 uint8_t bt3_t2_timer; 1016 uint16_t bt4_reaction; 1017 uint32_t lookup_table[12]; 1018 uint16_t bt4_decision; 1019 uint16_t valid; 1020 1021 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1022 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1023 1024 uint8_t tx_prio_boost; 1025 uint16_t rx_prio_boost; 1026 } __packed; 1027 881 1028 struct iwn_btcoex_priotable { 882 1029 uint8_t calib_init1; 883 1030 uint8_t calib_init2; … … struct iwn5000_phy_calib_temp_offset { 996 1143 uint16_t reserved; 997 1144 } __packed; 998 1145 1146 struct iwn5000_phy_calib_temp_offsetv2 { 1147 uint8_t code; 1148 uint8_t group; 1149 uint8_t ngroups; 1150 uint8_t isvalid; 1151 int16_t offset_high; 1152 int16_t offset_low; 1153 int16_t burnt_voltage_ref; 1154 int16_t reserved; 1155 } __packed; 1156 999 1157 struct iwn_phy_calib_gain { 1000 1158 uint8_t code; 1001 1159 uint8_t group; … … struct iwn_ucode_info { 1063 1221 } __packed; 1064 1222 1065 1223 /* Structures for IWN_TX_DONE notification. */ 1224 #define IWN_TX_STATUS_MSK 0xff 1225 #define TX_STATUS_SUCCESS 0x01 1226 #define TX_STATUS_DIRECT_DONE 0x02 1227 1066 1228 #define IWN_TX_SUCCESS 0x00 1067 1229 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1068 1230 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ … … struct iwn4965_tx_stat { 1084 1246 } __packed; 1085 1247 1086 1248 struct iwn5000_tx_stat { 1087 uint8_t nframes; 1249 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1088 1250 uint8_t btkillcnt; 1089 1251 uint8_t rtsfailcnt; 1090 1252 uint8_t ackfailcnt; … … struct iwn5000_tx_stat { 1096 1258 uint16_t seq; 1097 1259 uint16_t len; 1098 1260 uint8_t tlc; 1099 uint8_t ratid; 1261 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1100 1262 uint8_t fc[2]; 1101 1263 uint16_t status; 1102 1264 uint16_t sequence; … … struct iwn_rx_stat { 1144 1306 uint16_t chan; 1145 1307 uint8_t phybuf[32]; 1146 1308 uint32_t rate; 1309 /* 1310 * rate bit fields 1311 * 1312 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1313 * 2-0: 0) 6 Mbps 1314 * 1) 12 Mbps 1315 * 2) 18 Mbps 1316 * 3) 24 Mbps 1317 * 4) 36 Mbps 1318 * 5) 48 Mbps 1319 * 6) 54 Mbps 1320 * 7) 60 Mbps 1321 * 1322 * 4-3: 0) Single stream (SISO) 1323 * 1) Dual stream (MIMO) 1324 * 2) Triple stream (MIMO) 1325 * 1326 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1327 * 1328 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1329 * 3-0: 0xD) 6 Mbps 1330 * 0xF) 9 Mbps 1331 * 0x5) 12 Mbps 1332 * 0x7) 18 Mbps 1333 * 0x9) 24 Mbps 1334 * 0xB) 36 Mbps 1335 * 0x1) 48 Mbps 1336 * 0x3) 54 Mbps 1337 * 1338 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1339 * 6-0: 10) 1 Mbps 1340 * 20) 2 Mbps 1341 * 55) 5.5 Mbps 1342 * 110) 11 Mbps 1343 * 1344 */ 1147 1345 uint16_t len; 1148 1346 uint16_t reserve3; 1149 1347 } __packed; … … struct iwn_fw_tlv { 1366 1564 #define IWN_FW_TLV_INIT_DATA 4 1367 1565 #define IWN_FW_TLV_BOOT_TEXT 5 1368 1566 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1567 #define IWN_FW_TLV_PAN 7 1568 #define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1569 #define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1570 #define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1571 #define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1572 #define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1573 #define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1369 1574 #define IWN_FW_TLV_ENH_SENS 14 1370 1575 #define IWN_FW_TLV_PHY_CALIB 15 1576 #define IWN_FW_TLV_WOWLAN_INST 16 1577 #define IWN_FW_TLV_WOWLAN_DATA 17 1578 #define IWN_FW_TLV_FLAGS 18 1371 1579 1372 1580 uint16_t alt; 1373 1581 uint32_t len; … … struct iwn_fw_tlv { 1401 1609 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1402 1610 #define IWN4965_EEPROM_BANDS 0x0ea 1403 1611 /* Indirect offsets. */ 1612 #define IWN5000_EEPROM_NO_HT40 0x000 1404 1613 #define IWN5000_EEPROM_DOMAIN 0x001 1405 1614 #define IWN5000_EEPROM_BAND1 0x004 1406 1615 #define IWN5000_EEPROM_BAND2 0x013 … … static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1512 1721 IWN5000_EEPROM_BAND7 1513 1722 }; 1514 1723 1724 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1725 IWN5000_EEPROM_BAND1, 1726 IWN5000_EEPROM_BAND2, 1727 IWN5000_EEPROM_BAND3, 1728 IWN5000_EEPROM_BAND4, 1729 IWN5000_EEPROM_BAND5, 1730 IWN5000_EEPROM_BAND6, 1731 IWN5000_EEPROM_NO_HT40, 1732 }; 1733 1515 1734 #define IWN_CHAN_BANDS_COUNT 7 1516 1735 #define IWN_MAX_CHAN_PER_BAND 14 1517 1736 static const struct iwn_chan_band { … … static const struct iwn_chan_band { 1531 1750 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1532 1751 }; 1533 1752 1753 static const uint8_t iwn_bss_ac_to_queue[] = { 1754 2, 3, 1, 0, 1755 }; 1756 1757 static const uint8_t iwn_pan_ac_to_queue[] = { 1758 5, 4, 6, 7, 1759 }; 1534 1760 #define IWN1000_OTP_NBLOCKS 3 1535 1761 #define IWN6000_OTP_NBLOCKS 4 1536 1762 #define IWN6050_OTP_NBLOCKS 7 … … static const struct iwn_chan_band { 1540 1766 #define IWN_RIDX_OFDM6 4 1541 1767 1542 1768 #define IWN4965_MAX_PWR_INDEX 107 1769 #define IWN_POWERSAVE_LVL_NONE 0 1770 #define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 1771 #define IWN_POWERSAVE_LVL_MAX 5 1772 1773 #define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 1774 1775 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 1776 #define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 1543 1777 1544 1778 /* 1545 1779 * RF Tx gain values from highest to lowest power (values obtained from … … static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1722 1956 100 1723 1957 }; 1724 1958 1959 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 1960 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 1961 105,110, 1962 128,232, 1963 80,145, 1964 128,232, 1965 125,175, 1966 160,310, 1967 97, 1968 97, 1969 110 1970 }; 1971 1725 1972 /* Map TID to TX scheduler's FIFO. */ 1726 1973 static const uint8_t iwn_tid2fifo[] = { 1727 1974 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 … … static const char * const iwn_fw_errmsg[] = { 1772 2019 "NMI_INTERRUPT_DATA_ACTION_PT", 1773 2020 "NMI_TRM_HW_ER", 1774 2021 "NMI_INTERRUPT_TRM", 1775 "NMI_INTERRUPT_BREAKPOINT" ,2022 "NMI_INTERRUPT_BREAKPOINT" 1776 2023 "DEBUG_0", 1777 2024 "DEBUG_1", 1778 2025 "DEBUG_2", -
src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnvar.h
diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnvar.h b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwnvar.h index 7647b09..d1c0b76 100644
a b 2 2 /* $OpenBSD: if_iwnvar.h,v 1.18 2010/04/30 16:06:46 damien Exp $ */ 3 3 4 4 /*- 5 * Copyright (c) 2013 Cedric GROSS <cg@cgross.info> 6 * Copyright (c) 2011 Intel Corporation 5 7 * Copyright (c) 2007, 2008 6 8 * Damien Bergamini <damien.bergamini@free.fr> 7 9 * Copyright (c) 2008 Sam Leffler, Errno Consulting … … 18 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 22 */ 23 enum iwn_rxon_ctx_id { 24 IWN_RXON_BSS_CTX, 25 IWN_RXON_PAN_CTX, 26 IWN_NUM_RXON_CTX 27 }; 28 29 struct iwn_pan_slot { 30 uint16_t time; 31 uint8_t type; 32 uint8_t reserved; 33 } __packed; 34 35 struct iwn_pan_params_cmd { 36 uint16_t flags; 37 #define IWN_PAN_PARAMS_FLG_SLOTTED_MODE (1 << 3) 38 39 uint8_t reserved; 40 uint8_t num_slots; 41 struct iwn_pan_slot slots[10]; 42 } __packed; 43 44 struct iwn_led_mode 45 { 46 uint8_t led_cur_mode; 47 uint64_t led_cur_bt; 48 uint64_t led_last_bt; 49 uint64_t led_cur_tpt; 50 uint64_t led_last_tpt; 51 uint64_t led_bt_diff; 52 int led_cur_time; 53 int led_last_time; 54 }; 21 55 22 56 struct iwn_rx_radiotap_header { 23 57 struct ieee80211_radiotap_header wr_ihdr; … … struct iwn_node { 102 136 struct ieee80211_node ni; /* must be the first */ 103 137 uint16_t disable_tid; 104 138 uint8_t id; 105 uint32_t ridx[256];106 139 struct { 107 140 uint64_t bitmap; 108 141 int startidx; … … struct iwn_vap { 192 225 193 226 int (*iv_newstate)(struct ieee80211vap *, 194 227 enum ieee80211_state, int); 228 int ctx; 229 int beacon_int; 230 uint8_t macaddr[IEEE80211_ADDR_LEN]; 231 195 232 }; 196 233 #define IWN_VAP(_vap) ((struct iwn_vap *)(_vap)) 197 234 … … struct iwn_softc { 211 248 #define IWN_FLAG_HAS_11N (1 << 6) 212 249 #define IWN_FLAG_ENH_SENS (1 << 7) 213 250 #define IWN_FLAG_ADV_BTCOEX (1 << 8) 251 #define IWN_FLAG_PAN_SUPPORT (1 << 9) 214 252 215 253 uint8_t hw_type; 254 /* subdevice_id used to adjust configuration */ 255 uint16_t subdevice_id; 216 256 217 257 struct iwn_ops ops; 218 258 const char *fwname; … … struct iwn_softc { 254 294 struct iwn_tx_ring txq[IWN5000_NTXQUEUES]; 255 295 struct iwn_rx_ring rxq; 256 296 297 int mem_rid; 257 298 struct resource *mem; 258 299 bus_space_tag_t sc_st; 259 300 bus_space_handle_t sc_sh; 301 int irq_rid; 260 302 struct resource *irq; 261 303 void *sc_ih; 262 304 bus_size_t sc_sz; … … struct iwn_softc { 271 313 int calib_cnt; 272 314 struct iwn_calib_state calib; 273 315 struct callout watchdog_to; 274 316 struct callout ct_kill_exit_to; 275 317 struct iwn_fw_info fw; 276 318 struct iwn_calib_info calibcmd[5]; 277 319 uint32_t errptr; … … struct iwn_softc { 279 321 struct iwn_rx_stat last_rx_stat; 280 322 int last_rx_valid; 281 323 struct iwn_ucode_info ucode_info; 282 struct iwn_rxon rxon; 324 struct iwn_rxon rx_on[IWN_NUM_RXON_CTX]; 325 struct iwn_rxon *rxon; 326 int ctx; 327 struct ieee80211vap *ivap[IWN_NUM_RXON_CTX]; 328 329 uint8_t uc_scan_progress; 283 330 uint32_t rawtemp; 284 331 int temp; 285 332 int noise; … … struct iwn_softc { 294 341 char eeprom_domain[4]; 295 342 uint32_t eeprom_crystal; 296 343 int16_t eeprom_temp; 344 int16_t eeprom_temp_high; 297 345 int16_t eeprom_voltage; 298 346 int8_t maxpwr2GHz; 299 347 int8_t maxpwr5GHz; 300 348 int8_t maxpwr[IEEE80211_CHAN_MAX]; 301 349 350 uint32_t tlv_feature_flags; 351 302 352 int32_t temp_off; 303 353 uint32_t int_mask; 304 354 uint8_t ntxchains; … … struct iwn_softc { 308 358 uint8_t chainmask; 309 359 310 360 int sc_tx_timer; 361 int sc_scan_timer; 311 362 312 363 struct ieee80211_tx_ampdu *qid2tap[IWN5000_NTXQUEUES]; 313 364 … … struct iwn_softc { 322 373 void (*sc_addba_stop)(struct ieee80211_node *, 323 374 struct ieee80211_tx_ampdu *); 324 375 376 struct iwn_led_mode sc_led; 325 377 326 378 struct iwn_rx_radiotap_header sc_rxtap; 327 379 struct iwn_tx_radiotap_header sc_txtap; 328 380 329 #if defined(__HAIKU__) 330 uint32_t sc_intr_status_1; 331 uint32_t sc_intr_status_2; 332 #endif 381 /* The power save level originally configured by user */ 382 int desired_pwrsave_level; 383 384 /* 385 * The current power save level, this may differ from the 386 * configured value due to thermal throttling etc. 387 */ 388 int current_pwrsave_level; 389 390 /* For specifique params */ 391 struct iwn_base_params *base_params; 333 392 }; 334 393 335 394 #define IWN_LOCK_INIT(_sc) \ -
src/add-ons/kernel/drivers/network/wlan/iprowifi4965/glue.c
diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/glue.c b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/glue.c index 198bece..9b91f42 100644
a b HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) 56 56 return 0; 57 57 } 58 58 59 /* 59 60 atomic_set((int32*)&sc->sc_intr_status_1, r1); 60 61 atomic_set((int32*)&sc->sc_intr_status_2, r2); 62 */ 61 63 62 64 IWN_WRITE(sc, IWN_INT_MASK, 0); 63 65 // disable interrupts -
src/libs/compat/freebsd_wlan/net80211/ieee80211_output.c
diff --git a/src/libs/compat/freebsd_wlan/net80211/ieee80211_output.c b/src/libs/compat/freebsd_wlan/net80211/ieee80211_output.c index eb5ccb3..4a86174 100644
a b ieee80211_beacon_update(struct ieee80211_node *ni, 3063 3063 3064 3064 return len_changed; 3065 3065 } 3066 3067 /* 3068 * Added in FreeBSD 10.0.0 3069 */ 3070 3071 /* 3072 * Complete an mbuf transmission. 3073 * 3074 * For now, this simply processes a completed frame after the 3075 * driver has completed it's transmission and/or retransmission. 3076 * It assumes the frame is an 802.11 encapsulated frame. 3077 * 3078 * Later on it will grow to become the exit path for a given frame 3079 * from the driver and, depending upon how it's been encapsulated 3080 * and already transmitted, it may end up doing A-MPDU retransmission, 3081 * power save requeuing, etc. 3082 * 3083 * In order for the above to work, the driver entry point to this 3084 * must not hold any driver locks. Thus, the driver needs to delay 3085 * any actual mbuf completion until it can release said locks. 3086 * 3087 * This frees the mbuf and if the mbuf has a node reference, 3088 * the node reference will be freed. 3089 */ 3090 void 3091 ieee80211_tx_complete(struct ieee80211_node *ni, struct mbuf *m, int status) 3092 { 3093 3094 if (ni != NULL) { 3095 if (m->m_flags & M_TXCB) 3096 ieee80211_process_callback(ni, m, status); 3097 ieee80211_free_node(ni); 3098 } 3099 m_freem(m); 3100 } -
src/libs/compat/freebsd_wlan/net80211/ieee80211_phy.h
diff --git a/src/libs/compat/freebsd_wlan/net80211/ieee80211_phy.h b/src/libs/compat/freebsd_wlan/net80211/ieee80211_phy.h index 7508fe2..b247e17 100644
a b ieee80211_ack_duration(const struct ieee80211_rate_table *rt, 137 137 } 138 138 139 139 /* 140 * Declaration required for FreeBSD 10.0.0 iwn 141 */ 142 143 static __inline__ uint8_t 144 ieee80211_legacy_rate_lookup(const struct ieee80211_rate_table *rt, 145 uint8_t rate) 146 { 147 148 return (rt->rateCodeToIndex[rate & IEEE80211_RATE_VAL]); 149 } 150 151 /* 140 152 * Compute the time to transmit a frame of length frameLen bytes 141 153 * using the specified 802.11 rate code, phy, and short preamble 142 154 * setting. -
src/libs/compat/freebsd_wlan/net80211/ieee80211_proto.h
diff --git a/src/libs/compat/freebsd_wlan/net80211/ieee80211_proto.h b/src/libs/compat/freebsd_wlan/net80211/ieee80211_proto.h index 2b32557..8eed278 100644
a b int ieee80211_send_probereq(struct ieee80211_node *ni, 117 117 const uint8_t da[IEEE80211_ADDR_LEN], 118 118 const uint8_t bssid[IEEE80211_ADDR_LEN], 119 119 const uint8_t *ssid, size_t ssidlen); 120 void ieee80211_tx_complete(struct ieee80211_node *, 121 struct mbuf *, int); 120 122 /* 121 123 * The formation of ProbeResponse frames requires guidance to 122 124 * deal with legacy clients. When the client is identified as