Ticket #13343: 0001-xhci-Transfer-complete-semaphore-was-not-being-relea.patch

src/add-ons/kernel/busses/usb/xhci.cpp

@@ -1 +1 @@
 /*
- * Copyright 2006-2014, Haiku Inc. All rights reserved.
+ * Copyright 2006-2017, Haiku Inc. All rights reserved.
  * Distributed under the terms of the MIT License.
  *
  * Some code borrowed from the Haiku EHCI driver
@@ -517 +517 @@
     dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS
         * sizeof(xhci_trb);
     TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
+    //Make sure Command Ring is stopped
+    WriteOpReg(XHCI_CRCR_LO, CRCR_CA );
     WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS);
     WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0);
     // link trb
@@ -566 +568 @@
     SetRootHub(fRootHub);
 
     TRACE_ALWAYS("successfully started the controller\n");
-#ifdef TRACE_USB
+//#ifdef TRACE_USB
+#if 1
     TRACE("No-Op test...\n");
     status_t noopResult = Noop();
-    TRACE("No-Op %ssuccessful\n", noopResult < B_OK ? "un" : "");
+    TRACE_ALWAYS("No-Op %ssuccessful\n", noopResult < B_OK ? "un" : "");
 #endif
 
     //DumpRing(fCmdRing, (XHCI_MAX_COMMANDS - 1));
@@ -637 +640 @@
     }
 
     // set StatusStage
+    setupDescriptor->trbs[index].qwtrb0 = 0;
     setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0);
     setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32(
         TRB_3_TYPE(TRB_TYPE_STATUS_STAGE)
@@ -1095 +1099 @@
 
     uint8 slot = XHCI_MAX_SLOTS;
     if (EnableSlot(&slot) != B_OK) {
-        TRACE_ERROR("AllocateDevice() failed enable slot\n");
+        TRACE_ERROR("AllocateDevice() failed enable slot %d\n",slot);
         return NULL;
+    } else { 
+        TRACE_ALWAYS("EnableSlot %d\n",slot);
     }
 
     if (slot == 0 || slot > fSlotCount) {
@@ -1310 +1316 @@
         return NULL;
     }
 
-    TRACE("device_class: %d device_subclass %d device_protocol %d\n",
+    TRACE_ALWAYS("device_class: %d device_subclass %d device_protocol %d\n",
         deviceDescriptor.device_class, deviceDescriptor.device_subclass,
         deviceDescriptor.device_protocol);
 
@@ -1525 +1531 @@
     TRACE("_LinkDescriptorForPipe\n");
     MutexLocker endpointLocker(endpoint->lock);
     if (endpoint->used >= XHCI_MAX_TRANSFERS) {
-        TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded\n");
+        TRACE_ERROR("_LinkDescriptorForPipe max transfers count exceeded %d\n",endpoint->used );
+        //Seem to have a problem with interupts not occuring when this happens
+        //and endpoints are not being freed. 
         return B_BAD_VALUE;
     }
 
@@ -1812 +1820 @@
     default:
         return B_BAD_VALUE;
     }
-    ReadOpReg(portRegister);
     return B_OK;
 }
 
@@ -1861 +1868 @@
         return B_BAD_VALUE;
     }
 
-    ReadOpReg(portRegister);
     return B_OK;
 }
 
@@ -1893 +1899 @@
     while (ReadOpReg(XHCI_CMD) & CMD_HCRST) {
         snooze(1000);
         if (tries-- < 0) {
-            TRACE("ControllerReset() failed CMD_HCRST\n");
+            TRACE_ERROR("ControllerReset() failed CMD_HCRST\n");
             return B_ERROR;
         }
     }
@@ -1902 +1908 @@
     while (ReadOpReg(XHCI_STS) & STS_CNR) {
         snooze(1000);
         if (tries-- < 0) {
-            TRACE("ControllerReset() failed STS_CNR\n");
+            TRACE_ERROR("ControllerReset() failed STS_CNR\n");
             return B_ERROR;
         }
     }
@@ -2051 +2057 @@
             int64 offset = source - td_chain->this_phy;
             TRACE("HandleTransferComplete td %p offset %" B_PRId64 " %"
                 B_PRIxADDR "\n", td_chain, offset, source);
-            offset = offset / sizeof(xhci_trb);
+            offset = offset / sizeof(xhci_trb) +1;
             if (offset <= td_chain->trb_count && offset >= 0) {
                 TRACE("HandleTransferComplete td %p trb %" B_PRId64 " found "
                     "\n", td_chain, offset);
@@ -2129 +2135 @@
 
     trb->dwtrb2 = fCmdResult[0];
     trb->dwtrb3 = fCmdResult[1];
-    TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2,
+    TRACE("Storing command trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2,
         trb->dwtrb3);
 
     Unlock();
@@ -2171 +2177 @@
 status_t
 XHCI::DisableSlot(uint8 slot)
 {
-    TRACE("Disable Slot\n");
+    TRACE("Disable Slot %d\n", slot);
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -2184 +2190 @@
 status_t
 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot)
 {
-    TRACE("Set Address\n");
+    TRACE_ALWAYS("Set Address slot %d 0x%016" B_PRIx64 "\n", slot, inputContext);
     xhci_trb trb;
     trb.qwtrb0 = inputContext;
     trb.dwtrb2 = 0;

src/add-ons/kernel/busses/usb/xhci_hardware.h

@@ -91 +91 @@
 #define XHCI_CRCR_LO        0x18
 #define XHCI_CRCR_HI        0x1C
 #define CRCR_RCS            (1<<0)
+#define CRCR_CS             (1<<1)
+#define CRCR_CA             (1<<2)
+#define CRCR_CRR            (1<<3)
+
 // Section 5.4.6
 #define XHCI_DCBAAP_LO      0x30
 #define XHCI_DCBAAP_HI      0x34