From 6654e11b9e02a5b632658a81dce5d8d1b1eea2c8 Mon Sep 17 00:00:00 2001
From: Jessica Hamilton <jessica.l.hamilton@gmail.com>
Date: Thu, 14 Sep 2017 13:53:27 +1200
Subject: [PATCH] radeon_hd: testing framebuffer config
---
src/add-ons/accelerants/radeon_hd/accelerant.h | 2 +-
src/add-ons/accelerants/radeon_hd/display.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.h b/src/add-ons/accelerants/radeon_hd/accelerant.h
index 94c43a6f26..7b233ae590 100644
a
|
b
|
|
22 | 22 | #include "ringqueue.h" |
23 | 23 | |
24 | 24 | |
25 | | #define MAX_DISPLAY 2 |
| 25 | #define MAX_DISPLAY 4 |
26 | 26 | // Maximum displays (more then two requires AtomBIOS) |
27 | 27 | #define MAX_GPIO_PINS 64 |
28 | 28 | // Maximum possible GPIO pins in gGPIOInfo |
diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp b/src/add-ons/accelerants/radeon_hd/display.cpp
index 7dcfc29ce5..2c4a472ff3 100644
a
|
b
|
display_crtc_fb_set(uint8 crtcID, display_mode* mode)
|
827 | 827 | Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF)); |
828 | 828 | |
829 | 829 | if (info.chipsetID >= RADEON_R600) { |
830 | | Write32(CRT, regs->grphControl, fbFormat); |
| 830 | Write32(CRT, regs->grphControl, fbFormat | (((4) & 0x1f) << 24)); |
831 | 831 | Write32(CRT, regs->grphSwapControl, fbSwap); |
832 | 832 | } |
833 | 833 | |