Ticket #14672: 0001-A-PCI-to-ISA-Bridge-header-file-and-a-test-for-it.patch

new file headers/os/drivers/pci_isa_bridge.h

@@ +1 @@
+/*
+ * Copyright 2018, Jorma Karvonen, karvonen.jorma_at_gmail.com. 
+ * All rights reserved.
+ * Distributed under the terms of the MIT License.
+ *
+ * PC87200 is a PCI to ISA bus bridge developed by National Semiconductor 
+ * (later acquired by Texas Instruments) in 1999. The new PC99 specification 
+ * required then PC manufacturers to migrate from ISA to PCI system bus. 
+ * PCI-to-ISA Bridge converts PCI transactions to industry-standard 
+ * architecture (ISA) bus transactions and enables PC manufactures to 
+ * add up to four ISA slots to their PC99-compliant systems. ISA bus 
+ * was also used in some computer as an internal bus of the 
+ * computer even after ISA bus slots were removed from the modern 
+ * motherboards. 
+ */
+
+#ifndef _PCI_ISA_BRIDGE_H
+#define _PCI_ISA_BRIDGE_H
+
+#include <SupportDefs.h>
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * 0 = Disable, 1 = Enable; 
+    */
+    uint8 io_space: 1;
+    /** 
+    * 0 = Disable, 1 = Enable; 
+    */
+    uint8 memory_space: 1;
+    /** 
+    * 0 = Disable, 1 = Enable; 
+    */
+    uint8 bus_master: 1;
+    /** 
+    * Not supported, it must always be set to 0. 
+    */
+    uint8 speacial_cycles: 1;
+    /** 
+    * Allow PC87200 to do memory write and invalidate 
+    * cycles, if the PCI cache line register is set to 
+    * 16 bytes (04h). 0 = Disable, 1 = Enable. 
+    */
+    uint8 memory_write_and_invalidate: 1;
+    /** 
+    * Read only - This function is not supported in 
+    * PC87200. It is always disabled (bit is set to 0). 
+    */
+    uint8 vga_palette_snoop_enable: 1;
+    /**
+    * Allow PC87200 to check for parity errors on PCI 
+    * cycles for which it is a target, and to assert 
+    * PERR# when a parity error is detected: 
+    * 0 = Disable, 1 = Enable. 
+    */
+    uint8 parity_error: 1;
+    /**
+    * Read only - This function is not supported in 
+    * PC87200. It is always disabled (bit is set to 0). 
+    */
+    uint8 wait_cycle_control: 1;
+    /** 
+    * Allow SERR# assertion on detection of special 
+    * errors: 0 = Disable, 1 = Enable. 
+    */
+    uint8 serr_no: 1;
+    /** 
+    * Read only - This function is not supported in 
+    * PC87200. It is always disabled (bit is set to 0). 
+    */
+    uint8 fast_back_to_back_enable: 1;
+    /** 
+    * Reserved - Set to 0. 
+    */
+    uint8 reserved10: 6;
+}  pci_command;
+
+typedef struct __attribute__ ((packed)) {
+    /**
+    * Reserved - Set to 0. 
+    */
+    uint8 reserved: 6; 
+    /** 
+    * Fast Back-to-Back Capable - As a target, PC87200 
+    * is capable of accepting fast back-to-back transactions: 
+    * 0 = Disable, 1 = Enable. This bit is always set to 1. 
+    */
+    uint8 fast_back_to_back_capable: 1; 
+    /** 
+    * Data Parity Detected - This bit is set when: 
+    * 1) The 87200 asserted PERR# or observed PERR# asserted. 
+    * 2) PC87200 is the master for the cycle in which the 
+    * PERR# occurred., and PE is set (F0 Index 04h[6] = 1). 
+    * Write 1 to clear. 
+    */
+    uint8 data_parity_detected: 1; 
+    /** 
+    * Always 1 (Medium DEVSEL# timing or Reserved) 
+    */
+    uint8 devsel_no_0: 1; 
+    /** 
+    * 0 = Medium - Always 0 as the PC87200 will always 
+    * respond to cycles for which it is an active target 
+    * with medium DEVSEL# timing. 
+    * 1 = Fast 
+    */
+    uint8 devsel_no_1: 1; 
+    /** 
+    * Signalled Target Abort - This bit is set whenever 
+    * the 87200 signals a target abort. This occurs when 
+    * an address parity error occurs for an address that 
+    * hits in the  active address decode space of the 
+    * PC87200. Write 1 to clear. 
+    */
+    uint8 signalled_target_abort: 1; 
+    /** 
+    * Received Target Abort - This bit is set whenever a 
+    * target abort is received while the PC87200 is the 
+    * master for the PCI cycle. Write 1 to clear. 
+    */
+    uint8 received_target_abort: 1; 
+    /** 
+    * Received Master Abort - This bit is set whenever a 
+    * master abort cycle occurs. A master abort will occur 
+    * when a PCI cycle is not claimed, except for special 
+    * cycles. Write 1 to clear. Register is cleared after 
+    * RMA is read. 
+    */
+    uint8 received_master_abort: 1; 
+    /** 
+    * Signalled System Error - This bit is set whenever 
+    * PC87200 asserts SERR# active. Write 1 to clear. 
+    */
+    uint8 signalled_system_error: 1; 
+    /** 
+    * Detected Parity Error - This bit is set whenever 
+    * a parity error is detected. Write 1 to clear. 
+    */
+    uint8 detected_parity_error: 1; 
+} pci_status;
+
+typedef struct __attribute__ ((packed)) {
+    /** Index 09h. */ 
+    uint8 readonly0; 
+    /** Index 0Ah. */ 
+    uint8 readonly1; 
+    /** Index 0Bh. */ 
+    uint8 readonly2; 
+} pci_class_code;
+
+typedef struct __attribute__ ((packed)) {
+    uint8 pci_latency_timer_value: 4; 
+    /** 
+    * Reserved - Set to 0. 
+    */ 
+    uint8 reserved: 4; 
+} pci_latency_timer;
+
+typedef struct __attribute__ ((packed)) { 
+    uint8 type: 7; 
+    /** 
+    * Multifunction device (bit7 = 1).
+    * Not multifunction device (bit7 = 0).
+    */ 
+    uint8 multifunction: 1; 
+} pci_header_type;
+
+typedef struct __attribute__ ((packed)) {
+    /**
+    * BS8/16 - This bit can not be written. Always = 1.
+    */ 
+    uint8 bs8_slash_16: 1;
+    /** Reserved - set to 0. */
+    uint8 reserved: 2;
+    /** 
+    * Write Buffer - PCI slave write buffer: 0 = Disable; 1 = Enable.
+    */
+    uint8 write_buffer: 1;
+    /**
+    * Retry PCI Cycles - Retry inbound PCI cycles if data is 
+    * buffered and waiting to go outbound on PCI: 
+    * 0 = No Retry; 1 = Retry.
+    */
+    uint8 retry_pci_cycles: 1;
+    /**
+    * Single Read Mode - PC87200 accepts only single cycle read 
+    * transfers as a slave on the PCI bus and performs a target 
+    * disconnected with the firs data transferred. 
+    * 0 = Disable; 1 = Enable.
+    * Note: Bits 6 and 5 emulate the behaviour of first generation 
+    * devices developed for PCI.
+    */
+    uint8 single_read_mode: 1;
+    /**
+    * Single Write Mode - PC87200 accepts only single cycle write 
+    * transfers as a slave on the PCI bus and performs a target 
+    * disconnect with the first data transferred: 
+    * 0 = Disable (accepts burst write cycles);
+    * 1 = Enable.
+    * Note: Bits 6 and 5 emulate the behaviour of first generation 
+    * devices developed for PCI.
+    */
+    uint8 single_write_mode: 1;
+    /** Internal use, do not overwrite. */
+    uint8 internal_use_do_not_overwrite: 1;
+} pci_function_control_1;
+
+typedef struct __attribute__ ((packed)) {
+    /** Internal use, do not overwrite. */
+    uint8 internal_use_do_not_overwite: 1;
+    /**
+    * Subtractive Decode - These bits determine the point at which 
+    * the PC87200 accepts cycles that are not claimed by another 
+    * device. The PC87200 defaults to taking subtractive decode 
+    * cycles in the default cycle clock, but can be moved up to the 
+    * Slow Decode cycle point if all other PCI devices decode in 
+    * the fast or medium clocks. Disabling subtractive decode must 
+    * be done with care, as all ISA and ROM cycles are decoded 
+    * subtractively. 
+    * 00 = Default sample (4th clock from FRAME# active) 
+    * 01 = Slow sample (3rd clock from FRAME# active) 
+    * 1x = No subtractive decode. 
+    */
+    uint8 subtractive_decode: 2;
+    /**
+    * Internal use, do not overwrite.
+    */
+    uint8 another_internal_use: 1;
+    /**
+    * Write Buffer Enable - Allow 16-byte buffering for X-Bus 
+    * to PCI bus writes: 0 = Disable; 1 = Enable.
+    */
+    uint8 write_buffer_enable: 1;
+    /**
+    * PERR# Signals SERR# - Assert SERR# any time that PERR# 
+    * is asserted or detected active by the PC87200 (allows PERR# 
+    * assertion to be cascaded to NMI (SMI) generation in the 
+    * system): 0 = Disable; 1 = Enable.
+    */
+    uint8 perr_signals_serr: 1;
+    /**
+    * Internal use, do not overwrite.
+    */
+    uint8 again_internal_use: 1;
+    /**
+    * Burst to Beat - Bursts are converted to single beats for 
+    * X-Bus to PCI bus reads: 0 = Disable; 1 = Enable.
+    */
+    uint8 burst_to_beat: 1;
+} pci_function_control_2;
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1;
+    /** 
+    * No X-Bus ARB, Buffer Enable - When PC87200 is a PCI target, 
+    * allow buffer PCI transactions without X-Bus arbitration: 
+    * 0 = Disable, 1 = Enable. 
+    */
+    uint8 no_x_bus_arb: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1;
+    /** 
+    * Delayed Transactions - Allow delayed transactions on the 
+    * PCI bus: 0 = Disable, 1 = Enable. 
+    */
+    uint8 delayed_transactions: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use5: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use6: 1;
+} pci_function_control_3; 
+
+typedef struct __attribute__ ((packed)) { 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1;
+    /** 
+    * PCI Retry Cycles - When PC87200 is a PCI target and 
+    * the PCI buffer is empty, allow PCI bus to retry 
+    * cycles. 
+    * 0 = Disable, 1 = Enable.
+    * This works in conjunction with PCI bus delayed transactions 
+    * bit. F0 Index 42[5] must = 1 for this bit to be valid.
+    */
+    uint8 pci_retry_cycles: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use3: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use5: 1;
+    /** 
+    * Reserved. Set to 0.
+    */
+    uint8 reserved: 1;
+} pci_function_control_4; 
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * X-Bus Warm Start. 
+    * Write only: 0 = NOP, 1 = Execute system wide reset (used 
+    * only for clock configuration at power-up).
+    */
+    uint8 x_bus_warm_start: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use3: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use5: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use6: 1;
+} reset_control;
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * Determines the divisor of the PCI clock used to generate 
+    * the ISA bus clock.
+    * 010 = Divide by three (ISA clock = 11MHz). 
+    * 011 = Divide by four (ISA clock = 8.33MHz).
+    * All other values are invalid and can produce unexpected results.
+    */
+    uint8 isa_clock_divisor: 3;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use3: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1;
+} isa_clk;
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * 16-bit I/O Recovery - These bits determine the number of 
+    * ISA bus clocks between back-to-back 16 bit I/O read cycles. 
+    * This count is in addition to a preset one-clock delay 
+    * built into the controller. 
+    * 0000 = 1 PCI clock1101 = 14 PCI clocks.
+    * 0001 = 2 PCI clocks1110 = 15 PCI clocks.
+    * 1111 = 16 PCI clocks.
+    */
+    uint8 isa_16bit_i_o_recovery: 4;
+    /** 
+    * 8-bit I/O Recovery - These bits determine the number of 
+    * ISA bus clocks between back-to-back 8-bit I/O read cycle. 
+    * This count is in addition to a preset one-clock delay 
+    * built in the controller. 
+    */
+    uint8 isa_8bit_i_o_recovery: 4;
+} isa_i_o_recovery_control; 
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1;
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1;
+    /** 
+    * ROM 1MB Enable - Allow addressing to 512K or 1MB ROM 
+    * (FFF00000h - FFFFFFFFh).
+    * 0 = Disable, 1 = Enable. 
+    */
+    uint8 rom_1mb_enable: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use3: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use5: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use6: 1; 
+} rom_at_logic_control; 
+
+typedef struct __attribute__ ((packed)) {
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use0: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use1: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use2: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use3: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use4: 1; 
+    /** 
+    * BIOS ROM Positive Decode - Selects positive or subtractive 
+    * decoding for accesses to the configured ROM space. 
+    * 0 = Subtractive, 1 = Positive.
+    */
+    uint8 bios_rom_positive_decode: 1; 
+    /** 
+    * Reserved - Set to 0. 
+    */
+    uint8 reserved: 1; 
+    /** 
+    * Internal use, do not overwrite. 
+    */
+    uint8 internal_use5: 1; 
+} decode_control; 
+
+typedef struct bridge_configuration_registers {
+    /**
+    * Vendor Identification Register. 
+    * Index 00h - 01h. 
+    * Read only.
+    * Reset Value 100Bh. 
+    */
+    uint16 vendor_identification_register;
+
+    /**
+    * Device Identification Register
+    * Index 02h - 03h. 
+    * Read Only. 
+    * Reset Value 0021h. 
+    */
+    uint16 device_identification_register;
+
+    /**
+    * PCI Command Register. 
+    * Index 04h - 05h. 
+    * Read/Write. 
+    * Reset Value 0107h. 
+    */
+    pci_command pci_command_register;
+
+    /**
+    * PCI Status Register. 
+    * Index 06h - 07h. 
+    * Read/Write. 
+    * Reset value 0280h. 
+    */
+    pci_status pci_status_register;
+    
+    /**
+    * Device Revision ID Register. 
+    * Index 08h. 
+    * Read only. 
+    * Reset Value 00h. 
+    */
+    uint8 device_revision_id_register; 
+    
+    /** 
+    * PCI Class Code Register. 
+    * Index 09h - 0Bh. 
+    * Read only. 
+    * Reset Value 060100h. 
+    */
+    pci_class_code pci_class_code_register; 
+    
+    /** 
+    * PCI Cache Line Size Register. 
+    * Index 0Ch. 
+    * Read/Write. Reserved.
+    * Reset Value 00h. 
+    */
+    uint8 pci_cache_line_size_register; 
+    
+    /**
+    * PCI Latency Timer Value - The PCI Latency Timer. 
+    * Index 0Dh. 
+    * Read/Write. 
+    * Register prevents system lockup when a slave does 
+    * not respond to a cycle that the PC87200 masters. If the 
+    * value is set to 00h (default), the timer is disabled. 
+    * If the timer is written with any other value, bits [3:0] 
+    * become the four most significant bytes in a timer that 
+    * counts PCI clocks for slave response. The timer is reset 
+    * on each valid data transfer. If the counter expires before 
+    * the next assertion of TRDY# is received, the PC87200 
+    * stops the transaction with a master abort and asserts 
+    * SERR#, if enabled to do so. 
+    * Reset Value 00h. 
+    */
+    pci_latency_timer pci_latency_timer_register; 
+    
+    /** 
+    * PCI Header Type Register. 
+    * Index 0Eh. 
+    * Read only. 
+    * This register defines the format of this header. 
+    * This header is of type format 0. Additionally, 
+    * bit 7 defines whether this PCI device is a multifunction 
+    * device (bit7 = 1) or not (bit7 = 0).          
+    * Reset Value 00h. 
+    */
+    pci_header_type pci_header_type_register; 
+    
+    /** 
+    * PCI BIST Register. 
+    * Index 0Fh. 
+    * Read only. Set to 0.
+    * Reset Value 00h. 
+    */
+    uint8 pci_bist_register; 
+    
+    /** 
+    * Reserved registers. 
+    * Index 10h - 3Fh. 
+    * Do not access. 
+    * Reset Value 00h. 
+    */
+    uint8 reserved[48];
+    
+    /**
+    * PCI Function Control Register 1.
+    * Index 40h. 
+    * Read/Write. 
+    * Reset value 79h. 
+    */
+    pci_function_control_1 pci_function_control_register_1;
+    
+    /**
+    * PCI Function Control Register 2. 
+    * Index 41h. 
+    * Read/Write. 
+    * Reset Value 10h. 
+    */
+    pci_function_control_2 pci_function_control_register_2;
+
+    /**
+    * PCI Function Control Register 3. 
+    * Index 42h. 
+    * Read/Write. 
+    * Reset Value 28h. 
+    */
+    pci_function_control_3 pci_function_control_register_3;
+
+    /**
+    * PCI Function Control Register 4. 
+    * Index 43h. 
+    * Read/Write. 
+    * Reset Value 46h. 
+    */
+    pci_function_control_4 pci_function_control_register_4;
+
+    /**
+    * Reset Control Register. 
+    * Index 44h. 
+    * Read/Write. 
+    * Reset Value 00000000b. 
+    */
+    reset_control reset_control_register;
+    
+    /** 
+    * Internal use, do not overwrite. 
+    * Index 45h - 4Fh.
+    */ 
+    uint8 internal_use[11] ;
+
+    /** 
+    * ISA CLK Divider. 
+    * Index 50h. 
+    * Read/Write. 
+    * Reset Value 43h. 
+    */
+    isa_clk isa_clk_divider; 
+    
+    /** 
+    * ISA I/O Recovery Control Register. 
+    * Index 51h. 
+    * Read/Write. 
+    * Reset Value 43h. 
+    */
+    isa_i_o_recovery_control isa_i_o_recovery_control_register; 
+    
+    /** 
+    * ROM/AT Logic Control Register. 
+    * Index 52h. 
+    * Read/Write. 
+    * Reset Value 04h. 
+    */
+    rom_at_logic_control rom_at_logic_control_register; 
+    
+    /** 
+    * Internal use, do not overwrite. 
+    * Index 53h - 5Ah.
+    */ 
+    uint8 another_internal_use[8];
+    
+    /** 
+    * Decode Control Register 2. 
+    * Index 5Bh. 
+    * Read/Write. 
+    * Reset Value 00h. 
+    */
+    decode_control decode_control_register_2; 
+    
+    /** 
+    * Internal use, do not overwrite. 
+    * Index 5Ch - FFh. 
+    */ 
+    uint8 third_internal_use[163]; 
+}  __attribute__ ((packed)) pci_isa_bridge_configuration_registers;
+
+#endif /* _PCI_ISA_BRIDGE_H */
+

new file src/tests/add-ons/kernel/drivers/pciisabridge/Jamfile

@@ +1 @@
+SubDir HAIKU_TOP src tests add-ons kernel drivers pciisabridge ;
+
+UseHeaders [ FDirName $(HAIKU_TOP) headers os drivers ] : true ;
+
+Application pciisabridge_test : 
+    main.cpp    
+    ;
+
+

new file src/tests/add-ons/kernel/drivers/pciisabridge/main.cpp

@@ +1 @@
+/*
+ * Copyright 2018, Jorma Karvonen, karvonen.jorma_at_gmail.com. 
+ * All rights reserved.
+ * Distributed under the terms of the MIT License.
+ */
+
+#include <stdio.h>
+#include <pci_isa_bridge.h>
+
+int main(int argc, char* argv[])
+{
+    pci_isa_bridge_configuration_registers bridge;
+    bridge.vendor_identification_register = 0xFFFF;
+
+    unsigned long arvo = (unsigned long)sizeof(bridge);
+    if (arvo == (unsigned long)0xFF) {
+    printf("PCI-to-ISA bridge configuration registers struct size : %lu bytes.\n",
+         arvo);
+    } else {
+        printf("PCI-to-ISA bridge configuration registers struct size "\
+            " should be %lu bytes, but it is %lu bytes.\n", 
+            (unsigned long)0xFF, arvo);
+    }
+
+    printf("Vendor Identification Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.vendor_identification_register));
+
+    printf("Device Identification Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.device_identification_register));
+
+    printf("PCI Command Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_command_register));
+
+    printf("PCI Status Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_status_register));
+
+    printf("Device Revision ID Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.device_revision_id_register));
+
+    printf("PCI Class Code Register struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.pci_class_code_register));
+
+    printf("PCI Cache Line Size Register struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.pci_cache_line_size_register));
+
+    printf("PCI Latency Timer Register struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.pci_latency_timer_register));
+
+    printf("PCI Header Type Register struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.pci_header_type_register));
+
+    printf("PCI BIST Register struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.pci_bist_register));
+
+    printf("reserved[48] array size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.reserved));
+
+    printf("PCI Function Control Register 1 struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_function_control_register_1));
+
+    printf("PCI Function Control Register 2 struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_function_control_register_2));
+
+    printf("PCI Function Control Register 3 struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_function_control_register_3));
+
+    printf("PCI Function Control Register 4 struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.pci_function_control_register_4));
+
+    printf("Reset Control Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.reset_control_register));
+
+    printf("internal_use[11] array size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.internal_use));
+
+    printf("ISA CLK Divider struct size: %lu bytes.\n",
+    (unsigned long)sizeof(bridge.isa_clk_divider));
+
+    printf("ISA I/O Recovery Control Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.isa_i_o_recovery_control_register));
+
+    printf("ROM/AT Logic Control Register struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.rom_at_logic_control_register));
+
+    printf("another_intenal_use[8] array size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.another_internal_use));
+
+    printf("Decode Control Register 2 struct size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.decode_control_register_2));
+
+    printf("third_Intenal_use[163] array size: %lu bytes. \n",
+    (unsigned long)sizeof(bridge.third_internal_use));
+
+    return 0;
+}