Ticket #1590: broadcom570x.diff
| File broadcom570x.diff, 43.3 KB (added by , 15 years ago) |
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build/jam/HaikuImage
142 142 $(X86_ONLY)via_rhine wb840 $(X86_ONLY)ipro100 $(X86_ONLY)nforce 143 143 #vlance 144 144 $(X86_ONLY)marvell_yukon $(X86_ONLY)syskonnect usb_ecm 145 $(GPL_ONLY)bcm440x $(GPL_ONLY)bcm570x 145 $(GPL_ONLY)bcm440x $(GPL_ONLY)bcm570x broadcom570x 146 146 ; 147 147 #BEOS_ADD_ONS_DRIVERS_ACPI = $(X86_ONLY)acpi_button ; 148 148 BEOS_ADD_ONS_BUS_MANAGERS = pci $(X86_ONLY)ps2 $(X86_ONLY)isa ide scsi … … 161 161 : generic_ide_pci it8211 legacy_sata silicon_image_3112 $(X86_ONLY)ide_isa ; 162 162 AddFilesToHaikuImage beos system add-ons kernel busses scsi 163 163 : ahci ; 164 AddFilesToHaikuImage beos system add-ons kernel busses usb165 : <usb>uhci <usb>ohci <usb>ehci ;164 #AddFilesToHaikuImage beos system add-ons kernel busses usb 165 # : <usb>uhci <usb>ohci <usb>ehci ; 166 166 AddFilesToHaikuImage beos system add-ons kernel console : vga_text ; 167 167 AddFilesToHaikuImage beos system add-ons kernel debugger 168 168 : $(X86_ONLY)<kdebug>disasm <kdebug>hangman <kdebug>invalidate_on_exit ; … … 385 385 $(PPC_ONLY)openpic 386 386 ide_adapter locked_pool scsi_periph 387 387 ahci generic_ide_pci it8211 legacy_sata silicon_image_3112 $(X86_ONLY)ide_isa 388 <usb>uhci <usb>ohci <usb>ehci388 # <usb>uhci <usb>ohci <usb>ehci 389 389 scsi_cd scsi_disk usb_disk 390 390 intel 391 391 bfs -
src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h
30 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.73 2007/05/22 19:22:58 jkimExp $33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.73.2.4 2008/06/27 03:24:54 jhb Exp $ 34 34 */ 35 35 36 36 /* … … 277 277 #define BGE_CHIPID_BCM5755_A0 0xa0000000 278 278 #define BGE_CHIPID_BCM5755_A1 0xa0010000 279 279 #define BGE_CHIPID_BCM5755_A2 0xa0020000 280 #define BGE_CHIPID_BCM5722_A0 0xa2000000 280 281 #define BGE_CHIPID_BCM5754_A0 0xb0000000 281 282 #define BGE_CHIPID_BCM5754_A1 0xb0010000 282 283 #define BGE_CHIPID_BCM5754_A2 0xb0020000 283 284 #define BGE_CHIPID_BCM5787_A0 0xb0000000 284 285 #define BGE_CHIPID_BCM5787_A1 0xb0010000 285 286 #define BGE_CHIPID_BCM5787_A2 0xb0020000 287 #define BGE_CHIPID_BCM5906_A1 0xc0010000 288 #define BGE_CHIPID_BCM5906_A2 0xc0020000 286 289 287 290 /* shorthand one */ 288 291 #define BGE_ASICREV(x) ((x) >> 28) … … 299 302 #define BGE_ASICREV_BCM5755 0x0a 300 303 #define BGE_ASICREV_BCM5754 0x0b 301 304 #define BGE_ASICREV_BCM5787 0x0b 305 #define BGE_ASICREV_BCM5906 0x0c 302 306 303 307 /* chip revisions */ 304 308 #define BGE_CHIPREV(x) ((x) >> 24) … … 1438 1442 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1439 1443 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1440 1444 1445 /* 1446 * V? CPU registers 1447 */ 1448 #define BGE_VCPU_STATUS 0x5100 1449 #define BGE_VCPU_EXT_CTRL 0x6890 1441 1450 1451 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1452 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1453 1454 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1455 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1456 1442 1457 /* 1443 1458 * TX CPU registers 1444 1459 */ … … 1684 1699 #define BGE_EE_DELAY 0x6848 1685 1700 #define BGE_FASTBOOT_PC 0x6894 1686 1701 1702 /* 1703 * NVRAM Control registers 1704 */ 1705 #define BGE_NVRAM_CMD 0x7000 1706 #define BGE_NVRAM_STAT 0x7004 1707 #define BGE_NVRAM_WRDATA 0x7008 1708 #define BGE_NVRAM_ADDR 0x700c 1709 #define BGE_NVRAM_RDDATA 0x7010 1710 #define BGE_NVRAM_CFG1 0x7014 1711 #define BGE_NVRAM_CFG2 0x7018 1712 #define BGE_NVRAM_CFG3 0x701c 1713 #define BGE_NVRAM_SWARB 0x7020 1714 #define BGE_NVRAM_ACCESS 0x7024 1715 #define BGE_NVRAM_WRITE1 0x7028 1716 1717 #define BGE_NVRAMCMD_RESET 0x00000001 1718 #define BGE_NVRAMCMD_DONE 0x00000008 1719 #define BGE_NVRAMCMD_START 0x00000010 1720 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1721 #define BGE_NVRAMCMD_ERASE 0x00000040 1722 #define BGE_NVRAMCMD_FIRST 0x00000080 1723 #define BGE_NVRAMCMD_LAST 0x00000100 1724 1725 #define BGE_NVRAM_READCMD \ 1726 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1727 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1728 #define BGE_NVRAM_WRITECMD \ 1729 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1730 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1731 1732 #define BGE_NVRAMSWARB_SET0 0x00000001 1733 #define BGE_NVRAMSWARB_SET1 0x00000002 1734 #define BGE_NVRAMSWARB_SET2 0x00000003 1735 #define BGE_NVRAMSWARB_SET3 0x00000004 1736 #define BGE_NVRAMSWARB_CLR0 0x00000010 1737 #define BGE_NVRAMSWARB_CLR1 0x00000020 1738 #define BGE_NVRAMSWARB_CLR2 0x00000040 1739 #define BGE_NVRAMSWARB_CLR3 0x00000080 1740 #define BGE_NVRAMSWARB_GNT0 0x00000100 1741 #define BGE_NVRAMSWARB_GNT1 0x00000200 1742 #define BGE_NVRAMSWARB_GNT2 0x00000400 1743 #define BGE_NVRAMSWARB_GNT3 0x00000800 1744 #define BGE_NVRAMSWARB_REQ0 0x00001000 1745 #define BGE_NVRAMSWARB_REQ1 0x00002000 1746 #define BGE_NVRAMSWARB_REQ2 0x00004000 1747 #define BGE_NVRAMSWARB_REQ3 0x00008000 1748 1749 #define BGE_NVRAMACC_ENABLE 0x00000001 1750 #define BGE_NVRAMACC_WRENABLE 0x00000002 1751 1687 1752 /* Mode control register */ 1688 1753 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1689 1754 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 … … 1711 1776 /* Misc. config register */ 1712 1777 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1713 1778 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1779 #define BGE_MISCCFG_BOARD_ID 0x0001E000 1780 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1781 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1782 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1714 1783 1715 1784 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1716 1785 … … 2011 2080 #define BCOM_DEVICEID_BCM5715S 0x1679 2012 2081 #define BCOM_DEVICEID_BCM5720 0x1658 2013 2082 #define BCOM_DEVICEID_BCM5721 0x1659 2083 #define BCOM_DEVICEID_BCM5722 0x165A 2014 2084 #define BCOM_DEVICEID_BCM5750 0x1676 2015 2085 #define BCOM_DEVICEID_BCM5750M 0x167C 2016 2086 #define BCOM_DEVICEID_BCM5751 0x1677 … … 2037 2107 #define BCOM_DEVICEID_BCM5901 0x170D 2038 2108 #define BCOM_DEVICEID_BCM5901A2 0x170E 2039 2109 #define BCOM_DEVICEID_BCM5903M 0x16FF 2110 #define BCOM_DEVICEID_BCM5906 0x1712 2111 #define BCOM_DEVICEID_BCM5906M 0x1713 2040 2112 2041 2113 /* 2042 2114 * Alteon AceNIC PCI vendor/device ID. … … 2090 2162 * Offset of MAC address inside EEPROM. 2091 2163 */ 2092 2164 #define BGE_EE_MAC_OFFSET 0x7C 2165 #define BGE_EE_MAC_OFFSET_5906 0x10 2093 2166 #define BGE_EE_HWCFG_OFFSET 0xC8 2094 2167 2095 2168 #define BGE_HWCFG_VOLTAGE 0x00000003 … … 2458 2531 uint32_t bge_flags; 2459 2532 #define BGE_FLAG_TBI 0x00000001 2460 2533 #define BGE_FLAG_JUMBO 0x00000002 2461 #define BGE_FLAG_EEPROM 0x00000004 2534 #define BGE_FLAG_WIRESPEED 0x00000004 2535 #define BGE_FLAG_EADDR 0x00000008 2462 2536 #define BGE_FLAG_MSI 0x00000100 2463 2537 #define BGE_FLAG_PCIX 0x00000200 2464 2538 #define BGE_FLAG_PCIE 0x00000400 … … 2474 2548 #define BGE_FLAG_BER_BUG 0x02000000 2475 2549 #define BGE_FLAG_ADJUST_TRIM 0x04000000 2476 2550 #define BGE_FLAG_CRC_BUG 0x08000000 2551 #define BGE_FLAG_5788 0x20000000 2477 2552 uint32_t bge_chipid; 2478 2553 uint8_t bge_asicrev; 2479 2554 uint8_t bge_chiprev; … … 2506 2581 #ifdef DEVICE_POLLING 2507 2582 int rxcycles; 2508 2583 #endif /* DEVICE_POLLING */ 2584 u_int32_t bge_intr_status; 2585 int transmitting; 2509 2586 }; 2510 2587 2511 2588 #define BGE_LOCK_INIT(_sc, _name) \ … … 2514 2591 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2515 2592 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2516 2593 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2594 -
src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c
32 32 */ 33 33 34 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198 2007/09/30 11:05:14 mariusExp $");35 __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198.2.9 2008/06/27 03:24:54 jhb Exp $"); 36 36 37 37 /* 38 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. … … 169 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 172 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 173 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 174 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, … … 195 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 196 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 197 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 198 201 199 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 200 203 … … 205 208 206 209 static const struct bge_vendor { 207 210 uint16_t v_id; 208 211 const char *v_name; 209 212 } bge_vendors[] = { 210 213 { ALTEON_VENDORID, "Alteon" }, 211 214 { ALTIMA_VENDORID, "Altima" }, … … 219 222 220 223 static const struct bge_revision { 221 224 uint32_t br_chipid; 222 225 const char *br_name; 223 226 } bge_revisions[] = { 224 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 225 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, … … 267 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 268 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 269 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 270 274 /* 5754 and 5787 share the same ASIC ID */ 271 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 272 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 273 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 274 280 275 281 { 0, NULL } 276 282 }; … … 293 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 294 300 /* 5754 and 5787 share the same ASIC ID */ 295 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 296 303 297 304 { 0, NULL } 298 305 }; … … 305 312 306 313 const struct bge_revision * bge_lookup_rev(uint32_t); 307 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 308 318 static int bge_probe(device_t); 309 319 static int bge_attach(device_t); 310 320 static int bge_detach(device_t); … … 315 325 static int bge_dma_alloc(device_t); 316 326 static void bge_dma_free(struct bge_softc *); 317 327 328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 333 318 334 static void bge_txeof(struct bge_softc *); 319 335 static void bge_rxeof(struct bge_softc *); 320 336 … … 337 353 static int bge_ifmedia_upd(struct ifnet *); 338 354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 339 355 356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 358 340 359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 341 360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 342 361 … … 356 375 static int bge_chipinit(struct bge_softc *); 357 376 static int bge_blockinit(struct bge_softc *); 358 377 359 static int bge_has_e eprom(struct bge_softc *);378 static int bge_has_eaddr(struct bge_softc *); 360 379 static uint32_t bge_readmem_ind(struct bge_softc *, int); 361 380 static void bge_writemem_ind(struct bge_softc *, int, int); 381 //bge_writembx() used in glue.c 382 void bge_writembx(struct bge_softc *, int, int); 362 383 #ifdef notdef 363 384 static uint32_t bge_readreg_ind(struct bge_softc *, int); 364 385 #endif … … 378 399 static void bge_sig_legacy(struct bge_softc *, int); 379 400 static void bge_sig_pre_reset(struct bge_softc *, int); 380 401 static int bge_reset(struct bge_softc *); 381 staticvoid bge_link_upd(struct bge_softc *);402 /*static*/ void bge_link_upd(struct bge_softc *); 382 403 383 404 /* 384 405 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may … … 425 446 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 426 447 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 427 448 428 static int bge_allow_asf = 1;449 static int bge_allow_asf = 0; 429 450 430 451 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 431 452 … … 440 461 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 441 462 442 463 static int 443 bge_has_e eprom(struct bge_softc *sc)464 bge_has_eaddr(struct bge_softc *sc) 444 465 { 445 466 #ifdef __sparc64__ 446 467 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; … … 533 554 CSR_WRITE_4(sc, off, val); 534 555 } 535 556 557 void 558 bge_writembx(struct bge_softc *sc, int off, int val) 559 { 560 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 561 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 562 563 CSR_WRITE_4(sc, off, val); 564 } 565 536 566 /* 537 567 * Map a single buffer address. 538 568 */ … … 555 585 ctx->bge_busaddr = segs->ds_addr; 556 586 } 557 587 588 static uint8_t 589 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 590 { 591 uint32_t access, byte = 0; 592 int i; 593 594 /* Lock. */ 595 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 596 for (i = 0; i < 8000; i++) { 597 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 598 break; 599 DELAY(20); 600 } 601 if (i == 8000) 602 return (1); 603 604 /* Enable access. */ 605 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 606 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 607 608 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 609 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 610 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 611 DELAY(10); 612 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 613 DELAY(10); 614 break; 615 } 616 } 617 618 if (i == BGE_TIMEOUT * 10) { 619 if_printf(sc->bge_ifp, "nvram read timed out\n"); 620 return (1); 621 } 622 623 /* Get result. */ 624 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 625 626 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 627 628 /* Disable access. */ 629 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 630 631 /* Unlock. */ 632 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 633 CSR_READ_4(sc, BGE_NVRAM_SWARB); 634 635 return (0); 636 } 637 558 638 /* 639 * Read a sequence of bytes from NVRAM. 640 */ 641 static int 642 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 643 { 644 int err = 0, i; 645 uint8_t byte = 0; 646 647 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 648 return (1); 649 650 for (i = 0; i < cnt; i++) { 651 err = bge_nvram_getbyte(sc, off + i, &byte); 652 if (err) 653 break; 654 *(dest + i) = byte; 655 } 656 657 return (err ? 1 : 0); 658 } 659 660 /* 559 661 * Read a byte of data stored in the EEPROM at address 'addr.' The 560 662 * BCM570x supports both the traditional bitbang interface and an 561 663 * auto access interface for reading the EEPROM. We use the auto … … 659 761 } 660 762 661 763 if (i == BGE_TIMEOUT) { 662 device_printf(sc->bge_dev, "PHY read timed out\n"); 764 device_printf(sc->bge_dev, 765 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 766 phy, reg, val); 663 767 val = 0; 664 768 goto done; 665 769 } 666 770 771 DELAY(5); 667 772 val = CSR_READ_4(sc, BGE_MI_COMM); 668 773 669 774 done: … … 687 792 688 793 sc = device_get_softc(dev); 689 794 795 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 796 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 797 return(0); 798 690 799 /* Reading with autopolling on may trigger PCI errors */ 691 800 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 692 801 if (autopoll & BGE_MIMODE_AUTOPOLL) { … … 699 808 700 809 for (i = 0; i < BGE_TIMEOUT; i++) { 701 810 DELAY(10); 702 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 811 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 812 DELAY(5); 813 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 703 814 break; 704 815 } 816 } 705 817 706 818 if (i == BGE_TIMEOUT) { 707 device_printf(sc->bge_dev, "PHY write timed out\n"); 819 device_printf(sc->bge_dev, 820 "PHY write timed out (phy %d, reg %d, val %d)\n", 821 phy, reg, val); 708 822 return (0); 709 823 } 710 824 … … 887 1001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 1002 889 1003 sc->bge_std = i - 1; 890 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);1004 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 891 1005 892 1006 return (0); 893 1007 } … … 934 1048 BGE_RCB_FLAG_USE_EXT_RX_BD); 935 1049 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 936 1050 937 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);1051 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 938 1052 939 1053 return (0); 940 1054 } … … 990 1104 991 1105 /* Initialize transmit producer index for host-memory send ring. */ 992 1106 sc->bge_tx_prodidx = 0; 993 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);1107 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 994 1108 995 1109 /* 5700 b2 errata */ 996 1110 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 997 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);1111 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 998 1112 999 1113 /* NIC-memory send ring not used; initialize to zero. */ 1000 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);1114 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1001 1115 /* 5700 b2 errata */ 1002 1116 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1003 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);1117 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1004 1118 1005 1119 return (0); 1006 1120 } … … 1168 1282 /* 1169 1283 * Check the 'ROM failed' bit on the RX CPU to see if 1170 1284 * self-tests passed. Skip this check when there's no 1171 * EEPROM fitted, since in that case it will always1172 * fail.1285 * chip containing the Ethernet address fitted, since 1286 * in that case it will always fail. 1173 1287 */ 1174 if ((sc->bge_flags & BGE_FLAG_E EPROM) &&1288 if ((sc->bge_flags & BGE_FLAG_EADDR) && 1175 1289 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1176 1290 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1177 1291 return (ENODEV); … … 1271 1385 /* Set the timer prescaler (always 66Mhz) */ 1272 1386 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1273 1387 1388 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1389 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1390 DELAY(40); /* XXX */ 1391 1392 /* Put PHY into ready state */ 1393 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1394 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1395 DELAY(40); 1396 } 1397 1274 1398 return (0); 1275 1399 } 1276 1400 … … 1308 1432 } 1309 1433 1310 1434 /* Configure mbuf pool watermarks */ 1311 if (!(BGE_IS_5705_PLUS(sc))) { 1435 if (!BGE_IS_5705_PLUS(sc)) { 1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1438 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1439 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1312 1440 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1442 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1443 } else { 1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1313 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1314 } else { 1315 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1317 1447 } 1318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);1319 1448 1320 1449 /* Configure DMA resource watermarks */ 1321 1450 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); … … 1421 1550 * requirement of all 575x family chips. The Linux driver sets 1422 1551 * the lower threshold for all 5705 family chips as well, but there 1423 1552 * are reports that it might not need to be so strict. 1553 * 1554 * XXX Linux does some extra fiddling here for the 5906 parts as 1555 * well. 1424 1556 */ 1425 1557 if (BGE_IS_5705_PLUS(sc)) 1426 1558 val = 8; … … 1462 1594 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1463 1595 BGE_RCB_FLAG_RING_DISABLED)); 1464 1596 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1465 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +1597 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1466 1598 (i * (sizeof(uint64_t))), 0); 1467 1599 vrcb += sizeof(struct bge_rcb); 1468 1600 } 1469 1601 1470 1602 /* Initialize RX ring indexes */ 1471 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);1472 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);1473 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);1603 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1604 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1605 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1474 1606 1475 1607 /* 1476 1608 * Set up RX return ring 0 … … 1679 1811 const struct bge_revision * 1680 1812 bge_lookup_rev(uint32_t chipid) 1681 1813 { 1682 1814 const struct bge_revision *br; 1683 1815 1684 1816 for (br = bge_revisions; br->br_name != NULL; br++) { 1685 1817 if (br->br_chipid == chipid) … … 1697 1829 const struct bge_vendor * 1698 1830 bge_lookup_vendor(uint16_t vid) 1699 1831 { 1700 1832 const struct bge_vendor *v; 1701 1833 1702 1834 for (v = bge_vendors; v->v_name != NULL; v++) 1703 1835 if (v->v_id == vid) … … 1730 1862 while(t->bge_vid != 0) { 1731 1863 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1732 1864 char model[64], buf[96]; 1733 1734 1865 const struct bge_revision *br; 1866 const struct bge_vendor *v; 1735 1867 uint32_t id; 1736 1868 1737 1869 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & … … 1740 1872 v = bge_lookup_vendor(vid); 1741 1873 { 1742 1874 #if __FreeBSD_version > 700024 1743 1875 const char *pname; 1744 1876 1745 1877 if (pci_get_vpd_ident(dev, &pname) == 0) 1746 1878 snprintf(model, 64, "%s", pname); … … 1892 2024 /* 1893 2025 * Allocate the parent bus DMA tag appropriate for PCI. 1894 2026 */ 1895 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1896 1, 0, /* alignment, boundary */ 1897 BUS_SPACE_MAXADDR, /* lowaddr */ 1898 BUS_SPACE_MAXADDR, /* highaddr */ 1899 NULL, NULL, /* filter, filterarg */ 1900 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1901 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1902 0, /* flags */ 1903 NULL, NULL, /* lockfunc, lockarg */ 1904 &sc->bge_cdata.bge_parent_tag); 2027 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2028 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2029 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2030 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 1905 2031 1906 2032 if (error != 0) { 1907 2033 device_printf(sc->bge_dev, … … 1910 2036 } 1911 2037 1912 2038 /* 1913 * Create tag for RXmbufs.2039 * Create tag for mbufs. 1914 2040 */ 1915 2041 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1916 2042 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, … … 2229 2355 { 2230 2356 struct ifnet *ifp; 2231 2357 struct bge_softc *sc; 2232 uint32_t hwcfg = 0; 2233 uint32_t mac_tmp = 0; 2358 uint32_t hwcfg = 0, misccfg; 2234 2359 u_char eaddr[ETHER_ADDR_LEN]; 2235 2360 int error, reg, rid, trys; 2236 2361 2237 2362 sc = device_get_softc(dev); 2238 2363 sc->bge_dev = dev; 2364 sc->transmitting = 0; 2239 2365 2240 2366 /* 2241 2367 * Map control/status registers. … … 2263 2389 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2264 2390 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2265 2391 2266 if (bge_has_eeprom(sc)) 2267 sc->bge_flags |= BGE_FLAG_EEPROM; 2392 /* 2393 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2394 * 5705 A0 and A1 chips. 2395 */ 2396 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2397 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2398 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2399 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2400 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2268 2401 2402 if (bge_has_eaddr(sc)) 2403 sc->bge_flags |= BGE_FLAG_EADDR; 2404 2269 2405 /* Save chipset family. */ 2270 2406 switch (sc->bge_asicrev) { 2271 2407 case BGE_ASICREV_BCM5700: … … 2283 2419 case BGE_ASICREV_BCM5752: 2284 2420 case BGE_ASICREV_BCM5755: 2285 2421 case BGE_ASICREV_BCM5787: 2422 case BGE_ASICREV_BCM5906: 2286 2423 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2287 2424 /* FALLTHRU */ 2288 2425 case BGE_ASICREV_BCM5705: … … 2302 2439 if (BGE_IS_5705_PLUS(sc) && 2303 2440 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2304 2441 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2305 sc->bge_asicrev == BGE_ASICREV_BCM5787) 2442 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2443 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2306 2444 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2307 else2445 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2308 2446 sc->bge_flags |= BGE_FLAG_BER_BUG; 2309 2447 } 2310 2448 2449 2311 2450 /* 2451 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2452 * but I do not know the DEVICEID for the 5788M. 2453 */ 2454 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2455 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2456 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2457 sc->bge_flags |= BGE_FLAG_5788; 2458 2459 /* 2312 2460 * Check if this is a PCI-X or PCI Express device. 2313 2461 */ 2314 2462 #if __FreeBSD_version > 602101 … … 2414 2562 goto fail; 2415 2563 } 2416 2564 2417 #ifdef __sparc64__ 2418 if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0) 2419 OF_getetheraddr(dev, eaddr); 2420 else 2421 #endif 2422 { 2423 mac_tmp = bge_readmem_ind(sc, 0x0C14); 2424 if ((mac_tmp >> 16) == 0x484B) { 2425 eaddr[0] = (u_char)(mac_tmp >> 8); 2426 eaddr[1] = (u_char)mac_tmp; 2427 mac_tmp = bge_readmem_ind(sc, 0x0C18); 2428 eaddr[2] = (u_char)(mac_tmp >> 24); 2429 eaddr[3] = (u_char)(mac_tmp >> 16); 2430 eaddr[4] = (u_char)(mac_tmp >> 8); 2431 eaddr[5] = (u_char)mac_tmp; 2432 } else if (bge_read_eeprom(sc, eaddr, 2433 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2565 error = bge_get_eaddr(sc, eaddr); 2566 if (error) { 2434 2567 device_printf(sc->bge_dev, 2435 2568 "failed to read station address\n"); 2436 2569 error = ENXIO; 2437 2570 goto fail; 2438 2571 } 2439 }2440 2572 2441 2573 /* 5705 limits RX return ring to 512 entries. */ 2442 2574 if (BGE_IS_5705_PLUS(sc)) … … 2507 2639 */ 2508 2640 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2509 2641 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2510 else if (sc->bge_flags & BGE_FLAG_EEPROM) { 2642 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2643 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2511 2644 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2512 2645 sizeof(hwcfg))) { 2513 2646 device_printf(sc->bge_dev, "failed to read EEPROM\n"); … … 2682 2815 bge_reset(struct bge_softc *sc) 2683 2816 { 2684 2817 device_t dev; 2685 uint32_t cachesize, command, pcistate, reset ;2818 uint32_t cachesize, command, pcistate, reset, val; 2686 2819 void (*write_op)(struct bge_softc *, int, int); 2687 int i , val = 0;2820 int i; 2688 2821 2689 2822 dev = sc->bge_dev; 2690 2823 2691 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { 2824 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2825 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2692 2826 if (sc->bge_flags & BGE_FLAG_PCIE) 2693 2827 write_op = bge_writemem_direct; 2694 2828 else … … 2744 2878 /* Issue global reset */ 2745 2879 write_op(sc, BGE_MISC_CFG, reset); 2746 2880 2881 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2882 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2883 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2884 val | BGE_VCPU_STATUS_DRV_RESET); 2885 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2886 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2887 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2888 } 2889 2747 2890 DELAY(1000); 2748 2891 2749 2892 /* XXX: Broadcom Linux driver. */ 2750 2893 if (sc->bge_flags & BGE_FLAG_PCIE) { 2751 2894 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2752 uint32_t v;2753 2754 2895 DELAY(500000); /* wait for link training to complete */ 2755 v = pci_read_config(dev, 0xC4, 4);2756 pci_write_config(dev, 0xC4, v | (1 << 15), 4);2896 val = pci_read_config(dev, 0xC4, 4); 2897 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 2757 2898 } 2758 2899 /* 2759 2900 * Set PCIE max payload size to 128 bytes and clear error … … 2772 2913 2773 2914 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2774 2915 if (BGE_IS_5714_FAMILY(sc)) { 2775 uint32_t val;2776 2777 2916 /* This chip disables MSI on reset. */ 2778 2917 if (sc->bge_flags & BGE_FLAG_MSI) { 2779 2918 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); … … 2788 2927 } else 2789 2928 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2790 2929 2930 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2931 for (i = 0; i < BGE_TIMEOUT; i++) { 2932 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2933 if (val & BGE_VCPU_STATUS_INIT_DONE) 2934 break; 2935 DELAY(100); 2936 } 2937 if (i == BGE_TIMEOUT) { 2938 device_printf(sc->bge_dev, "reset timed out\n"); 2939 return (1); 2940 } 2941 } else { 2791 2942 /* 2792 2943 * Poll until we see the 1's complement of the magic number. 2793 2944 * This indicates that the firmware initialization is complete. 2794 * We expect this to fail if no EEPROM is fitted though. 2945 * We expect this to fail if no chip containing the Ethernet 2946 * address is fitted though. 2795 2947 */ 2796 2948 for (i = 0; i < BGE_TIMEOUT; i++) { 2797 2949 DELAY(10); … … 2800 2952 break; 2801 2953 } 2802 2954 2803 if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT)2955 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 2804 2956 device_printf(sc->bge_dev, "firmware handshake timed out, " 2805 2957 "found 0x%08x\n", val); 2958 } 2806 2959 2807 2960 /* 2808 2961 * XXX Wait for the value of the PCISTATE register to … … 2840 2993 */ 2841 2994 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2842 2995 sc->bge_flags & BGE_FLAG_TBI) { 2843 uint32_t serdescfg; 2844 2845 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2846 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2847 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2996 val = CSR_READ_4(sc, BGE_SERDES_CFG); 2997 val = (val & ~0xFFF) | 0x880; 2998 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 2848 2999 } 2849 3000 2850 3001 /* XXX: Broadcom Linux driver. */ 2851 3002 if (sc->bge_flags & BGE_FLAG_PCIE && 2852 3003 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2853 uint32_t v; 2854 2855 v = CSR_READ_4(sc, 0x7C00); 2856 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 3004 val = CSR_READ_4(sc, 0x7C00); 3005 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 2857 3006 } 2858 3007 DELAY(10000); 2859 3008 … … 2882 3031 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 2883 3032 return; 2884 3033 3034 dprintf("bge_rxeof\n"); 3035 2885 3036 ifp = sc->bge_ifp; 2886 3037 2887 3038 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, … … 3022 3173 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3023 3174 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3024 3175 3025 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);3176 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3026 3177 if (stdcnt) 3027 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);3178 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3028 3179 if (jumbocnt) 3029 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);3180 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3030 3181 #ifdef notyet 3031 3182 /* 3032 3183 * This register wraps very quickly under heavy packet drops. … … 3050 3201 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3051 3202 return; 3052 3203 3204 dprintf("bge_txeof\n"); 3205 3053 3206 ifp = sc->bge_ifp; 3054 3207 3055 3208 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, … … 3137 3290 3138 3291 sc = xsc; 3139 3292 3293 dprintf("bge_intr, sc->bge_intr_status=0x%x\n", sc->bge_intr_status); 3294 3140 3295 BGE_LOCK(sc); 3141 3296 3142 3297 ifp = sc->bge_ifp; … … 3168 3323 * the status check). So toggling would probably be a pessimization 3169 3324 * even with MSI. It would only be needed for using a task queue. 3170 3325 */ 3171 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3326 #ifndef __HAIKU__ 3327 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3328 #endif 3172 3329 3173 3330 /* 3174 3331 * Do the mandatory PCI flush as well as get the link status. 3175 3332 */ 3176 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3333 #ifndef __HAIKU__ 3334 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3335 #else 3336 /* Get the statusword as saved in __haiku_disable_interrupts 3337 * and clear the saved value */ 3338 statusword = atomic_and((int32 *)&sc->bge_intr_status, 0) & BGE_MACSTAT_LINK_CHANGED; 3339 #endif 3177 3340 3178 3341 /* Make sure the descriptor ring indexes are coherent. */ 3179 3342 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, … … 3181 3344 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3182 3345 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3183 3346 3184 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3185 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3186 statusword || sc->bge_link_evt) 3187 bge_link_upd(sc); 3347 /* TODO: bge_link_upd is probably not correct with interrupt changes 3348 * May need to also use the saved statusword... */ 3349 //QQQ 3350 //if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3351 // sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3352 // statusword || sc->bge_link_evt) 3353 // bge_link_upd(sc); 3188 3354 3189 3355 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3190 3356 /* Check RX return ring producer/consumer. */ … … 3255 3421 #endif 3256 3422 { 3257 3423 sc->bge_link_evt++; 3424 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3425 sc->bge_flags & BGE_FLAG_5788) 3258 3426 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3427 else 3428 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3259 3429 } 3260 3430 } 3261 3431 … … 3390 3560 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3391 3561 &nsegs, BUS_DMA_NOWAIT); 3392 3562 if (error == EFBIG) { 3393 m = m_defrag(m, M_DONTWAIT); 3563 //m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3564 panic("m_collapse not implemented"); 3394 3565 if (m == NULL) { 3395 3566 m_freem(*m_head); 3396 3567 *m_head = NULL; … … 3482 3653 3483 3654 sc = ifp->if_softc; 3484 3655 3485 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3656 //if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3657 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3486 3658 return; 3487 3659 3488 3660 prodidx = sc->bge_tx_prodidx; … … 3544 3716 /* No packets were dequeued. */ 3545 3717 return; 3546 3718 3719 sc -> transmitting = 1; 3547 3720 /* Transmit. */ 3548 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);3721 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3549 3722 /* 5700 b2 errata */ 3550 3723 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3551 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);3724 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3552 3725 3553 3726 sc->bge_tx_prodidx = prodidx; 3554 3727 … … 3675 3848 if (ifp->if_capenable & IFCAP_POLLING) { 3676 3849 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3677 3850 BGE_PCIMISCCTL_MASK_PCI_INTR); 3678 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);3851 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3679 3852 } else 3680 3853 #endif 3681 3854 3682 3855 /* Enable host interrupts. */ 3856 //QQQ 3683 3857 { 3684 3858 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3685 3859 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3686 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);3860 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3687 3861 } 3688 3862 3689 3863 bge_ifmedia_upd_locked(ifp); … … 3783 3957 } 3784 3958 mii_mediachg(mii); 3785 3959 3960 /* 3961 * Force an interrupt so that we will call bge_link_upd 3962 * if needed and clear any pending link state attention. 3963 * Without this we are not getting any further interrupts 3964 * for link state changes and thus will not UP the link and 3965 * not be able to send in bge_start_locked. The only 3966 * way to get things working was to receive a packet and 3967 * get an RX intr. 3968 * bge_tick should help for fiber cards and we might not 3969 * need to do this here if BGE_FLAG_TBI is set but as 3970 * we poll for fiber anyway it should not harm. 3971 */ 3972 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3973 sc->bge_flags & BGE_FLAG_5788) 3974 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3975 else 3976 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3977 3786 3978 return (0); 3787 3979 } 3788 3980 … … 3906 4098 BGE_LOCK(sc); 3907 4099 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3908 4100 BGE_PCIMISCCTL_MASK_PCI_INTR); 3909 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);4101 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3910 4102 ifp->if_capenable |= IFCAP_POLLING; 3911 4103 BGE_UNLOCK(sc); 3912 4104 } else { … … 3915 4107 BGE_LOCK(sc); 3916 4108 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 3917 4109 BGE_PCIMISCCTL_MASK_PCI_INTR); 3918 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);4110 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3919 4111 ifp->if_capenable &= ~IFCAP_POLLING; 3920 4112 BGE_UNLOCK(sc); 3921 4113 } … … 4040 4232 4041 4233 /* Disable host interrupts. */ 4042 4234 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4043 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);4235 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4044 4236 4045 4237 /* 4046 4238 * Tell firmware we're shutting down. … … 4083 4275 */ 4084 4276 if (mii != NULL) { 4085 4277 ifm = mii->mii_media.ifm_cur; 4278 if (ifm == NULL) 4279 { 4280 panic("bge_stop: ifm == NULL"); 4281 return ; 4282 } 4086 4283 mtmp = ifm->ifm_media; 4087 4284 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4088 4285 mii_mediachg(mii); … … 4150 4347 return (0); 4151 4348 } 4152 4349 4153 staticvoid4350 /*static*/ void 4154 4351 bge_link_upd(struct bge_softc *sc) 4155 4352 { 4156 4353 struct mii_data *mii; 4157 4354 uint32_t link, status; 4158 4355 4356 4159 4357 BGE_LOCK_ASSERT(sc); 4160 4358 4161 4359 /* Clear 'pending link event' flag. */ … … 4232 4430 * in status word always set. Workaround this bug by reading 4233 4431 * PHY link status directly. 4234 4432 */ 4433 #define lnDbg do {printf("%s: %s: %d\n", __FILE__,__func__, __LINE__); } while(0) 4434 lnDbg; 4235 4435 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4236 4436 4237 4437 if (link != sc->bge_link || 4238 4438 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4439 lnDbg; 4239 4440 mii = device_get_softc(sc->bge_miibus); 4240 4441 mii_pollstat(mii); 4241 4442 if (!sc->bge_link && 4242 4443 mii->mii_media_status & IFM_ACTIVE && 4243 4444 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4445 lnDbg; 4244 4446 sc->bge_link++; 4245 4447 if (bootverbose) 4246 4448 if_printf(sc->bge_ifp, "link UP\n"); … … 4263 4465 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4264 4466 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4265 4467 BGE_MACSTAT_LINK_CHANGED); 4468 4469 dprintf("bge_link_upd, sc->bge_link=0x%x\n", sc->bge_link); 4266 4470 } 4267 4471 4268 4472 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ … … 4295 4499 4296 4500 #endif 4297 4501 4502 if (BGE_IS_5705_PLUS(sc)) 4503 return; 4504 4298 4505 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4299 4506 NULL, "BGE Statistics"); 4300 4507 schildren = children = SYSCTL_CHILDREN(tree); … … 4417 4624 { 4418 4625 struct bge_softc *sc; 4419 4626 uint32_t result; 4420 int base,offset;4627 int offset; 4421 4628 4422 4629 sc = (struct bge_softc *)arg1; 4423 4630 offset = arg2; 4424 if (BGE_IS_5705_PLUS(sc)) 4425 base = BGE_MAC_STATS; 4426 else 4427 base = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4428 result = CSR_READ_4(sc, base + offset + offsetof(bge_hostaddr, 4429 bge_addr_lo)); 4631 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4632 offsetof(bge_hostaddr, bge_addr_lo)); 4430 4633 return (sysctl_handle_int(oidp, &result, 0, req)); 4431 4634 } 4432 4635 … … 4537 4740 return (error); 4538 4741 } 4539 4742 #endif 4743 4744 static int 4745 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4746 { 4747 4748 if (sc->bge_flags & BGE_FLAG_EADDR) 4749 return (1); 4750 4751 #ifdef __sparc64__ 4752 OF_getetheraddr(sc->bge_dev, ether_addr); 4753 return (0); 4754 #endif 4755 return (1); 4756 } 4757 4758 static int 4759 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4760 { 4761 uint32_t mac_addr; 4762 4763 mac_addr = bge_readmem_ind(sc, 0x0c14); 4764 if ((mac_addr >> 16) == 0x484b) { 4765 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4766 ether_addr[1] = (uint8_t)mac_addr; 4767 mac_addr = bge_readmem_ind(sc, 0x0c18); 4768 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4769 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4770 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4771 ether_addr[5] = (uint8_t)mac_addr; 4772 return (0); 4773 } 4774 return (1); 4775 } 4776 4777 static int 4778 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4779 { 4780 int mac_offset = BGE_EE_MAC_OFFSET; 4781 4782 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4783 mac_offset = BGE_EE_MAC_OFFSET_5906; 4784 4785 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4786 ETHER_ADDR_LEN)); 4787 } 4788 4789 static int 4790 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4791 { 4792 4793 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4794 return (1); 4795 4796 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4797 ETHER_ADDR_LEN)); 4798 } 4799 4800 static int 4801 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4802 { 4803 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4804 /* NOTE: Order is critical */ 4805 bge_get_eaddr_fw, 4806 bge_get_eaddr_mem, 4807 bge_get_eaddr_nvram, 4808 bge_get_eaddr_eeprom, 4809 NULL 4810 }; 4811 const bge_eaddr_fcn_t *func; 4812 4813 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4814 if ((*func)(sc, eaddr) == 0) 4815 break; 4816 } 4817 return (*func == NULL ? ENXIO : 0); 4818 } -
src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/glue.c
5 5 6 6 7 7 #include <sys/bus.h> 8 #include "if_bgereg.h" 8 9 9 10 10 11 HAIKU_FBSD_DRIVER_GLUE(broadcom570x, bge, pci); … … 25 26 return __haiku_probe_miibus(dev, drivers); 26 27 } 27 28 29 int 30 __haiku_disable_interrupts(device_t dev) 31 { 32 struct bge_softc *sc = device_get_softc(dev); 33 34 // Obtain the status and return 0 if the bge did not set the intr 35 u_int32_t status = CSR_READ_4(sc, BGE_MAC_STS); 36 // status & 0x1000 for media change, sc->transmitting if sending a packet 37 // use BGE_PCI_PCISTATE to check interrupt source like in the Linux driver 38 if ( ((status & 0x1000)==0)&&(sc->transmitting==0) && ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE,4) & BGE_PCISTATE_INTR_STATE) != 0)) { 39 return 0; 40 } 41 sc->transmitting=0; 42 43 // Clear the interrupt, the bge intr handler will take care of it 44 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 45 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 46 47 // save the status for the interrupt handler 48 atomic_or((int32 *)&sc->bge_intr_status, status); 49 // *** 50 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 51 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 52 (status&0x1000) || sc->bge_link_evt) 53 bge_link_upd(sc); 54 // *** 55 return 1; 56 } 57 58 59 void 60 __haiku_reenable_interrupts(device_t dev) 61 { 62 struct bge_softc *sc = device_get_softc(dev); 63 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 64 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 65 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 66 } -
src/libs/compat/freebsd_network/compat/sys/mbuf.h
82 82 83 83 #define M_BCAST 0x00000200 84 84 #define M_MCAST 0x00000400 85 #define M_FRAG 0x00000800 86 #define M_FIRSTFRAG 0x00001000 87 #define M_LASTFRAG 0x00002000 85 88 #define M_VLANTAG 0x00010000 86 89 87 90 #define CSUM_IP 0x0001 … … 125 128 struct mbuf *m_get(int how, short type); 126 129 struct mbuf *m_gethdr(int how, short type); 127 130 void m_clget(struct mbuf *m, int how); 131 void * m_cljget(struct mbuf *m, int how, int size); 128 132 129 133 void m_extadd(struct mbuf *m, caddr_t buffer, u_int size, 130 134 void (*freeHook)(void *, void *), void *args, int flags, int type); -
src/libs/compat/freebsd_network/fbsd_mii_physubr.c
510 510 } 511 511 512 512 if (sc->mii_capabilities & BMSR_ANEG) { 513 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 514 MII_NMEDIA); /* intentionally invalid index */ 513 dprintf("don't know how to handle sc->mii_capabilities & BMSR_ANEG\n"); 514 //ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 515 //MII_NMEDIA); /* intentionally invalid index */ 515 516 PRINT("auto"); 516 517 } 517 518 #undef ADD -
src/libs/compat/freebsd_network/mbuf.c
150 150 construct_ext_mbuf(m, how); 151 151 } 152 152 153 /* 154 * Comment from the freebsd (mbuf.h): 155 * m_cljget() is different from m_clget() as it can allocate clusters without 156 * attaching them to an mbuf. In that case the return value is the pointer 157 * to the cluster of the requested size. If an mbuf was specified, it gets 158 * the cluster attached to it and the return value can be safely ignored. 159 * For size it takes MCLBYTES, MJUMPAGESIZE, MJUM9BYTES, MJUM16BYTES. 160 */ 161 void * 162 m_cljget(struct mbuf *m, int how, int size) 163 { 164 // TODO: implement this 165 panic("m_cljget not yet implemented"); 166 return (void *) NULL; 167 168 /* 169 // This is the freebsd code 170 uma_zone_t zone; 171 172 if (m && m->m_flags & M_EXT) 173 printf("%s: %p mbuf already has cluster\n", __func__, m); 174 if (m != NULL) 175 m->m_ext.ext_buf = NULL; 176 177 zone = m_getzone(size); 178 return (uma_zalloc_arg(zone, m, how)); 179 */ 180 } 181 182 153 183 154 184 void 155 185 m_freem(struct mbuf *mb)
