Ticket #1590: if_bge.update.diff
File if_bge.update.diff, 27.6 KB (added by , 16 years ago) |
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if_bge.
old new 32 32 */ 33 33 34 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198 2007/09/30 11:05:14 mariusExp $");35 __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198.2.9 2008/06/27 03:24:54 jhb Exp $"); 36 36 37 37 /* 38 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. … … 169 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 172 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 173 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 174 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, … … 195 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 196 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 197 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 198 201 199 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 200 203 … … 205 208 206 209 static const struct bge_vendor { 207 210 uint16_t v_id; 208 211 const char *v_name; 209 212 } bge_vendors[] = { 210 213 { ALTEON_VENDORID, "Alteon" }, 211 214 { ALTIMA_VENDORID, "Altima" }, … … 219 222 220 223 static const struct bge_revision { 221 224 uint32_t br_chipid; 222 225 const char *br_name; 223 226 } bge_revisions[] = { 224 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 225 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, … … 267 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 268 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 269 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 270 274 /* 5754 and 5787 share the same ASIC ID */ 271 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 272 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 273 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 274 280 275 281 { 0, NULL } 276 282 }; … … 293 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 294 300 /* 5754 and 5787 share the same ASIC ID */ 295 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 296 303 297 304 { 0, NULL } 298 305 }; … … 305 312 306 313 const struct bge_revision * bge_lookup_rev(uint32_t); 307 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 308 318 static int bge_probe(device_t); 309 319 static int bge_attach(device_t); 310 320 static int bge_detach(device_t); … … 315 325 static int bge_dma_alloc(device_t); 316 326 static void bge_dma_free(struct bge_softc *); 317 327 328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 333 318 334 static void bge_txeof(struct bge_softc *); 319 335 static void bge_rxeof(struct bge_softc *); 320 336 … … 337 353 static int bge_ifmedia_upd(struct ifnet *); 338 354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 339 355 356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 358 340 359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 341 360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 342 361 … … 356 375 static int bge_chipinit(struct bge_softc *); 357 376 static int bge_blockinit(struct bge_softc *); 358 377 359 static int bge_has_e eprom(struct bge_softc *);378 static int bge_has_eaddr(struct bge_softc *); 360 379 static uint32_t bge_readmem_ind(struct bge_softc *, int); 361 380 static void bge_writemem_ind(struct bge_softc *, int, int); 381 static void bge_writembx(struct bge_softc *, int, int); 362 382 #ifdef notdef 363 383 static uint32_t bge_readreg_ind(struct bge_softc *, int); 364 384 #endif … … 425 445 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 426 446 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 427 447 428 static int bge_allow_asf = 1;448 static int bge_allow_asf = 0; 429 449 430 450 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 431 451 … … 440 460 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 441 461 442 462 static int 443 bge_has_e eprom(struct bge_softc *sc)463 bge_has_eaddr(struct bge_softc *sc) 444 464 { 445 465 #ifdef __sparc64__ 446 466 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; … … 452 472 /* 453 473 * The on-board BGEs found in sun4u machines aren't fitted with 454 474 * an EEPROM which means that we have to obtain the MAC address 455 * via OFW and that some tests will always fail. We distinguish475 * via OFW and that some tests will always fail. We distinguish 456 476 * such BGEs by the subvendor ID, which also has to be obtained 457 477 * from OFW instead of the PCI configuration space as the latter 458 478 * indicates Broadcom as the subvendor of the netboot interface. … … 533 553 CSR_WRITE_4(sc, off, val); 534 554 } 535 555 556 static void 557 bge_writembx(struct bge_softc *sc, int off, int val) 558 { 559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 560 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 561 562 CSR_WRITE_4(sc, off, val); 563 } 564 536 565 /* 537 566 * Map a single buffer address. 538 567 */ … … 555 584 ctx->bge_busaddr = segs->ds_addr; 556 585 } 557 586 587 static uint8_t 588 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 589 { 590 uint32_t access, byte = 0; 591 int i; 592 593 /* Lock. */ 594 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 595 for (i = 0; i < 8000; i++) { 596 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 597 break; 598 DELAY(20); 599 } 600 if (i == 8000) 601 return (1); 602 603 /* Enable access. */ 604 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 605 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 606 607 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 608 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 609 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 610 DELAY(10); 611 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 612 DELAY(10); 613 break; 614 } 615 } 616 617 if (i == BGE_TIMEOUT * 10) { 618 if_printf(sc->bge_ifp, "nvram read timed out\n"); 619 return (1); 620 } 621 622 /* Get result. */ 623 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 624 625 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 626 627 /* Disable access. */ 628 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 629 630 /* Unlock. */ 631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 632 CSR_READ_4(sc, BGE_NVRAM_SWARB); 633 634 return (0); 635 } 636 637 /* 638 * Read a sequence of bytes from NVRAM. 639 */ 640 static int 641 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 642 { 643 int err = 0, i; 644 uint8_t byte = 0; 645 646 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 647 return (1); 648 649 for (i = 0; i < cnt; i++) { 650 err = bge_nvram_getbyte(sc, off + i, &byte); 651 if (err) 652 break; 653 *(dest + i) = byte; 654 } 655 656 return (err ? 1 : 0); 657 } 658 558 659 /* 559 660 * Read a byte of data stored in the EEPROM at address 'addr.' The 560 661 * BCM570x supports both the traditional bitbang interface and an … … 659 760 } 660 761 661 762 if (i == BGE_TIMEOUT) { 662 device_printf(sc->bge_dev, "PHY read timed out\n"); 763 device_printf(sc->bge_dev, 764 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 765 phy, reg, val); 663 766 val = 0; 664 767 goto done; 665 768 } 666 769 770 DELAY(5); 667 771 val = CSR_READ_4(sc, BGE_MI_COMM); 668 772 669 773 done: … … 687 791 688 792 sc = device_get_softc(dev); 689 793 794 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 795 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 796 return(0); 797 690 798 /* Reading with autopolling on may trigger PCI errors */ 691 799 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 692 800 if (autopoll & BGE_MIMODE_AUTOPOLL) { … … 699 807 700 808 for (i = 0; i < BGE_TIMEOUT; i++) { 701 809 DELAY(10); 702 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 810 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 811 DELAY(5); 812 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 703 813 break; 814 } 704 815 } 705 816 706 817 if (i == BGE_TIMEOUT) { 707 device_printf(sc->bge_dev, "PHY write timed out\n"); 818 device_printf(sc->bge_dev, 819 "PHY write timed out (phy %d, reg %d, val %d)\n", 820 phy, reg, val); 708 821 return (0); 709 822 } 710 823 … … 887 1000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 1001 889 1002 sc->bge_std = i - 1; 890 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);1003 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 891 1004 892 1005 return (0); 893 1006 } … … 934 1047 BGE_RCB_FLAG_USE_EXT_RX_BD); 935 1048 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 936 1049 937 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);1050 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 938 1051 939 1052 return (0); 940 1053 } … … 990 1103 991 1104 /* Initialize transmit producer index for host-memory send ring. */ 992 1105 sc->bge_tx_prodidx = 0; 993 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 994 1107 995 1108 /* 5700 b2 errata */ 996 1109 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 997 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);1110 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 998 1111 999 1112 /* NIC-memory send ring not used; initialize to zero. */ 1000 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1001 1114 /* 5700 b2 errata */ 1002 1115 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1003 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);1116 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1004 1117 1005 1118 return (0); 1006 1119 } … … 1168 1281 /* 1169 1282 * Check the 'ROM failed' bit on the RX CPU to see if 1170 1283 * self-tests passed. Skip this check when there's no 1171 * EEPROM fitted, since in that case it will always1172 * fail.1284 * chip containing the Ethernet address fitted, since 1285 * in that case it will always fail. 1173 1286 */ 1174 if ((sc->bge_flags & BGE_FLAG_E EPROM) &&1287 if ((sc->bge_flags & BGE_FLAG_EADDR) && 1175 1288 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1176 1289 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1177 1290 return (ENODEV); … … 1271 1384 /* Set the timer prescaler (always 66Mhz) */ 1272 1385 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1273 1386 1387 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1388 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1389 DELAY(40); /* XXX */ 1390 1391 /* Put PHY into ready state */ 1392 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1393 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1394 DELAY(40); 1395 } 1396 1274 1397 return (0); 1275 1398 } 1276 1399 … … 1308 1431 } 1309 1432 1310 1433 /* Configure mbuf pool watermarks */ 1311 if (!(BGE_IS_5705_PLUS(sc))) { 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1314 } else { 1434 if (!BGE_IS_5705_PLUS(sc)) { 1315 1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1316 1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1438 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1440 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1442 } else { 1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1317 1446 } 1318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);1319 1447 1320 1448 /* Configure DMA resource watermarks */ 1321 1449 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); … … 1421 1549 * requirement of all 575x family chips. The Linux driver sets 1422 1550 * the lower threshold for all 5705 family chips as well, but there 1423 1551 * are reports that it might not need to be so strict. 1552 * 1553 * XXX Linux does some extra fiddling here for the 5906 parts as 1554 * well. 1424 1555 */ 1425 1556 if (BGE_IS_5705_PLUS(sc)) 1426 1557 val = 8; … … 1462 1593 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1463 1594 BGE_RCB_FLAG_RING_DISABLED)); 1464 1595 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1465 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +1596 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1466 1597 (i * (sizeof(uint64_t))), 0); 1467 1598 vrcb += sizeof(struct bge_rcb); 1468 1599 } 1469 1600 1470 1601 /* Initialize RX ring indexes */ 1471 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);1472 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);1473 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);1602 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1603 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1604 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1474 1605 1475 1606 /* 1476 1607 * Set up RX return ring 0 … … 1679 1810 const struct bge_revision * 1680 1811 bge_lookup_rev(uint32_t chipid) 1681 1812 { 1682 1813 const struct bge_revision *br; 1683 1814 1684 1815 for (br = bge_revisions; br->br_name != NULL; br++) { 1685 1816 if (br->br_chipid == chipid) … … 1697 1828 const struct bge_vendor * 1698 1829 bge_lookup_vendor(uint16_t vid) 1699 1830 { 1700 1831 const struct bge_vendor *v; 1701 1832 1702 1833 for (v = bge_vendors; v->v_name != NULL; v++) 1703 1834 if (v->v_id == vid) … … 1730 1861 while(t->bge_vid != 0) { 1731 1862 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1732 1863 char model[64], buf[96]; 1733 1734 1864 const struct bge_revision *br; 1865 const struct bge_vendor *v; 1735 1866 uint32_t id; 1736 1867 1737 1868 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & … … 1740 1871 v = bge_lookup_vendor(vid); 1741 1872 { 1742 1873 #if __FreeBSD_version > 700024 1743 1874 const char *pname; 1744 1875 1745 1876 if (pci_get_vpd_ident(dev, &pname) == 0) 1746 1877 snprintf(model, 64, "%s", pname); … … 1892 2023 /* 1893 2024 * Allocate the parent bus DMA tag appropriate for PCI. 1894 2025 */ 1895 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1896 1, 0, /* alignment, boundary */ 1897 BUS_SPACE_MAXADDR, /* lowaddr */ 1898 BUS_SPACE_MAXADDR, /* highaddr */ 1899 NULL, NULL, /* filter, filterarg */ 1900 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1901 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1902 0, /* flags */ 1903 NULL, NULL, /* lockfunc, lockarg */ 1904 &sc->bge_cdata.bge_parent_tag); 2026 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2027 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2028 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2029 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 1905 2030 1906 2031 if (error != 0) { 1907 2032 device_printf(sc->bge_dev, … … 1910 2035 } 1911 2036 1912 2037 /* 1913 * Create tag for RXmbufs.2038 * Create tag for mbufs. 1914 2039 */ 1915 2040 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1916 2041 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, … … 2229 2354 { 2230 2355 struct ifnet *ifp; 2231 2356 struct bge_softc *sc; 2232 uint32_t hwcfg = 0; 2233 uint32_t mac_tmp = 0; 2357 uint32_t hwcfg = 0, misccfg; 2234 2358 u_char eaddr[ETHER_ADDR_LEN]; 2235 2359 int error, reg, rid, trys; 2236 2360 … … 2263 2387 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2264 2388 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2265 2389 2266 if (bge_has_eeprom(sc)) 2267 sc->bge_flags |= BGE_FLAG_EEPROM; 2390 /* 2391 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2392 * 5705 A0 and A1 chips. 2393 */ 2394 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2395 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2396 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2397 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2398 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2399 2400 if (bge_has_eaddr(sc)) 2401 sc->bge_flags |= BGE_FLAG_EADDR; 2268 2402 2269 2403 /* Save chipset family. */ 2270 2404 switch (sc->bge_asicrev) { … … 2283 2417 case BGE_ASICREV_BCM5752: 2284 2418 case BGE_ASICREV_BCM5755: 2285 2419 case BGE_ASICREV_BCM5787: 2420 case BGE_ASICREV_BCM5906: 2286 2421 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2287 2422 /* FALLTHRU */ 2288 2423 case BGE_ASICREV_BCM5705: … … 2302 2437 if (BGE_IS_5705_PLUS(sc) && 2303 2438 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2304 2439 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2305 sc->bge_asicrev == BGE_ASICREV_BCM5787) 2306 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2307 else 2440 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2441 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2442 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2443 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2308 2444 sc->bge_flags |= BGE_FLAG_BER_BUG; 2309 2445 } 2310 2446 2447 2448 /* 2449 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2450 * but I do not know the DEVICEID for the 5788M. 2451 */ 2452 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2453 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2454 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2455 sc->bge_flags |= BGE_FLAG_5788; 2456 2311 2457 /* 2312 2458 * Check if this is a PCI-X or PCI Express device. 2313 2459 */ … … 2414 2560 goto fail; 2415 2561 } 2416 2562 2417 #ifdef __sparc64__ 2418 if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0) 2419 OF_getetheraddr(dev, eaddr); 2420 else 2421 #endif 2422 { 2423 mac_tmp = bge_readmem_ind(sc, 0x0C14); 2424 if ((mac_tmp >> 16) == 0x484B) { 2425 eaddr[0] = (u_char)(mac_tmp >> 8); 2426 eaddr[1] = (u_char)mac_tmp; 2427 mac_tmp = bge_readmem_ind(sc, 0x0C18); 2428 eaddr[2] = (u_char)(mac_tmp >> 24); 2429 eaddr[3] = (u_char)(mac_tmp >> 16); 2430 eaddr[4] = (u_char)(mac_tmp >> 8); 2431 eaddr[5] = (u_char)mac_tmp; 2432 } else if (bge_read_eeprom(sc, eaddr, 2433 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2434 device_printf(sc->bge_dev, 2435 "failed to read station address\n"); 2436 error = ENXIO; 2437 goto fail; 2438 } 2563 error = bge_get_eaddr(sc, eaddr); 2564 if (error) { 2565 device_printf(sc->bge_dev, 2566 "failed to read station address\n"); 2567 error = ENXIO; 2568 goto fail; 2439 2569 } 2440 2570 2441 2571 /* 5705 limits RX return ring to 512 entries. */ … … 2507 2637 */ 2508 2638 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2509 2639 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2510 else if (sc->bge_flags & BGE_FLAG_EEPROM) { 2640 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2641 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2511 2642 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2512 2643 sizeof(hwcfg))) { 2513 2644 device_printf(sc->bge_dev, "failed to read EEPROM\n"); … … 2682 2813 bge_reset(struct bge_softc *sc) 2683 2814 { 2684 2815 device_t dev; 2685 uint32_t cachesize, command, pcistate, reset ;2816 uint32_t cachesize, command, pcistate, reset, val; 2686 2817 void (*write_op)(struct bge_softc *, int, int); 2687 int i , val = 0;2818 int i; 2688 2819 2689 2820 dev = sc->bge_dev; 2690 2821 2691 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { 2822 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2823 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2692 2824 if (sc->bge_flags & BGE_FLAG_PCIE) 2693 2825 write_op = bge_writemem_direct; 2694 2826 else … … 2744 2876 /* Issue global reset */ 2745 2877 write_op(sc, BGE_MISC_CFG, reset); 2746 2878 2879 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2880 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2881 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2882 val | BGE_VCPU_STATUS_DRV_RESET); 2883 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2884 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2885 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2886 } 2887 2747 2888 DELAY(1000); 2748 2889 2749 2890 /* XXX: Broadcom Linux driver. */ 2750 2891 if (sc->bge_flags & BGE_FLAG_PCIE) { 2751 2892 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2752 uint32_t v;2753 2754 2893 DELAY(500000); /* wait for link training to complete */ 2755 v = pci_read_config(dev, 0xC4, 4);2756 pci_write_config(dev, 0xC4, v | (1 << 15), 4);2894 val = pci_read_config(dev, 0xC4, 4); 2895 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 2757 2896 } 2758 2897 /* 2759 2898 * Set PCIE max payload size to 128 bytes and clear error … … 2772 2911 2773 2912 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2774 2913 if (BGE_IS_5714_FAMILY(sc)) { 2775 uint32_t val;2776 2777 2914 /* This chip disables MSI on reset. */ 2778 2915 if (sc->bge_flags & BGE_FLAG_MSI) { 2779 2916 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); … … 2788 2925 } else 2789 2926 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2790 2927 2791 /* 2792 * Poll until we see the 1's complement of the magic number. 2793 * This indicates that the firmware initialization is complete. 2794 * We expect this to fail if no EEPROM is fitted though. 2795 */ 2796 for (i = 0; i < BGE_TIMEOUT; i++) { 2797 DELAY(10); 2798 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2799 if (val == ~BGE_MAGIC_NUMBER) 2800 break; 2801 } 2928 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2929 for (i = 0; i < BGE_TIMEOUT; i++) { 2930 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2931 if (val & BGE_VCPU_STATUS_INIT_DONE) 2932 break; 2933 DELAY(100); 2934 } 2935 if (i == BGE_TIMEOUT) { 2936 device_printf(sc->bge_dev, "reset timed out\n"); 2937 return (1); 2938 } 2939 } else { 2940 /* 2941 * Poll until we see the 1's complement of the magic number. 2942 * This indicates that the firmware initialization is complete. 2943 * We expect this to fail if no chip containing the Ethernet 2944 * address is fitted though. 2945 */ 2946 for (i = 0; i < BGE_TIMEOUT; i++) { 2947 DELAY(10); 2948 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2949 if (val == ~BGE_MAGIC_NUMBER) 2950 break; 2951 } 2802 2952 2803 if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT) 2804 device_printf(sc->bge_dev, "firmware handshake timed out, " 2805 "found 0x%08x\n", val); 2953 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 2954 device_printf(sc->bge_dev, "firmware handshake timed out, " 2955 "found 0x%08x\n", val); 2956 } 2806 2957 2807 2958 /* 2808 2959 * XXX Wait for the value of the PCISTATE register to … … 2840 2991 */ 2841 2992 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2842 2993 sc->bge_flags & BGE_FLAG_TBI) { 2843 uint32_t serdescfg; 2844 2845 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2846 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2847 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2994 val = CSR_READ_4(sc, BGE_SERDES_CFG); 2995 val = (val & ~0xFFF) | 0x880; 2996 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 2848 2997 } 2849 2998 2850 2999 /* XXX: Broadcom Linux driver. */ 2851 3000 if (sc->bge_flags & BGE_FLAG_PCIE && 2852 3001 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2853 uint32_t v; 2854 2855 v = CSR_READ_4(sc, 0x7C00); 2856 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 3002 val = CSR_READ_4(sc, 0x7C00); 3003 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 2857 3004 } 2858 3005 DELAY(10000); 2859 3006 … … 3022 3169 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3023 3170 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3024 3171 3025 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);3172 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3026 3173 if (stdcnt) 3027 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);3174 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3028 3175 if (jumbocnt) 3029 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);3176 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3030 3177 #ifdef notyet 3031 3178 /* 3032 3179 * This register wraps very quickly under heavy packet drops. … … 3168 3315 * the status check). So toggling would probably be a pessimization 3169 3316 * even with MSI. It would only be needed for using a task queue. 3170 3317 */ 3171 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);3318 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3172 3319 3173 3320 /* 3174 3321 * Do the mandatory PCI flush as well as get the link status. … … 3255 3402 #endif 3256 3403 { 3257 3404 sc->bge_link_evt++; 3258 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3405 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3406 sc->bge_flags & BGE_FLAG_5788) 3407 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3408 else 3409 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3259 3410 } 3260 3411 } 3261 3412 … … 3390 3541 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3391 3542 &nsegs, BUS_DMA_NOWAIT); 3392 3543 if (error == EFBIG) { 3393 m = m_ defrag(m, M_DONTWAIT);3544 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3394 3545 if (m == NULL) { 3395 3546 m_freem(*m_head); 3396 3547 *m_head = NULL; … … 3545 3696 return; 3546 3697 3547 3698 /* Transmit. */ 3548 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);3699 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3549 3700 /* 5700 b2 errata */ 3550 3701 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3551 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);3702 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3552 3703 3553 3704 sc->bge_tx_prodidx = prodidx; 3554 3705 … … 3675 3826 if (ifp->if_capenable & IFCAP_POLLING) { 3676 3827 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3677 3828 BGE_PCIMISCCTL_MASK_PCI_INTR); 3678 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);3829 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3679 3830 } else 3680 3831 #endif 3681 3832 … … 3683 3834 { 3684 3835 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3685 3836 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3686 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);3837 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3687 3838 } 3688 3839 3689 3840 bge_ifmedia_upd_locked(ifp); … … 3783 3934 } 3784 3935 mii_mediachg(mii); 3785 3936 3937 /* 3938 * Force an interrupt so that we will call bge_link_upd 3939 * if needed and clear any pending link state attention. 3940 * Without this we are not getting any further interrupts 3941 * for link state changes and thus will not UP the link and 3942 * not be able to send in bge_start_locked. The only 3943 * way to get things working was to receive a packet and 3944 * get an RX intr. 3945 * bge_tick should help for fiber cards and we might not 3946 * need to do this here if BGE_FLAG_TBI is set but as 3947 * we poll for fiber anyway it should not harm. 3948 */ 3949 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3950 sc->bge_flags & BGE_FLAG_5788) 3951 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3952 else 3953 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3954 3786 3955 return (0); 3787 3956 } 3788 3957 … … 3906 4075 BGE_LOCK(sc); 3907 4076 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3908 4077 BGE_PCIMISCCTL_MASK_PCI_INTR); 3909 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);4078 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3910 4079 ifp->if_capenable |= IFCAP_POLLING; 3911 4080 BGE_UNLOCK(sc); 3912 4081 } else { … … 3915 4084 BGE_LOCK(sc); 3916 4085 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 3917 4086 BGE_PCIMISCCTL_MASK_PCI_INTR); 3918 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);4087 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3919 4088 ifp->if_capenable &= ~IFCAP_POLLING; 3920 4089 BGE_UNLOCK(sc); 3921 4090 } … … 4040 4209 4041 4210 /* Disable host interrupts. */ 4042 4211 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4043 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);4212 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4044 4213 4045 4214 /* 4046 4215 * Tell firmware we're shutting down. … … 4295 4464 4296 4465 #endif 4297 4466 4467 if (BGE_IS_5705_PLUS(sc)) 4468 return; 4469 4298 4470 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4299 4471 NULL, "BGE Statistics"); 4300 4472 schildren = children = SYSCTL_CHILDREN(tree); … … 4417 4589 { 4418 4590 struct bge_softc *sc; 4419 4591 uint32_t result; 4420 int base,offset;4592 int offset; 4421 4593 4422 4594 sc = (struct bge_softc *)arg1; 4423 4595 offset = arg2; 4424 if (BGE_IS_5705_PLUS(sc)) 4425 base = BGE_MAC_STATS; 4426 else 4427 base = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4428 result = CSR_READ_4(sc, base + offset + offsetof(bge_hostaddr, 4429 bge_addr_lo)); 4596 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4597 offsetof(bge_hostaddr, bge_addr_lo)); 4430 4598 return (sysctl_handle_int(oidp, &result, 0, req)); 4431 4599 } 4432 4600 … … 4537 4705 return (error); 4538 4706 } 4539 4707 #endif 4708 4709 static int 4710 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4711 { 4712 4713 if (sc->bge_flags & BGE_FLAG_EADDR) 4714 return (1); 4715 4716 #ifdef __sparc64__ 4717 OF_getetheraddr(sc->bge_dev, ether_addr); 4718 return (0); 4719 #endif 4720 return (1); 4721 } 4722 4723 static int 4724 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4725 { 4726 uint32_t mac_addr; 4727 4728 mac_addr = bge_readmem_ind(sc, 0x0c14); 4729 if ((mac_addr >> 16) == 0x484b) { 4730 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4731 ether_addr[1] = (uint8_t)mac_addr; 4732 mac_addr = bge_readmem_ind(sc, 0x0c18); 4733 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4734 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4735 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4736 ether_addr[5] = (uint8_t)mac_addr; 4737 return (0); 4738 } 4739 return (1); 4740 } 4741 4742 static int 4743 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4744 { 4745 int mac_offset = BGE_EE_MAC_OFFSET; 4746 4747 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4748 mac_offset = BGE_EE_MAC_OFFSET_5906; 4749 4750 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4751 ETHER_ADDR_LEN)); 4752 } 4753 4754 static int 4755 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4756 { 4757 4758 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4759 return (1); 4760 4761 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4762 ETHER_ADDR_LEN)); 4763 } 4764 4765 static int 4766 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4767 { 4768 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4769 /* NOTE: Order is critical */ 4770 bge_get_eaddr_fw, 4771 bge_get_eaddr_mem, 4772 bge_get_eaddr_nvram, 4773 bge_get_eaddr_eeprom, 4774 NULL 4775 }; 4776 const bge_eaddr_fcn_t *func; 4777 4778 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4779 if ((*func)(sc, eaddr) == 0) 4780 break; 4781 } 4782 return (*func == NULL ? ENXIO : 0); 4783 }