Ticket #5180: rtl81xx.diff

File rtl81xx.diff, 31.1 KB (added by Lynton, 11 years ago)

RTL81XX Network Driver Diff

  • src/add-ons/kernel/drivers/network/rtl81xx/pci/if_rlreg.h

     
    2929 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
    3030 * THE POSSIBILITY OF SUCH DAMAGE.
    3131 *
    32  * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.67.2.14 2008/08/09 02:07:30 yongari Exp $
     32 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.67.2.26 2009/11/29 20:34:41 yongari Exp $
    3333 */
    3434
    3535/*
     
    131131#define RL_TBI_ANAR     0x0068
    132132#define RL_TBI_LPAR     0x006A
    133133#define RL_GMEDIASTAT       0x006C  /* 8 bits */
     134#define RL_MACDBG       0x006D  /* 8 bits, 8168C SPIN2 only */
     135#define RL_GPIO         0x006E  /* 8 bits, 8168C SPIN2 only */
    134136#define RL_MAXRXPKTLEN      0x00DA  /* 16 bits, chip multiplies by 8 */
    135137#define RL_GTXSTART     0x0038  /* 8 bits */
    136138
     
    152154/* Known revision codes. */
    153155
    154156#define RL_HWREV_8169       0x00000000
    155 #define RL_HWREV_8110S      0x00800000
    156 #define RL_HWREV_8169S      0x04000000
     157#define RL_HWREV_8169S      0x00800000
     158#define RL_HWREV_8110S      0x04000000
    157159#define RL_HWREV_8169_8110SB    0x10000000
    158160#define RL_HWREV_8169_8110SC    0x18000000
    159161#define RL_HWREV_8102EL     0x24800000
     162#define RL_HWREV_8102EL_SPIN1   0x24c00000
     163#define RL_HWREV_8168D      0x28000000
     164#define RL_HWREV_8168DP     0x28800000
    160165#define RL_HWREV_8168_SPIN1 0x30000000
    161166#define RL_HWREV_8100E      0x30800000
    162167#define RL_HWREV_8101E      0x34000000
     
    177182#define RL_HWREV_8101       0x74c00000
    178183#define RL_HWREV_8100       0x78800000
    179184#define RL_HWREV_8169_8110SBL   0x7CC00000
     185#define RL_HWREV_8169_8110SCE   0x98000000
    180186
    181187#define RL_TXDMA_16BYTES    0x00000000
    182188#define RL_TXDMA_32BYTES    0x00000100
     
    307313#define RL_CMD_TX_ENB       0x0004
    308314#define RL_CMD_RX_ENB       0x0008
    309315#define RL_CMD_RESET        0x0010
     316#define RL_CMD_STOPREQ      0x0080
    310317
    311318/*
    312319 * EEPROM control register
     
    501508#define RL_RXBUFLEN     (1 << ((RL_RX_BUF_SZ >> 11) + 13))
    502509#define RL_TX_LIST_CNT      4
    503510#define RL_MIN_FRAMELEN     60
     511#define RL_TX_8139_BUF_ALIGN    4
     512#define RL_RX_8139_BUF_ALIGN    8
     513#define RL_RX_8139_BUF_RESERVE  sizeof(int64_t)
     514#define RL_RX_8139_BUF_GUARD_SZ \
     515    (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
    504516#define RL_TXTHRESH(x)      ((x) << 11)
    505517#define RL_TX_THRESH_INIT   96
    506518#define RL_RX_FIFOTHRESH    RL_RXFIFO_NOTHRESH
     
    522534    uint16_t        cur_rx;
    523535    uint8_t         *rl_rx_buf;
    524536    uint8_t         *rl_rx_buf_ptr;
    525     bus_dmamap_t        rl_rx_dmamap;
    526537
    527538    struct mbuf     *rl_tx_chain[RL_TX_LIST_CNT];
    528539    bus_dmamap_t        rl_tx_dmamap[RL_TX_LIST_CNT];
     540    bus_dma_tag_t       rl_tx_tag;
     541    bus_dma_tag_t       rl_rx_tag;
     542    bus_dmamap_t        rl_rx_dmamap;
     543    bus_addr_t      rl_rx_buf_paddr;
    529544    uint8_t         last_tx;
    530545    uint8_t         cur_tx;
    531546};
     
    745760#define RE_RX_DESC_BUFLEN   MCLBYTES
    746761#endif
    747762
    748 #define RL_MSI_MESSAGES 2
     763#define RL_MSI_MESSAGES 1
    749764
    750765#define RL_ADDR_LO(y)       ((uint64_t) (y) & 0xFFFFFFFF)
    751766#define RL_ADDR_HI(y)       ((uint64_t) (y) >> 32)
     
    813828    void            *rl_intrhand[RL_MSI_MESSAGES];
    814829    device_t        rl_miibus;
    815830    bus_dma_tag_t       rl_parent_tag;
    816     bus_dma_tag_t       rl_tag;
    817831    uint8_t         rl_type;
    818832    int         rl_eecmd_read;
    819833    int         rl_eewidth;
     
    841855    int         rl_txstart;
    842856    uint32_t        rl_flags;
    843857#define RL_FLAG_MSI     0x0001
    844 #define RL_FLAG_INVMAR      0x0004
     858#define RL_FLAG_AUTOPAD     0x0002
    845859#define RL_FLAG_PHYWAKE     0x0008
    846860#define RL_FLAG_NOJUMBO     0x0010
    847861#define RL_FLAG_PAR     0x0020
    848862#define RL_FLAG_DESCV2      0x0040
    849863#define RL_FLAG_MACSTAT     0x0080
     864#define RL_FLAG_FASTETHER   0x0100
     865#define RL_FLAG_CMDSTOP     0x0200
     866#define RL_FLAG_MACRESET    0x0400
     867#define RL_FLAG_WOLRXENB    0x1000
     868#define RL_FLAG_MACSLEEP    0x2000
     869#define RL_FLAG_PCIE        0x4000
    850870#define RL_FLAG_LINK        0x8000
    851871};
    852872
     
    892912    CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
    893913
    894914#define RL_TIMEOUT      1000
     915#define RL_PHY_TIMEOUT      2000
    895916
    896917/*
    897918 * General constants that are fun to know.
     
    10971118#define RL_PSTATE_D3        0x0003
    10981119#define RL_PME_EN       0x0010
    10991120#define RL_PME_STATUS       0x8000
    1100 
  • src/add-ons/kernel/drivers/network/rtl81xx/pci/if_re.c

     
    3131 */
    3232
    3333#include <sys/cdefs.h>
    34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.95.2.36 2008/09/19 03:36:53 yongari Exp $");
     34__FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.95.2.54 2009/12/03 18:50:04 yongari Exp $");
    3535
    3636/*
    3737 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
     
    156156#include "miibus_if.h"
    157157
    158158/* Tunables. */
    159 static int msi_disable = 1;
     159static int msi_disable = 0;
    160160TUNABLE_INT("hw.re.msi_disable", &msi_disable);
     161static int prefer_iomap = 0;
     162TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
    161163
    162164#define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
    163165
     
    167169static struct rl_type re_devs[] = {
    168170    { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
    169171        "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
    170     /*{ RT_VENDORID, RT_DEVICEID_8139, 0,
    171         "RealTek 8139C+ 10/100BaseTX" },*/
     172    { RT_VENDORID, RT_DEVICEID_8139, 0,
     173        "RealTek 8139C+ 10/100BaseTX" },
    172174    { RT_VENDORID, RT_DEVICEID_8101E, 0,
    173175        "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" },
    174     /*{ RT_VENDORID, RT_DEVICEID_8168, 0,
    175         "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe "
    176         "Gigabit Ethernet" },
     176    { RT_VENDORID, RT_DEVICEID_8168, 0,
     177        "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/"
     178        "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" },
    177179    { RT_VENDORID, RT_DEVICEID_8169, 0,
    178180        "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
    179181    { RT_VENDORID, RT_DEVICEID_8169SC, 0,
    180         "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },*/
     182        "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
    181183    { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
    182184        "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
    183185    { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
     
    199201    { RL_HWREV_8169, RL_8169, "8169"},
    200202    { RL_HWREV_8169S, RL_8169, "8169S"},
    201203    { RL_HWREV_8110S, RL_8169, "8110S"},
    202     { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
    203     { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
    204     { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"},
     204    { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"},
     205    { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"},
     206    { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"},
     207    { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"},
    205208    { RL_HWREV_8100, RL_8139, "8100"},
    206209    { RL_HWREV_8101, RL_8139, "8101"},
    207210    { RL_HWREV_8100E, RL_8169, "8100E"},
    208211    { RL_HWREV_8101E, RL_8169, "8101E"},
    209212    { RL_HWREV_8102E, RL_8169, "8102E"},
    210213    { RL_HWREV_8102EL, RL_8169, "8102EL"},
     214    { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"},
    211215    { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
    212216    { RL_HWREV_8168_SPIN3, RL_8169, "8168"},
    213217    { RL_HWREV_8168C, RL_8169, "8168C/8111C"},
    214218    { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
    215219    { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
     220    { RL_HWREV_8168D, RL_8169, "8168D/8111D"},
     221    { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"},
    216222    { 0, 0, NULL }
    217223};
    218224
     
    220226static int re_attach        (device_t);
    221227static int re_detach        (device_t);
    222228
    223 static struct mbuf *re_defrag   (struct mbuf *, int, int);
    224229static int re_encap     (struct rl_softc *, struct mbuf **);
    225230
    226231static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
     
    266271static int re_miibus_writereg   (device_t, int, int, int);
    267272static void re_miibus_statchg   (device_t);
    268273
    269 static void re_setmulti     (struct rl_softc *);
     274static void re_set_rxmode       (struct rl_softc *);
    270275static void re_reset        (struct rl_softc *);
    271276static void re_setwol       (struct rl_softc *);
    272277static void re_clrwol       (struct rl_softc *);
     
    419424    CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
    420425    DELAY(1000);
    421426
    422     for (i = 0; i < RL_TIMEOUT; i++) {
     427    for (i = 0; i < RL_PHY_TIMEOUT; i++) {
    423428        rval = CSR_READ_4(sc, RL_PHYAR);
    424429        if (rval & RL_PHYAR_BUSY)
    425430            break;
    426431        DELAY(100);
    427432    }
    428433
    429     if (i == RL_TIMEOUT) {
     434    if (i == RL_PHY_TIMEOUT) {
    430435        device_printf(sc->rl_dev, "PHY read failed\n");
    431436        return (0);
    432437    }
     
    447452        (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
    448453    DELAY(1000);
    449454
    450     for (i = 0; i < RL_TIMEOUT; i++) {
     455    for (i = 0; i < RL_PHY_TIMEOUT; i++) {
    451456        rval = CSR_READ_4(sc, RL_PHYAR);
    452457        if (!(rval & RL_PHYAR_BUSY))
    453458            break;
    454459        DELAY(100);
    455460    }
    456461
    457     if (i == RL_TIMEOUT) {
     462    if (i == RL_PHY_TIMEOUT) {
    458463        device_printf(sc->rl_dev, "PHY write failed\n");
    459464        return (0);
    460465    }
     
    573578static void
    574579re_miibus_statchg(device_t dev)
    575580{
     581    struct rl_softc     *sc;
     582    struct ifnet        *ifp;
     583    struct mii_data     *mii;
    576584
     585    sc = device_get_softc(dev);
     586    mii = device_get_softc(sc->rl_miibus);
     587    ifp = sc->rl_ifp;
     588    if (mii == NULL || ifp == NULL ||
     589        (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
     590        return;
     591
     592    sc->rl_flags &= ~RL_FLAG_LINK;
     593    if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
     594        (IFM_ACTIVE | IFM_AVALID)) {
     595        switch (IFM_SUBTYPE(mii->mii_media_active)) {
     596        case IFM_10_T:
     597        case IFM_100_TX:
     598            sc->rl_flags |= RL_FLAG_LINK;
     599            break;
     600        case IFM_1000_T:
     601            if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
     602                break;
     603            sc->rl_flags |= RL_FLAG_LINK;
     604            break;
     605        default:
     606            break;
     607        }
     608    }
     609    /*
     610     * RealTek controllers does not provide any interface to
     611     * Tx/Rx MACs for resolved speed, duplex and flow-control
     612     * parameters.
     613     */
    577614}
    578615
    579616/*
    580  * Program the 64-bit multicast hash filter.
     617 * Set the RX configuration and 64-bit multicast hash filter.
    581618 */
    582619static void
    583 re_setmulti(struct rl_softc *sc)
     620re_set_rxmode(struct rl_softc *sc)
    584621{
    585622    struct ifnet        *ifp;
    586     int         h = 0;
    587     u_int32_t       hashes[2] = { 0, 0 };
    588623    struct ifmultiaddr  *ifma;
    589     u_int32_t       rxfilt;
    590     int         mcnt = 0;
     624    uint32_t        hashes[2] = { 0, 0 };
     625    uint32_t        h, rxfilt;
    591626
    592627    RL_LOCK_ASSERT(sc);
    593628
    594629    ifp = sc->rl_ifp;
    595630
     631    rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
    596632
    597     rxfilt = CSR_READ_4(sc, RL_RXCFG);
    598     rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI);
    599     if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
     633    if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
    600634        if (ifp->if_flags & IFF_PROMISC)
    601635            rxfilt |= RL_RXCFG_RX_ALLPHYS;
    602636        /*
     
    605639         * promiscuous mode.
    606640         */
    607641        rxfilt |= RL_RXCFG_RX_MULTI;
    608         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
    609         CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
    610         CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
    611         return;
     642        hashes[0] = hashes[1] = 0xffffffff;
     643        goto done;
    612644    }
    613645
    614     /* first, zot all the existing hash bits */
    615     CSR_WRITE_4(sc, RL_MAR0, 0);
    616     CSR_WRITE_4(sc, RL_MAR4, 0);
    617 
    618     /* now program new ones */
    619646    IF_ADDR_LOCK(ifp);
    620647    TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
    621648        if (ifma->ifma_addr->sa_family != AF_LINK)
     
    626653            hashes[0] |= (1 << h);
    627654        else
    628655            hashes[1] |= (1 << (h - 32));
    629         mcnt++;
    630656    }
    631657    IF_ADDR_UNLOCK(ifp);
    632658
    633     if (mcnt)
     659    if (hashes[0] != 0 || hashes[1] != 0) {
     660        /*
     661         * For some unfathomable reason, RealTek decided to
     662         * reverse the order of the multicast hash registers
     663         * in the PCI Express parts.  This means we have to
     664         * write the hash pattern in reverse order for those
     665         * devices.
     666         */
     667        if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
     668            h = bswap32(hashes[0]);
     669            hashes[0] = bswap32(hashes[1]);
     670            hashes[1] = h;
     671        }
    634672        rxfilt |= RL_RXCFG_RX_MULTI;
    635     else
    636         rxfilt &= ~RL_RXCFG_RX_MULTI;
     673    }
    637674
     675done:
     676    CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
     677    CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
    638678    CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
    639 
    640     /*
    641      * For some unfathomable reason, RealTek decided to reverse
    642      * the order of the multicast hash registers in the PCI Express
    643      * parts. This means we have to write the hash pattern in reverse
    644      * order for those devices.
    645      */
    646 
    647     if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) {
    648         CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1]));
    649         CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0]));
    650     } else {
    651         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
    652         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
    653     }
    654679}
    655680
    656681static void
     
    670695    if (i == RL_TIMEOUT)
    671696        device_printf(sc->rl_dev, "reset never completed!\n");
    672697
    673     CSR_WRITE_1(sc, 0x82, 1);
     698    if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
     699        CSR_WRITE_1(sc, 0x82, 1);
     700    if (sc->rl_hwrev == RL_HWREV_8169S)
     701        re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
    674702}
    675703
    676704#ifdef RE_DIAG
     
    726754
    727755    ifp->if_flags |= IFF_PROMISC;
    728756    sc->rl_testmode = 1;
    729     re_reset(sc);
     757    ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
    730758    re_init_locked(sc);
    731759    sc->rl_flags |= RL_FLAG_LINK;
    732760    if (sc->rl_type == RL_8169)
     
    10971125    pci_enable_busmaster(dev);
    10981126
    10991127    devid = pci_get_device(dev);
    1100     /* Prefer memory space register mapping over IO space. */
    1101     sc->rl_res_id = PCIR_BAR(1);
    1102     sc->rl_res_type = SYS_RES_MEMORY;
    1103     /* RTL8168/8101E seems to use different BARs. */
    1104     if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
    1105         sc->rl_res_id = PCIR_BAR(2);
     1128    /*
     1129     * Prefer memory space register mapping over IO space.
     1130     * Because RTL8169SC does not seem to work when memory mapping
     1131     * is used always activate io mapping.
     1132     */
     1133    if (devid == RT_DEVICEID_8169SC)
     1134        prefer_iomap = 1;
     1135    if (prefer_iomap == 0) {
     1136        sc->rl_res_id = PCIR_BAR(1);
     1137        sc->rl_res_type = SYS_RES_MEMORY;
     1138        /* RTL8168/8101E seems to use different BARs. */
     1139        if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
     1140            sc->rl_res_id = PCIR_BAR(2);
     1141    } else {
     1142        sc->rl_res_id = PCIR_BAR(0);
     1143        sc->rl_res_type = SYS_RES_IOPORT;
     1144    }
    11061145    sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
    11071146        &sc->rl_res_id, RF_ACTIVE);
    1108 
    1109     if (sc->rl_res == NULL) {
     1147    if (sc->rl_res == NULL && prefer_iomap == 0) {
    11101148        sc->rl_res_id = PCIR_BAR(0);
    11111149        sc->rl_res_type = SYS_RES_IOPORT;
    11121150        sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
    11131151            &sc->rl_res_id, RF_ACTIVE);
    1114         if (sc->rl_res == NULL) {
    1115             device_printf(dev, "couldn't map ports/memory\n");
    1116             error = ENXIO;
    1117             goto fail;
    1118         }
    11191152    }
     1153    if (sc->rl_res == NULL) {
     1154        device_printf(dev, "couldn't map ports/memory\n");
     1155        error = ENXIO;
     1156        goto fail;
     1157    }
    11201158
    11211159    sc->rl_btag = rman_get_bustag(sc->rl_res);
    11221160    sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
    11231161
    11241162    msic = 0;
    11251163    if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
     1164        sc->rl_flags |= RL_FLAG_PCIE;
    11261165        msic = pci_msi_count(dev);
    11271166        if (bootverbose)
    11281167            device_printf(dev, "MSI count : %d\n", msic);
    11291168    }
    1130     if (msic == RL_MSI_MESSAGES  && msi_disable == 0) {
     1169    if (msic > 0 && msi_disable == 0) {
     1170        msic = 1;
    11311171        if (pci_alloc_msi(dev, &msic) == 0) {
    11321172            if (msic == RL_MSI_MESSAGES) {
    11331173                device_printf(dev, "Using %d MSI messages\n",
     
    11861226
    11871227    hw_rev = re_hwrevs;
    11881228    hwrev = CSR_READ_4(sc, RL_TXCFG);
    1189     device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
     1229    switch (hwrev & 0x70000000) {
     1230    case 0x00000000:
     1231    case 0x10000000:
     1232        device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
     1233        hwrev &= (RL_TXCFG_HWREV | 0x80000000);
     1234        break;
     1235    default:
     1236        device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
     1237        hwrev &= RL_TXCFG_HWREV;
     1238        break;
     1239    }
    11901240    device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
    1191     hwrev &= RL_TXCFG_HWREV;
    11921241    while (hw_rev->rl_desc != NULL) {
    11931242        if (hw_rev->rl_rev == hwrev) {
    11941243            sc->rl_type = hw_rev->rl_type;
     1244            sc->rl_hwrev = hw_rev->rl_rev;
    11951245            break;
    11961246        }
    11971247        hw_rev++;
     
    12041254
    12051255    switch (hw_rev->rl_rev) {
    12061256    case RL_HWREV_8139CPLUS:
    1207         sc->rl_flags |= RL_FLAG_NOJUMBO;
     1257        sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER |
     1258            RL_FLAG_AUTOPAD;
    12081259        break;
    12091260    case RL_HWREV_8100E:
    12101261    case RL_HWREV_8101E:
    1211         sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
    1212             RL_FLAG_PHYWAKE;
     1262        sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
     1263            RL_FLAG_FASTETHER;
    12131264        break;
    12141265    case RL_HWREV_8102E:
    12151266    case RL_HWREV_8102EL:
    1216         sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
    1217             RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
    1218             RL_FLAG_MACSTAT;
     1267    case RL_HWREV_8102EL_SPIN1:
     1268        sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
     1269            RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
     1270            RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
    12191271        break;
    12201272    case RL_HWREV_8168_SPIN1:
    12211273    case RL_HWREV_8168_SPIN2:
     1274        sc->rl_flags |= RL_FLAG_WOLRXENB;
     1275        /* FALLTHROUGH */
    12221276    case RL_HWREV_8168_SPIN3:
    1223         sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
    1224             RL_FLAG_MACSTAT;
     1277        sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
    12251278        break;
     1279    case RL_HWREV_8168C_SPIN2:
     1280        sc->rl_flags |= RL_FLAG_MACSLEEP;
     1281        /* FALLTHROUGH */
    12261282    case RL_HWREV_8168C:
    1227     case RL_HWREV_8168C_SPIN2:
     1283        if ((hwrev & 0x00700000) == 0x00200000)
     1284            sc->rl_flags |= RL_FLAG_MACSLEEP;
     1285        /* FALLTHROUGH */
    12281286    case RL_HWREV_8168CP:
    1229         sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
    1230             RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT;
     1287    case RL_HWREV_8168D:
     1288    case RL_HWREV_8168DP:
     1289        sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
     1290            RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
     1291            RL_FLAG_AUTOPAD;
    12311292        /*
    12321293         * These controllers support jumbo frame but it seems
    12331294         * that enabling it requires touching additional magic
     
    12411302        sc->rl_flags |= RL_FLAG_NOJUMBO;
    12421303        break;
    12431304    case RL_HWREV_8169_8110SB:
     1305    case RL_HWREV_8169_8110SBL:
    12441306    case RL_HWREV_8169_8110SC:
    1245     case RL_HWREV_8169_8110SBL:
     1307    case RL_HWREV_8169_8110SCE:
    12461308        sc->rl_flags |= RL_FLAG_PHYWAKE;
     1309        /* FALLTHROUGH */
     1310    case RL_HWREV_8169:
     1311    case RL_HWREV_8169S:
     1312    case RL_HWREV_8110S:
     1313        sc->rl_flags |= RL_FLAG_MACRESET;
    12471314        break;
    12481315    default:
    12491316        break;
     
    13061373        goto fail;
    13071374    }
    13081375
     1376    /* Take controller out of deep sleep mode. */
     1377    if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
     1378        if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
     1379            CSR_WRITE_1(sc, RL_GPIO,
     1380                CSR_READ_1(sc, RL_GPIO) | 0x01);
     1381        else
     1382            CSR_WRITE_1(sc, RL_GPIO,
     1383                CSR_READ_1(sc, RL_GPIO) & ~0x01);
     1384    }
     1385
    13091386    /* Take PHY out of power down mode. */
    13101387    if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
    13111388        re_gmii_writereg(dev, 1, 0x1f, 0);
     
    13551432    ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
    13561433    if (ifp->if_capabilities & IFCAP_HWCSUM)
    13571434        ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
    1358 #ifdef ENABLE_WOL
    13591435    /* Enable WOL if PM is supported. */
    13601436    if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &reg) == 0)
    13611437        ifp->if_capabilities |= IFCAP_WOL;
    1362 #endif
    13631438    ifp->if_capenable = ifp->if_capabilities;
    13641439    /*
    13651440     * Don't enable TSO by default. Under certain
     
    17441819
    17451820    for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
    17461821        i = RL_RX_DESC_NXT(sc, i)) {
     1822        if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
     1823            break;
    17471824        cur_rx = &sc->rl_ldata.rl_rx_list[i];
    17481825        rxstat = le32toh(cur_rx->rl_cmdstat);
    17491826        if ((rxstat & RL_RDESC_STAT_OWN) != 0)
     
    19842061    /* No changes made to the TX ring, so no flush needed */
    19852062
    19862063    if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
    1987         /*
    1988          * Some chips will ignore a second TX request issued
    1989          * while an existing transmission is in progress. If
    1990          * the transmitter goes idle but there are still
    1991          * packets waiting to be sent, we need to restart the
    1992          * channel here to flush them out. This only seems to
    1993          * be required with the PCIe devices.
    1994          */
    1995         CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
    1996 
    19972064#ifdef RE_TX_MODERATION
    19982065        /*
    19992066         * If not all descriptors have been reaped yet, reload
     
    20122079{
    20132080    struct rl_softc     *sc;
    20142081    struct mii_data     *mii;
    2015     struct ifnet        *ifp;
    20162082
    20172083    sc = xsc;
    2018     ifp = sc->rl_ifp;
    20192084
    20202085    RL_LOCK_ASSERT(sc);
    20212086
    2022     re_watchdog(sc);
    2023 
    20242087    mii = device_get_softc(sc->rl_miibus);
    20252088    mii_tick(mii);
    2026     if ((sc->rl_flags & RL_FLAG_LINK) != 0) {
    2027         if (!(mii->mii_media_status & IFM_ACTIVE))
    2028             sc->rl_flags &= ~RL_FLAG_LINK;
    2029     } else {
    2030         if (mii->mii_media_status & IFM_ACTIVE &&
    2031             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
    2032             sc->rl_flags |= RL_FLAG_LINK;
    2033             if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
    2034                 taskqueue_enqueue_fast(taskqueue_fast,
    2035                     &sc->rl_txtask);
    2036         }
    2037     }
    2038 
     2089    if ((sc->rl_flags & RL_FLAG_LINK) == 0)
     2090        re_miibus_statchg(sc->rl_dev);
     2091    /*
     2092     * Reclaim transmitted frames here. Technically it is not
     2093     * necessary to do here but it ensures periodic reclamation
     2094     * regardless of Tx completion interrupt which seems to be
     2095     * lost on PCIe based controllers under certain situations.
     2096     */
     2097    re_txeof(sc);
     2098    re_watchdog(sc);
    20392099    callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
    20402100}
    20412101
     
    20732133            return;
    20742134        if (status)
    20752135            CSR_WRITE_2(sc, RL_ISR, status);
     2136        if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
     2137            (sc->rl_flags & RL_FLAG_PCIE))
     2138            CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
    20762139
    20772140        /*
    20782141         * XXX check behaviour on receiver stalls.
    20792142         */
    20802143
    20812144        if (status & RL_ISR_SYSTEM_ERR) {
    2082             re_reset(sc);
     2145            ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
    20832146            re_init_locked(sc);
    20842147        }
    20852148    }
     
    21362199    if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
    21372200        rval = re_rxeof(sc);
    21382201
     2202    /*
     2203     * Some chips will ignore a second TX request issued
     2204     * while an existing transmission is in progress. If
     2205     * the transmitter goes idle but there are still
     2206     * packets waiting to be sent, we need to restart the
     2207     * channel here to flush them out. This only seems to
     2208     * be required with the PCIe devices.
     2209     */
     2210    if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
     2211        (sc->rl_flags & RL_FLAG_PCIE))
     2212        CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
    21392213    if (status & (
    21402214#ifdef RE_TX_MODERATION
    21412215        RL_ISR_TIMEOUT_EXPIRED|
     
    21462220        re_txeof(sc);
    21472221
    21482222    if (status & RL_ISR_SYSTEM_ERR) {
    2149         re_reset(sc);
     2223        ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
    21502224        re_init_locked(sc);
    21512225    }
    21522226
    2153     if (status & RL_ISR_LINKCHG) {
    2154         callout_stop(&sc->rl_stat_callout);
    2155         re_tick(sc);
    2156     }
    2157 
    21582227    if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
    21592228        taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
    21602229
     
    21682237    CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
    21692238}
    21702239
    2171 /*
    2172  * It's copy of ath_defrag(ath(4)).
    2173  *
    2174  * Defragment an mbuf chain, returning at most maxfrags separate
    2175  * mbufs+clusters.  If this is not possible NULL is returned and
    2176  * the original mbuf chain is left in it's present (potentially
    2177  * modified) state.  We use two techniques: collapsing consecutive
    2178  * mbufs and replacing consecutive mbufs by a cluster.
    2179  */
    2180 static struct mbuf *
    2181 re_defrag(m0, how, maxfrags)
    2182     struct mbuf *m0;
    2183     int how;
    2184     int maxfrags;
    2185 {
    2186     struct mbuf *m, *n, *n2, **prev;
    2187     u_int curfrags;
    2188 
    2189     /*
    2190      * Calculate the current number of frags.
    2191      */
    2192     curfrags = 0;
    2193     for (m = m0; m != NULL; m = m->m_next)
    2194         curfrags++;
    2195     /*
    2196      * First, try to collapse mbufs.  Note that we always collapse
    2197      * towards the front so we don't need to deal with moving the
    2198      * pkthdr.  This may be suboptimal if the first mbuf has much
    2199      * less data than the following.
    2200      */
    2201     m = m0;
    2202 again:
    2203     for (;;) {
    2204         n = m->m_next;
    2205         if (n == NULL)
    2206             break;
    2207         if ((m->m_flags & M_RDONLY) == 0 &&
    2208             n->m_len < M_TRAILINGSPACE(m)) {
    2209             bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
    2210                 n->m_len);
    2211             m->m_len += n->m_len;
    2212             m->m_next = n->m_next;
    2213             m_free(n);
    2214             if (--curfrags <= maxfrags)
    2215                 return (m0);
    2216         } else
    2217             m = n;
    2218     }
    2219     KASSERT(maxfrags > 1,
    2220         ("maxfrags %u, but normal collapse failed", maxfrags));
    2221     /*
    2222      * Collapse consecutive mbufs to a cluster.
    2223      */
    2224     prev = &m0->m_next;     /* NB: not the first mbuf */
    2225     while ((n = *prev) != NULL) {
    2226         if ((n2 = n->m_next) != NULL &&
    2227             n->m_len + n2->m_len < MCLBYTES) {
    2228             m = m_getcl(how, MT_DATA, 0);
    2229             if (m == NULL)
    2230                 goto bad;
    2231             bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
    2232             bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
    2233                 n2->m_len);
    2234             m->m_len = n->m_len + n2->m_len;
    2235             m->m_next = n2->m_next;
    2236             *prev = m;
    2237             m_free(n);
    2238             m_free(n2);
    2239             if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
    2240                 return m0;
    2241             /*
    2242              * Still not there, try the normal collapse
    2243              * again before we allocate another cluster.
    2244              */
    2245             goto again;
    2246         }
    2247         prev = &n->m_next;
    2248     }
    2249     /*
    2250      * No place where we can collapse to a cluster; punt.
    2251      * This can occur if, for example, you request 2 frags
    2252      * but the packet requires that both be clusters (we
    2253      * never reallocate the first mbuf to avoid moving the
    2254      * packet header).
    2255      */
    2256 bad:
    2257     return (NULL);
    2258 }
    2259 
    2260 
    2261 
    22622240static int
    22632241re_encap(struct rl_softc *sc, struct mbuf **m_head)
    22642242{
     
    22862264     * offload is enabled, we always manually pad short frames out
    22872265     * to the minimum ethernet frame size.
    22882266     */
    2289     if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 &&
     2267    if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
    22902268        (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
    22912269        ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
    22922270        padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
     
    23262304    error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
    23272305        *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
    23282306    if (error == EFBIG) {
    2329         m_new = re_defrag(*m_head, M_DONTWAIT, RL_NTXSEGS);
     2307        m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
    23302308        if (m_new == NULL) {
    23312309            m_freem(*m_head);
    23322310            *m_head = NULL;
     
    25492527{
    25502528    struct ifnet        *ifp = sc->rl_ifp;
    25512529    struct mii_data     *mii;
    2552     u_int32_t       rxcfg = 0;
     2530    uint32_t        reg;
    25532531    uint16_t        cfg;
    25542532    union {
    25552533        uint32_t align_dummy;
     
    25602538
    25612539    mii = device_get_softc(sc->rl_miibus);
    25622540
     2541    if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
     2542        return;
     2543
    25632544    /*
    25642545     * Cancel pending I/O and free all RX/TX buffers.
    25652546     */
    25662547    re_stop(sc);
    25672548
     2549    /* Put controller into known state. */
     2550    re_reset(sc);
     2551
    25682552    /*
    25692553     * Enable C+ RX and TX mode, as well as VLAN stripping and
    25702554     * RX checksum offload. We must configure the C+ register
     
    25822566    } else
    25832567        cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
    25842568    CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
     2569    if (sc->rl_hwrev == RL_HWREV_8169_8110SC ||
     2570        sc->rl_hwrev == RL_HWREV_8169_8110SCE) {
     2571        reg = 0x000fff00;
     2572        if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
     2573            reg |= 0x000000ff;
     2574        if (sc->rl_hwrev == RL_HWREV_8169_8110SCE)
     2575            reg |= 0x00f00000;
     2576        CSR_WRITE_4(sc, 0x7c, reg);
     2577        /* Disable interrupt mitigation. */
     2578        CSR_WRITE_2(sc, 0xe2, 0);
     2579    }
    25852580    /*
    25862581     * Disable TSO if interface MTU size is greater than MSS
    25872582     * allowed in controller.
     
    26312626    CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
    26322627
    26332628    /*
    2634      * Set the initial TX and RX configuration.
     2629     * Set the initial TX configuration.
    26352630     */
    26362631    if (sc->rl_testmode) {
    26372632        if (sc->rl_type == RL_8169)
     
    26452640
    26462641    CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
    26472642
    2648     CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
    2649 
    2650     /* Set the individual bit to receive frames for this host only. */
    2651     rxcfg = CSR_READ_4(sc, RL_RXCFG);
    2652     rxcfg |= RL_RXCFG_RX_INDIV;
    2653 
    2654     /* If we want promiscuous mode, set the allframes bit. */
    2655     if (ifp->if_flags & IFF_PROMISC)
    2656         rxcfg |= RL_RXCFG_RX_ALLPHYS;
    2657     else
    2658         rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
    2659     CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
    2660 
    26612643    /*
    2662      * Set capture broadcast bit to capture broadcast frames.
     2644     * Set the initial RX configuration.
    26632645     */
    2664     if (ifp->if_flags & IFF_BROADCAST)
    2665         rxcfg |= RL_RXCFG_RX_BROAD;
    2666     else
    2667         rxcfg &= ~RL_RXCFG_RX_BROAD;
    2668     CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
     2646    re_set_rxmode(sc);
    26692647
    2670     /*
    2671      * Program the multicast filter, if necessary.
    2672      */
    2673     re_setmulti(sc);
    2674 
    26752648#ifdef DEVICE_POLLING
    26762649    /*
    26772650     * Disable interrupts if we are polling.
     
    27442717{
    27452718    struct rl_softc     *sc;
    27462719    struct mii_data     *mii;
     2720    int         error;
    27472721
    27482722    sc = ifp->if_softc;
    27492723    mii = device_get_softc(sc->rl_miibus);
    27502724    RL_LOCK(sc);
    2751     mii_mediachg(mii);
     2725    error = mii_mediachg(mii);
    27522726    RL_UNLOCK(sc);
    27532727
    2754     return (0);
     2728    return (error);
    27552729}
    27562730
    27572731/*
     
    28082782            if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
    28092783                if (((ifp->if_flags ^ sc->rl_if_flags)
    28102784                    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
    2811                     re_setmulti(sc);
     2785                    re_set_rxmode(sc);
    28122786            } else
    28132787                re_init_locked(sc);
    28142788        } else {
     
    28212795    case SIOCADDMULTI:
    28222796    case SIOCDELMULTI:
    28232797        RL_LOCK(sc);
    2824         re_setmulti(sc);
     2798        if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
     2799            re_set_rxmode(sc);
    28252800        RL_UNLOCK(sc);
    28262801        break;
    28272802    case SIOCGIFMEDIA:
     
    28812856                ifp->if_hwassist &= ~CSUM_TSO;
    28822857            }
    28832858        }
    2884 #ifdef ENABLE_WOL
    28852859        if ((mask & IFCAP_WOL) != 0 &&
    28862860            (ifp->if_capabilities & IFCAP_WOL) != 0) {
    28872861            if ((mask & IFCAP_WOL_UCAST) != 0)
     
    28912865            if ((mask & IFCAP_WOL_MAGIC) != 0)
    28922866                ifp->if_capenable ^= IFCAP_WOL_MAGIC;
    28932867        }
    2894 #endif
    2895         if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
     2868        if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
     2869            ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
    28962870            re_init(sc);
     2871        }
    28972872        VLAN_CAPABILITIES(ifp);
    28982873        }
    28992874        break;
     
    29082883static void
    29092884re_watchdog(struct rl_softc *sc)
    29102885{
     2886    struct ifnet        *ifp;
    29112887
    29122888    RL_LOCK_ASSERT(sc);
    29132889
    29142890    if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
    29152891        return;
    29162892
    2917     device_printf(sc->rl_dev, "watchdog timeout\n");
    2918     sc->rl_ifp->if_oerrors++;
     2893    ifp = sc->rl_ifp;
     2894    re_txeof(sc);
     2895    if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
     2896        if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
     2897            "-- recovering\n");
     2898        if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
     2899            taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
     2900        return;
     2901    }
    29192902
    2920     re_txeof(sc);
     2903    if_printf(ifp, "watchdog timeout\n");
     2904    ifp->if_oerrors++;
     2905
    29212906    re_rxeof(sc);
     2907    ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
    29222908    re_init_locked(sc);
     2909    if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
     2910        taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
    29232911}
    29242912
    29252913/*
     
    29422930    callout_stop(&sc->rl_stat_callout);
    29432931    ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
    29442932
    2945     CSR_WRITE_1(sc, RL_COMMAND, 0x00);
     2933    if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0)
     2934        CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
     2935            RL_CMD_RX_ENB);
     2936    else
     2937        CSR_WRITE_1(sc, RL_COMMAND, 0x00);
     2938    DELAY(1000);
    29462939    CSR_WRITE_2(sc, RL_IMR, 0x0000);
    29472940    CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
    29482941
     
    30173010    RL_LOCK(sc);
    30183011
    30193012    ifp = sc->rl_ifp;
     3013    /* Take controller out of sleep mode. */
     3014    if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
     3015        if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
     3016            CSR_WRITE_1(sc, RL_GPIO,
     3017                CSR_READ_1(sc, RL_GPIO) | 0x01);
     3018    }
    30203019
    3021     /* reinitialize interface if necessary */
    3022     if (ifp->if_flags & IFF_UP)
    3023         re_init_locked(sc);
    3024 
    30253020    /*
    30263021     * Clear WOL matching such that normal Rx filtering
    30273022     * wouldn't interfere with WOL patterns.
    30283023     */
    30293024    re_clrwol(sc);
     3025
     3026    /* reinitialize interface if necessary */
     3027    if (ifp->if_flags & IFF_UP)
     3028        re_init_locked(sc);
     3029
    30303030    sc->suspended = 0;
    30313031    RL_UNLOCK(sc);
    30323032
     
    30613061static void
    30623062re_setwol(struct rl_softc *sc)
    30633063{
    3064 #ifdef ENABLE_WOL
    30653064    struct ifnet        *ifp;
    30663065    int         pmc;
    30673066    uint16_t        pmstat;
     
    30733072        return;
    30743073
    30753074    ifp = sc->rl_ifp;
     3075    /* Put controller into sleep mode. */
     3076    if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
     3077        if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
     3078            CSR_WRITE_1(sc, RL_GPIO,
     3079                CSR_READ_1(sc, RL_GPIO) & ~0x01);
     3080    }
     3081    if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
     3082        (sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
     3083        CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
    30763084    /* Enable config register write. */
    30773085    CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
    30783086
     
    31153123    if ((ifp->if_capenable & IFCAP_WOL) != 0)
    31163124        pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
    31173125    pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
    3118 #endif
    31193126}
    31203127
    31213128static void
    31223129re_clrwol(struct rl_softc *sc)
    31233130{
    3124 #ifdef ENABLE_WOL
    31253131    int         pmc;
    31263132    uint8_t         v;
    31273133
     
    31443150    v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
    31453151    v &= ~RL_CFG5_WOL_LANWAKE;
    31463152    CSR_WRITE_1(sc, RL_CFG5, v);
    3147 #endif
    31483153}
    3149