Ticket #5380: haiku-beagle-video.diff

File haiku-beagle-video.diff, 22.9 KB (added by notzed, 9 years ago)

patch

  • src/system/boot/platform/u-boot/video.cpp

     
    8888        return;
    8989
    9090    //XXX: not yet, DISABLED
    91     return;
     91    //return;
    9292
    9393    status_t err;
    9494
     
    118118        #warning ARM:TODO
    119119    arch_probe_video_mode();
    120120    //XXX for testing
    121     //platform_switch_to_logo();
     121    platform_switch_to_logo();
    122122    //return arch_probe_video_mode();
    123     //return B_OK;
     123    return B_OK;
    124124}
    125125
  • src/system/boot/platform/u-boot/Jamfile

     
    196197        $(HAIKU_BOARD_SDIMAGE_UBOOT_SCRIPT) ;
    197198}
    198199
     200if $(HAIKU_BOARD_MLO_IMAGE) && $(HAIKU_BOARD_MLO_IMAGE_URL) {
     201    DownloadFile $(HAIKU_BOARD_MLO_IMAGE) $(HAIKU_BOARD_MLO_IMAGE_URL) ;
     202}
     203
    199204if $(HAIKU_BOARD_UBOOT_IMAGE) && $(HAIKU_BOARD_UBOOT_IMAGE_URL) {
    200205    # Download the u-boot binary file.
    201206    DownloadFile $(HAIKU_BOARD_UBOOT_IMAGE) $(HAIKU_BOARD_UBOOT_IMAGE_URL) ;
  • src/system/boot/arch/arm/arch_video.cpp

     
    209209#elif BOARD_CPU_OMAP3
    210210//  #pragma mark -
    211211
     212#include "graphics/omap/omap3_regs.h"
    212213
     214extern void *gFrameBufferBase;
     215
     216struct video_mode {
     217    short width, height;
     218    const char *name;
     219    uint32 dispc_timing_h;
     220    uint32 dispc_timing_v;
     221    uint32 dispc_divisor;
     222    uint32 dss_divisor;
     223};
     224
     225// Master clock (PLL4) is 864 Mhz, and changing it is a pita since it
     226// cascades to other devices.
     227// Pixel clock is 864 / cm_clksel_dss.dss1_alwan_fclk / dispc_divisor.divisor.pcd
     228// So most of these modes are just approximate (1280x1024 is correct)
     229// List must be in ascending order.
     230struct video_mode modes[] = {
     231    {
     232        640, 480, "640x480-71",
     233        (128 << DISPCB_HBP) | (24 << DISPCB_HFP) | (40 << DISPCB_HSW),
     234        (28 << DISPCB_VBP) | (9 << DISPCB_VFP) | (3 << DISPCB_VSW),
     235        2, 14
     236    },
     237    {
     238        800, 600, "800x600-59",
     239        (88 << DISPCB_HBP) | (40 << DISPCB_HFP) | (128 << DISPCB_HSW),
     240        (23 << DISPCB_VBP) | (1 << DISPCB_VFP) | (4 << DISPCB_VSW),
     241        2, 11
     242    },           
     243    {
     244        1024, 768, "1024x768-61",
     245        (160 << DISPCB_HBP) | (24 << DISPCB_HFP) | (136 << DISPCB_HSW),
     246        (29 << DISPCB_VBP) | (3 << DISPCB_VFP) | (6 << DISPCB_VSW),
     247        1, 13
     248    },
     249    {
     250        1280, 1024, "1280x1024-60",
     251        (248 << DISPCB_HBP) | (48 << DISPCB_HFP) | (112 << DISPCB_HSW),
     252        (38 << DISPCB_VBP) | (1 << DISPCB_VFP) | (3 << DISPCB_VSW),
     253        1, 8
     254    },
     255};
     256
     257
     258static inline void setaddr(uint32 reg, unsigned int v)
     259{
     260    *((volatile uint32 *)(reg)) = v;
     261}
     262
     263
     264static inline void modaddr(unsigned int reg, unsigned int m, unsigned int v)
     265{
     266    uint32 o;
     267
     268    o = *((volatile uint32 *)(reg));
     269    o &= ~m;
     270    o |= v;
     271    *((volatile uint32 *)(reg)) = o;
     272}
     273
     274
     275static inline void setreg(uint32 base, unsigned int reg, unsigned int v)
     276{
     277    *((volatile uint32 *)(base+reg)) = v;
     278}
     279
     280
     281static inline uint32 readreg(uint32 base, unsigned int reg)
     282{
     283    return *((volatile uint32 *)(base+reg));
     284}
     285
     286
     287static inline void modreg(uint32 base, unsigned int reg, unsigned int m, unsigned int v)
     288{
     289    uint32 o;
     290
     291    o = *((volatile uint32 *)(base+reg));
     292    o &= ~m;
     293    o |= v;
     294    *((volatile uint32 *)(base+reg)) = o;
     295}
     296
     297
     298// init beagle gpio for video
     299static void omap_beagle_init(void)
     300{
     301    // setup GPIO stuff, i can't find any references to these
     302    setreg(GPIO1_BASE, GPIO_OE, 0xfefffedf);
     303    setreg(GPIO1_BASE, GPIO_SETDATAOUT, 0x01000120);
     304    // DVI-D is enabled by GPIO 170?
     305}
     306
     307
     308static void omap_clock_init(void)
     309{
     310    // sets pixel clock to 72MHz
     311
     312    // sys_clk = 26.0 Mhz
     313    // DPLL4 = sys_clk * 432 / 13 = 864
     314    // DSS1_ALWON_FCLK = 864 / 6 = 144
     315    // Pixel clock (DISPC_DIVISOR) = 144 / 2 = 72Mhz
     316    // and also VENC clock = 864 / 16 = 54MHz
     317
     318    // The clock multiplier/divider cannot be changed
     319    // without affecting other system clocks - do don't.
     320
     321    // pll4 clock multiplier/divider
     322    setaddr(CM_CLKSEL2_PLL, (432 << 8) | 12);
     323    // tv clock divider, dss1 alwon fclk divider
     324    setaddr(CM_CLKSEL_DSS, (16 << 8) | 6);
     325    // core/peripheral PLL to 1MHz
     326    setaddr(CM_CLKEN_PLL, 0x00370037);
     327}
     328
     329
     330static void omap_dss_init(void)
     331{
     332    setreg(DSS_BASE, DSS_SYSCONFIG, DSS_AUTOIDLE);
     333    // Select DSS1 ALWON as clock source
     334    setreg(DSS_BASE, DSS_CONTROL, DSS_VENC_OUT_SEL | DSS_DAC_POWERDN_BGZ | DSS_DAC_DEMEN | DSS_VENC_CLOCK_4X_ENABLE);
     335}
     336
     337
     338static void omap_dispc_init(void)
     339{
     340    uint32 DISPC = DISPC_BASE;
     341
     342    setreg(DISPC, DISPC_SYSCONFIG,
     343        DISPC_MIDLEMODE_SMART
     344        | DISPC_SIDLEMODE_SMART
     345        | DISPC_ENWAKEUP
     346        | DISPC_AUTOIDLE);
     347
     348    setreg(DISPC, DISPC_CONFIG, DISPC_LOADMODE_FRAME);
     349
     350    // LCD default colour = black
     351    setreg(DISPC, DISPC_DEFAULT_COLOR0, 0x000000);
     352
     353    setreg(DISPC, DISPC_POL_FREQ,
     354        DISPC_POL_IPC
     355        | DISPC_POL_IHS
     356        | DISPC_POL_IVS
     357        | (2<<DISPCB_POL_ACBI)
     358        | (8<<DISPCB_POL_ACB));
     359
     360    // Set pixel clock divisor = 2
     361    setreg(DISPC, DISPC_DIVISOR,
     362        (1<<DISPCB_DIVISOR_LCD)
     363        | (2<<DISPCB_DIVISOR_PCD));
     364
     365    // Disable graphical output
     366    setreg(DISPC, DISPC_GFX_ATTRIBUTES, 0);
     367
     368    // Turn on the LCD output
     369    setreg(DISPC, DISPC_CONTROL,
     370        DISPC_GPOUT1
     371        | DISPC_GPOUT0
     372        | DISPC_TFTDATALINES_24
     373        | DISPC_STDITHERENABLE
     374        | DISPC_GOLCD
     375        | DISPC_STNTFT
     376        | DISPC_LCDENABLE
     377        );
     378
     379    while ((readreg(DISPC, DISPC_CONTROL) & DISPC_GOLCD))
     380        ;
     381}
     382
     383
     384static void omap_set_lcd_mode(int w, int h) {
     385    uint32 DISPC = DISPC_BASE;
     386    unsigned int i;
     387    struct video_mode *m;
     388
     389    dprintf("omap3: set_lcd_mode %d,%d\n", w, h);
     390
     391    for (i=0;i<sizeof(modes)/sizeof(modes[0]);i++) {
     392        if (w <= modes[i].width
     393            && h <= modes[i].height)
     394        goto found;
     395    }
     396    i -= 1;
     397found:
     398    m = &modes[i];
     399   
     400    dprintf("omap3: found mode[%s]\n", m->name);
     401
     402    setreg(DISPC, DISPC_SIZE_LCD, (m->width - 1) | ((m->height-1) << 16));
     403    setreg(DISPC, DISPC_TIMING_H, m->dispc_timing_h);
     404    setreg(DISPC, DISPC_TIMING_V, m->dispc_timing_v);
     405
     406    modreg(DISPC, DISPC_DIVISOR, 0xffff, m->dispc_divisor);
     407    modaddr(CM_CLKSEL_DSS, 0xffff, m->dss_divisor);
     408
     409    // Tell hardware to update, and wait for it
     410    modreg(DISPC, DISPC_CONTROL,
     411          DISPC_GOLCD,
     412          DISPC_GOLCD);
     413
     414    while ((readreg(DISPC, DISPC_CONTROL) & DISPC_GOLCD))
     415        ;
     416}
     417
     418
     419static void omap_attach_framebuffer(void *data, int width, int height, int depth)
     420{
     421    uint32 DISPC = DISPC_BASE;
     422    uint32 gsize = ((height-1)<<16) | (width-1);
     423
     424    dprintf("omap3: attach bitmap (%d,%d) %p to screen\n", width, height, data);
     425
     426    setreg(DISPC, DISPC_GFX_BA0, (uint32)data);
     427    setreg(DISPC, DISPC_GFX_BA1, (uint32)data);
     428    setreg(DISPC, DISPC_GFX_POSITION, 0);
     429    setreg(DISPC, DISPC_GFX_SIZE, gsize);
     430    setreg(DISPC, DISPC_GFX_FIFO_THRESHOLD, (0x3ff << 16) | 0x3c0);
     431    setreg(DISPC, DISPC_GFX_ROW_INC, 1);
     432    setreg(DISPC, DISPC_GFX_PIXEL_INC, 1);
     433    setreg(DISPC, DISPC_GFX_WINDOW_SKIP, 0);
     434    setreg(DISPC, DISPC_GFX_ATTRIBUTES,
     435           DISPC_GFXFORMAT_RGB16
     436           | DISPC_GFXBURSTSIZE_16x32
     437           | DISPC_GFXENABLE);
     438
     439    // Tell hardware to update, and wait for it
     440    modreg(DISPC, DISPC_CONTROL,
     441           DISPC_GOLCD,
     442           DISPC_GOLCD);
     443   
     444    while ((readreg(DISPC, DISPC_CONTROL) & DISPC_GOLCD))
     445        ;
     446}
     447
     448
     449static void omap_init(void) {
     450    dprintf("omap3: video_init()\n");
     451
     452    setreg(DISPC_BASE, DISPC_IRQENABLE, 0x00000);
     453    setreg(DISPC_BASE, DISPC_IRQSTATUS, 0x1ffff);
     454
     455    omap_beagle_init();
     456    omap_clock_init();
     457    omap_dss_init();
     458    omap_dispc_init();
     459}
     460
     461
    213462status_t
    214463arch_probe_video_mode(void)
    215464{
    216     return B_ERROR;
     465    gKernelArgs.frame_buffer.depth = 16;
     466    gKernelArgs.frame_buffer.width = 1024;
     467    gKernelArgs.frame_buffer.height = 768;
     468    gKernelArgs.frame_buffer.bytes_per_row = gKernelArgs.frame_buffer.width * 2;
     469    gKernelArgs.frame_buffer.physical_buffer.size = gKernelArgs.frame_buffer.width
     470        * gKernelArgs.frame_buffer.height
     471        * gKernelArgs.frame_buffer.depth / 8;
     472
     473#if 0
     474    if (!gFrameBufferBase) {
     475        int err = platform_allocate_region(&gFrameBufferBase, gKernelArgs.frame_buffer.physical_buffer.size, 0, false);
     476        if (err < B_OK) return err;
     477        gKernelArgs.frame_buffer.physical_buffer.start = (addr_t)gFrameBufferBase;
     478        dprintf("video framebuffer: %p\n", gFrameBufferBase);
     479    }
     480#else
     481    gFrameBufferBase = (void *)0x88000000;
     482    gKernelArgs.frame_buffer.physical_buffer.start = (addr_t)gFrameBufferBase;
     483#endif
     484
     485    dprintf("video mode: %ux%ux%u\n", gKernelArgs.frame_buffer.width,
     486        gKernelArgs.frame_buffer.height, gKernelArgs.frame_buffer.depth);
     487
     488    gKernelArgs.frame_buffer.enabled = true;
     489
     490    omap_init();
     491
     492    return B_OK;
    217493}
    218494
    219495
    220496status_t
    221497arch_set_video_mode(int width, int height, int depth)
    222498{
    223     return B_ERROR;
     499    dprintf("arch_set_video_mode %d,%d @ %d\n", width, height, depth);
     500
     501    omap_set_lcd_mode(width, height);
     502    omap_attach_framebuffer(gFrameBufferBase, width, height, depth);
     503
     504    return B_OK;
    224505}
    225506
    226507
    227508status_t
    228509arch_set_default_video_mode()
    229510{
    230     return arch_set_video_mode(800, 600, 32);
     511    dprintf("arch_set_default_video_mode()\n");
     512
     513    return arch_set_video_mode(1024, 768, 16);
    231514}
    232515
    233516
  • headers/private/kernel/arch/arm/omap3.h

     
    253253#define I2C_ACTOA           (0x50)
    254254#define I2C_SBLOCK          (0x54)
    255255
     256/* GPIO */
     257#define GPIO1_BASE 0x48310000
     258#define GPIO2_BASE 0x49050000
     259#define GPIO3_BASE 0x49052000
     260#define GPIO4_BASE 0x49054000
     261#define GPIO5_BASE 0x49056000
     262#define GPIO6_BASE 0x49058000
     263
     264/* (incomplete) */
     265#define GPIO_OE 0x034
     266#define GPIO_DATAIN 0x038
     267#define GPIO_DATAOUT 0x03C
     268#define GPIO_SETDATAOUT 0x094
     269
    256270#endif
    257271
  • headers/private/graphics/omap/omap3_regs.h

     
     1/*
     2 * Copyright 2010 Michael Zucchi.
     3 * Distributed under the terms of the MIT License.
     4 *
     5 */
     6#ifndef _OMAP3_VIDEO_H
     7#define _OMAP3_VIDEO_H
     8
     9/* ********************************************************************** */
     10/* S 1.7.2 Display Subsystem & SDI Registers */
     11
     12#define DSS_BASE 0x48050000
     13
     14#define DSS_SYSCONFIG 0x010
     15#define DSS_SYSSTATUS 0x014
     16#define DSS_IRQSTATUS 0x018
     17#define DSS_CONTROL 0x040
     18#define DSS_SDI_CONTROL 0x044
     19#define DSS_PLL_CONTROL 0x048
     20#define DSS_SDI_STATUS 0x05C
     21
     22/* SYSCONFIG bits */
     23#define DSS_AUTOIDLE 1
     24#define DSS_SOFTRESET 2
     25/* SYSSTATUS bits */
     26#define DSS_RESETDONE 1
     27/* CONTROL bits */
     28#define DSS_VENC_OUT_SEL (1<<6) /* set s-video */
     29#define DSS_DAC_POWERDN_BGZ (1<<5)
     30#define DSS_DAC_DEMEN (1<<4)
     31#define DSS_VENC_CLOCK_4X_ENABLE (1<<3)
     32#define DSS_VENC_CLOCK_MODE (1<<2) /* set square pixel */
     33#define DSS_DSI_CLK_SWITCH (1<<1) /* select DSI2 PLL FCLK otherwise DSS1 ALWON FCLK */
     34#define DSS_DSS1_CLK_SWITCH (1<<0) /* same */
     35
     36/* ********************************************************************** */
     37/* S 1.7.3 Display controller */
     38
     39#define DISPC_BASE 0x48050400
     40
     41#define DISPC_SYSCONFIG 0x010
     42#define DISPC_SYSSTATUS 0x014
     43#define DISPC_IRQSTATUS 0x018
     44#define DISPC_IRQENABLE 0x01C
     45#define DISPC_CONTROL 0x040
     46#define DISPC_CONFIG 0x044
     47#define DISPC_DEFAULT_COLOR0 0x04c
     48#define DISPC_DEFAULT_COLOR1 0x050
     49#define DISPC_TRANS_COLOR0 0x54
     50#define DISPC_TRANS_COLOR1 0x58
     51#define DISPC_LINE_STATUS 0x05C
     52#define DISPC_LINE_NUMBER 0x060
     53#define DISPC_TIMING_H 0x064
     54#define DISPC_TIMING_V 0x068
     55#define DISPC_POL_FREQ 0x06C
     56#define DISPC_DIVISOR 0x070
     57#define DISPC_GLOBAL_ALPHA 0x074
     58#define DISPC_SIZE_DIG 0x078
     59#define DISPC_SIZE_LCD 0x07C
     60
     61#define DISPC_GFX_BA0 0x080
     62#define DISPC_GFX_BA1 0x084
     63#define DISPC_GFX_POSITION 0x088
     64#define DISPC_GFX_SIZE 0x08C
     65#define DISPC_GFX_ATTRIBUTES 0x0A0
     66#define DISPC_GFX_FIFO_THRESHOLD 0x0A4
     67#define DISPC_GFX_FIFO_SIZE_STATUS 0x0A8
     68#define DISPC_GFX_ROW_INC 0x0AC
     69#define DISPC_GFX_PIXEL_INC 0x0B0
     70#define DISPC_GFX_WINDOW_SKIP 0x0B4
     71#define DISPC_GFX_TABLE_BA 0x0B8
     72
     73#define DISPC_VID1_BA0 0x0BC
     74#define DISPC_VID1_BA1 0x0C0
     75#define DISPC_VID2_BA0 0x14C
     76#define DISPC_VID2_BA1 0x150
     77
     78#define DISPC_VID1_POSITION 0x0C4
     79#define DISPC_VID2_POSITION (0x0C4+0x90)
     80#define DISPC_VID1_SIZE 0x0C8
     81#define DISPC_VID2_SIZE (0x0C8+0x90)
     82#define DISPC_VID1_ATTRIBUTES 0x0CC
     83#define DISPC_VID2_ATTRIBUTES (0x0CC+0x90)
     84
     85#define DISPC_VID1_FIFO_THRESHOLD 0x0D0
     86#define DISPC_VID2_FIFO_THRESHOLD (0x0D0+0x90)
     87#define DISPC_VID1_FIFO_SIZE_STATUS 0x0D4
     88#define DISPC_VID2_FIFO_SIZE_STATUS (0x0D4+0x90)
     89#define DISPC_VID1_ROW_INC 0x0D8
     90#define DISPC_VID2_ROW_INC (0x0D8+0x90)
     91#define DISPC_VID1_PIXEL_INC 0x0DC
     92#define DISPC_VID2_PIXEL_INC (0x0DC+0x90)
     93/*
     94#define DISPC_VIDn_FIR 0x0E0+((n-1)*
     95*/
     96#define DISPC_VID1_PICTURE_SIZE 0x0E4
     97#define DISPC_VID2_PICTURE_SIZE (0x0E4+0x90)
     98/*
     99#define DISPC_VIDn_ACCUl 0x0E8
     100#define DISPC_VIDn_FIR_COEF_Hi 0x0F0+
     101#define DISPC_VIDn_FIR_COEF_HVi 0x0F4+
     102*/
     103#define DISPC_VID1_CONV_COEF0 0x130
     104#define DISPC_VID2_CONV_COEF0 (0x130+0x90)
     105#define DISPC_VID1_CONV_COEF1 0x134
     106#define DISPC_VID2_CONV_COEF1 (0x134+0x90)
     107#define DISPC_VID1_CONV_COEF2 0x138
     108#define DISPC_VID2_CONV_COEF2 (0x138+0x90)
     109#define DISPC_VID1_CONV_COEF3 0x13C
     110#define DISPC_VID2_CONV_COEF3 (0x13C+0x90)
     111#define DISPC_VID1_CONV_COEF4 0x140
     112#define DISPC_VID2_CONV_COEF4 (0x140+0x90)
     113/*
     114#define DISPC_DATA_CYCLEk 0x1D4+((k-1)*
     115#define DISPC_VIDn_FIR_COEF_Vi 0x1E0+
     116*/
     117#define DISPC_CPR_COEF_R 0x220
     118#define DISPC_CPR_COEF_G 0x224
     119#define DISPC_CPR_COEF_B 0x228
     120#define DISPC_GFX_PRELOAD 0x22C
     121#define DISPC_VID1_PRELOAD 0x230
     122#define DISPC_VID2_PRELOAD 0x234
     123
     124/* DISPC_SYSCONFIG bits */
     125#define DISPC_MIDLEMODE_FORCE (0<<12)
     126#define DISPC_MIDLEMODE_NEVER (1<<12)
     127#define DISPC_MIDLEMODE_SMART (2<<12)
     128
     129#define DISPC_SIDLEMODE_FORCE (0<<3)
     130#define DISPC_SIDLEMODE_NEVER (1<<3)
     131#define DISPC_SIDLEMODE_SMART (2<<3)
     132
     133#define DISPC_ENWAKEUP (1<<2)
     134#define DISPC_SOFTRESET (1<<1)
     135#define DISPC_AUTOIDLE (1<<0)
     136
     137/* DISPC_SYSSTATUS bits */
     138#define DISPC_RESETDONE 1
     139
     140/* TODO: IRQ bits */
     141
     142/* DISPC_CONTROL bits (incomplete) */
     143#define DISPC_DITHER_FRAMES_0 (0<<30)
     144#define DISPC_DITHER_FRAMES_2 (1<<30)
     145#define DISPC_DITHER_FRAMES_4 (2<<30)
     146#define DISPC_LCDENABLEPOL (1<<29)
     147#define DISPC_LCDENABLESIGNAL (1<<28)
     148#define DISPC_PCKFREEENABLE (1<<27)
     149#define DISPC_GPOUT1 (1<<16)
     150#define DISPC_GPOUT0 (1<<15)
     151#define DISPC_GPIN1 (1<<14)
     152#define DISPC_GPIN0 (1<<13)
     153#define DISPC_OVERLAYOPTIMISATION (1<<12)
     154#define DISPC_STALLMODE (1<<11)
     155#define DISPC_TFTDATALINES_12 (0<<8)
     156#define DISPC_TFTDATALINES_16 (1<<8)
     157#define DISPC_TFTDATALINES_18 (2<<8)
     158#define DISPC_TFTDATALINES_24 (3<<8)
     159#define DISPC_STDITHERENABLE (1<<7)
     160#define DISPC_GODIGITAL (1<<6)
     161#define DISPC_GOLCD (1<<5)
     162#define DISPC_M8B (1<<4)
     163#define DISPC_STNTFT (1<<3)
     164#define DISPC_MONOCOLOR (1<<2)
     165#define DISPC_DIGITALENABLE (1<<1)
     166#define DISPC_LCDENABLE (1<<0)
     167
     168/* DISPC_CONFIG bits */
     169#define DISPC_TVALPHABLENDERENABLE (1<<19)
     170#define DISPC_LCDALPHABLENDERENABLE (1<<18)
     171#define DISPC_FIFOFILLING (1<<17)
     172#define DISPC_FIFOHANDCHECK (1<<16)
     173#define DISPC_CPR (1<<15)
     174#define DISPC_FIFOMERGE (1<<14)
     175#define DISPC_TCKDIGSELECTION (1<<13)
     176#define DISPC_TCKDIGENABLE (1<<12)
     177#define DISPC_TCKLCDSELECTION (1<<11)
     178#define DISPC_TCKLCDENABLE (1<<10)
     179#define DISPC_FUNCGATED (1<<9)
     180#define DISPC_ACBIASGATED (1<<8)
     181#define DISPC_VSYNCGATED (1<<7)
     182#define DISPC_HSYNCGATED (1<<6)
     183#define DISPC_PIXELCLOCKGATED (1<<5)
     184#define DISPC_PIXELDATAGATED (1<<4)
     185#define DISPC_PALETTEGAMMATABLE (1<<3)
     186#define DISPC_LOADMODE_EVERY (0<<1)
     187#define DISPC_LOADMODE_MANUAL (1<<1)
     188#define DISPC_LOADMODE_FRAME (2<<1)
     189#define DISPC_LOADMODE_FIRST (3<<1)
     190#define DISPC_PIXELGATED 1
     191
     192/* DISPC_TIMING_H bits and masks */
     193#define DISPCB_HBP 20
     194#define DISPCB_HFP 8
     195#define DISPCB_HSW 0
     196#define DISPCM_HBP 0xfff00000
     197#define DISPCM_HFP 0x000fff00
     198#define DISPCM_HSW 0x000000ff
     199
     200/* DISPC_TIMING_V bits and masks */
     201#define DISPCB_VBP 20
     202#define DISPCB_VFP 8
     203#define DISPCB_VSW 0
     204#define DISPCM_VBP 0x0ff00000
     205#define DISPCM_VFP 0x0000ff00
     206#define DISPCM_VSW 0x0000003f
     207
     208/* DISPC_POL_FREQ bits */
     209#define DISPC_POL_ONOFF (1<<17)
     210#define DISPC_POL_RF (1<<16)
     211#define DISPC_POL_IEO (1<<15)
     212#define DISPC_POL_IPC (1<<14)
     213#define DISPC_POL_IHS (1<<13)
     214#define DISPC_POL_IVS (1<<12)
     215#define DISPCB_POL_ACBI 8
     216#define DISPCM_POL_ACBI 0xf00
     217#define DISPCB_POL_ACB 0
     218#define DISPCM_POL_ACB 0xff
     219
     220/* DISPC_DIVISOR bits */
     221#define DISPCB_DIVISOR_LCD 16
     222#define DISPCB_DIVISOR_PCD 0
     223
     224/* DISPC_GFX_ATTRIBUTES bits */
     225#define DISPC_GFXSELFREFRESH (1<<15)
     226#define DISPC_GFXARBITRATION (1<<14)
     227#define DISPC_GFXROTATION_0 (0<<12)
     228#define DISPC_GFXROTATION_90 (1<<12)
     229#define DISPC_GFXROTATION_180 (2<<12)
     230#define DISPC_GFXROTATION_270 (3<<12)
     231#define DISPC_GFXFIFOPRELOAD (1<<11)
     232#define DISPC_GFXENDIANNESS (1<<10)
     233#define DISPC_GFXNIBBLEMODE (1<<9)
     234#define DISPC_GFXCHANNELOUT (1<<8)
     235#define DISPC_GFXBURSTSIZE_4x32 (0<<6)
     236#define DISPC_GFXBURSTSIZE_8x32 (1<<6)
     237#define DISPC_GFXBURSTSIZE_16x32 (2<<6)
     238#define DISPC_GFXREPLICATIONENABLE (1<<5)
     239#define DISPC_GFXFORMAT_BITMAP1 (0<<1)
     240#define DISPC_GFXFORMAT_BITMAP2 (1<<1)
     241#define DISPC_GFXFORMAT_BITMAP4 (2<<1)
     242#define DISPC_GFXFORMAT_BITMAP8 (3<<1)
     243#define DISPC_GFXFORMAT_RGB12 (4<<1)
     244#define DISPC_GFXFORMAT_ARGB16 (5<<1)
     245#define DISPC_GFXFORMAT_RGB16 (6<<1)
     246#define DISPC_GFXFORMAT_RGB32 (8<<1) /* 24 bit, 32-bit un - packed */
     247#define DISPC_GFXFORMAT_RGB24 (9<<1)
     248#define DISPC_GFXFORMAT_ARGB32 (12<<1)
     249#define DISPC_GFXFORMAT_RGBA32 (13<<1)
     250#define DISPC_GFXFORMAT_RGBx (14<<1)
     251#define DISPC_GFXENABLE 1
     252
     253/* DISPC_VIDn_ATTRIBUTES bits */
     254#define DISPC_VIDSELFREFRESH (1<<24)
     255#define DISPC_VIDARBITRATION (1<<23)
     256#define DISPC_VIDLINEBUFFERSPLOT (1<<22)
     257#define DISPC_VIDVERTICALTAPS (1<<21)
     258#define DISPC_VIDOPTIMISATION (1<<20)
     259#define DISPC_VIDFIFOPRELOAD (1<<19)
     260#define DISPC_VIDROWREPEATENABLE (1<<18)
     261#define DISPC_VIDENDIANNESS (1<<17)
     262#define DISPC_VIDCHANNELOUT (1<<16)
     263#define DISPC_VIDBURSTSIZE_4x32 (0<<14)
     264#define DISPC_VIDBURSTSIZE_8x32 (1<<14)
     265#define DISPC_VIDBURSTSIZE_16x32 (2<<14)
     266#define DISPC_VIDROTATION_0 (0<<12)
     267#define DISPC_VIDROTATION_90 (1<<12)
     268#define DISPC_VIDROTATION_180 (2<<12)
     269#define DISPC_VIDROTATION_270 (3<<12)
     270#define DISPC_VIDFULLRANGE (1<<11)
     271#define DISPC_VIDREPLICATIONENABLE (1<<10)
     272#define DISPC_VIDCOLORCONVENABLE (1<<9)
     273#define DISPC_VIDVRESIZECONF (1<<8)
     274#define DISPC_VIDHRESIZECONF (1<<7)
     275#define DISPC_VIDRESIZEENABLE_H (1<<5)
     276#define DISPC_VIDRESIZEENABLE_V (2<<5)
     277#define DISPC_VIDRESIZEENABLE_HV (3<<5)
     278// Only VID2 supports the alpha formats
     279#define DISPC_VIDFORMAT_RGB12 (4<<1)
     280#define DISPC_VIDFORMAT_ARGB16 (5<<1)
     281#define DISPC_VIDFORMAT_RGB16 (6<<1)
     282#define DISPC_VIDFORMAT_RGB32 (8<<1) /* 24 bit, 32-bit un - packed */
     283#define DISPC_VIDFORMAT_RGB24 (9<<1)
     284#define DISPC_VIDFORMAT_YUV2 (10<<1)
     285#define DISPC_VIDFORMAT_UYVY (11<<1)
     286#define DISPC_VIDFORMAT_ARGB32 (12<<1)
     287#define DISPC_VIDFORMAT_RGBA32 (13<<1)
     288#define DISPC_VIDFORMAT_RGBx (14<<1)
     289#define DISPC_VIDENABLE 1
     290
     291/* TODO: video attributes, etc */
     292
     293/* ********************************************************************** */
     294/* S 1.7.5 Video Encoder Registers */
     295
     296#define VENC_BASE 0x48050c00
     297
     298#define VENC_STATUS 0x04
     299#define VENC_F_CONTROL 0x08
     300#define VENC_VIDOUT_CTRL 0x10
     301#define VENC_SYNC_CTRL 0x14
     302#define VENC_LLEN 0x1C
     303#define VENC_FLENS 0x20
     304#define VENC_HFLTR_CTRL 0x24
     305#define VENC_CC_CARR_WSS_CARR 0x28
     306#define VENC_C_PHASE 0x2C
     307#define VENC_GAIN_U 0x30
     308#define VENC_GAIN_V 0x34
     309#define VENC_GAIN_Y 0x38
     310#define VENC_BLACK_LEVEL 0x3C
     311#define VENC_BLANK_LEVEL 0x40
     312#define VENC_X_COLOR 0x44
     313#define VENC_M_CONTROL 0x48
     314#define VENC_BSTAMP_WSS_DATA 0x4C
     315#define VENC_S_CARR 0x50
     316#define VENC_LINE21 0x54
     317#define VENC_LN_SEL 0x58
     318#define VENC_L21_WC_CTL 0x5C
     319#define VENC_HTRIGGER_VTRIGGER 0x60
     320#define VENC_SAVID_EAVID 0x64
     321#define VENC_FLEN_FAL 0x68
     322#define VENC_LAL_PHASE_RESET 0x6C
     323#define VENC_HS_INT_START_STOP_X 0x70
     324#define VENC_HS_EXT_START_STOP_X 0x74
     325#define VENC_VS_INT_START_X 0x78
     326#define VENC_VS_INT_STOP_X_VS_INT_START_Y 0x7C
     327#define VENC_VS_INT_STOP_Y_VS_EXT_START_X 0x80
     328#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y 0x84
     329#define VENC_VS_EXT_STOP_Y 0x88
     330#define VENC_AVID_START_STOP_X 0x90
     331#define VENC_AVID_START_STOP_Y 0x94
     332#define VENC_FID_INT_START_X_FID_INT_START_Y 0xA0
     333#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 0xA4
     334#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 0xA8
     335#define VENC_TVDETGP_INT_START_STOP_X 0xB0
     336#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
     337#define VENC_GEN_CTRL 0xB8
     338#define VENC_OUTPUT_CONTROL 0xC4
     339#define VENC_OUTPUT_TEST 0xC8
     340
     341/* VENC_F_CONTROL bits */
     342#define VENC_RESET (1<<8)
     343#define VENC_SVDS_EXTERNAL (0<<6)
     344#define VENC_SVDS_COLOURBAR (1<<6)
     345#define VENC_SVDS_SOLID (2<<6)
     346#define VENC_RGBF (1<<5)
     347#define VENC_BCOLOR_BLACK (0<<2)
     348#define VENC_BCOLOR_BLUE (1<<2)
     349#define VENC_BCOLOR_RED (2<<2)
     350#define VENC_BCOLOR_MAGENTA (3<<2)
     351#define VENC_BCOLOR_GREEN (4<<2)
     352#define VENC_BCOLOR_CYAN (5<<2)
     353#define VENC_BCOLOR_YELLOW (6<<2)
     354#define VENC_BCOLOR_WHITE (7<<2)
     355#define VENC_FMT_24_RGB444 0
     356#define VENC_FMT_24_444 1
     357#define VENC_FMT_16_422 2
     358#define VENC_FMT_8_422 2
     359
     360/* VENC_VIDOUT_CTRL bits */
     361#define VENC_VIDOUT_54 (0)
     362#define VENC_VIDOUT_27 (1)
     363
     364/* VENC_SYNC_CTRL bits */
     365#define VENC_SYNC_FREE (1<<15)
     366#define VENC_SYNC_ESAV (1<<14)
     367#define VENC_SYNC_IGNP (1<<13)
     368#define VENC_SYNC_NBLNKS (1<<12)
     369#define VENC_SYNC_VBLKM_DFL (0<<10)
     370#define VENC_SYNC_VBLKM_LAL (1<<10)
     371#define VENC_SYNC_HBLKM_DFL (0<<10)
     372#define VENC_SYNC_HBLKM_EAV (1<<10)
     373#define VENC_SYNC_HBLKM_RANGE (2<<10)
     374#define VENC_SYNC_FID_POL (1<<6)
     375
     376/* VENC_HFLTR_CTRL bits */
     377#define VENC_CINTP_EN (0<<1)
     378#define VENC_CINTP_BYPASS_1 (1<<1)
     379#define VENC_CINTP_BYPASS_2 (2<<1)
     380#define VENC_CINTP_BYPASS (3<<1)
     381
     382#define VENC_YINTP_EN (0<<0)
     383#define VENC_YINTP_BYPASS (1<<0)
     384
     385/* VENC_CC_CARR_WSS_CARR bits */
     386#define VENCB_FWSS 16
     387#define VENCB_FCC 0
     388
     389/* VENC_X_COLOR bits */
     390#define VENC_XCE (1<<6)
     391#define VENC_XCBW_32_8 (0<<3)
     392#define VENC_XCBW_26_5 (1<<3)
     393#define VENC_XCBW_30_0 (2<<3)
     394#define VENC_XCBW_29_2 (3<<3)
     395#define VENC_LCD_0_0 0
     396#define VENC_LCD_0_5 1
     397#define VENC_LCD_1_0 2
     398#define VENC_LCD_1_5 3
     399#define VENC_LCD_m2_0 4
     400#define VENC_LCD_m1_5 5
     401#define VENC_LCD_m1_0 6
     402#define VENC_LCD_m0_5 7
     403
     404/* VENC_M_CONTROL bits */
     405#define VENC_M_PALI (1<<7)
     406#define VENC_M_PALN (1<<6)
     407#define VENC_M_PALPHS (1<<5)
     408#define VENC_M_CBW_21_8 (0<<2)
     409#define VENC_M_CBW_19_8 (1<<2)
     410#define VENC_M_CBW_18_0 (2<<2)
     411#define VENC_M_CBW_23_7 (5<<2)
     412#define VENC_M_CBW_26_8 (6<<2)
     413#define VENC_M_CBW_BYPASS (7<<2)
     414#define VENC_M_PAL (1<<1)
     415#define VENC_M_NTSC (1<<0)
     416
     417/* VENC_BSTAMP_WSS_DATA bits */
     418#define VENCB_WSS_DATA (8)
     419#define VENC_SQP (1<<7)
     420
     421/* VENC_S_CARR values - presets assuming Fclkenc = 27Mhz */
     422#define VENC_FSC_R601_NTSC_M 0x21F07C1F
     423#define VENC_FSC_R601_PAL_M 0x21E6EFE3
     424#define VENC_FSC_R601_PAL_G 0x2A098ACB
     425#define VENC_FSC_R601_PAL_Nc 0x21E6EFE3
     426
     427#endif