Ticket #8954: 0001-XHCI-Fixes.patch

src/add-ons/kernel/bus_managers/usb/Hub.cpp

@@ -17 +17 @@
 
 Hub::Hub(Object *parent, int8 hubAddress, uint8 hubPort,
     usb_device_descriptor &desc, int8 deviceAddress, usb_speed speed,
-    bool isRootHub)
+    bool isRootHub, void *controllerCookie)
     :   Device(parent, hubAddress, hubPort, desc, deviceAddress, speed,
-            isRootHub),
+            isRootHub, controllerCookie),
         fInterruptPipe(NULL)
 {
     TRACE("creating hub\n");

src/add-ons/kernel/bus_managers/usb/Stack.cpp

@@ -61 +61 @@
     // be enumerated as the last item. As this does not apply to us we have to
     // ensure ordering using another method.
     const char *moduleNames[] = {
+        "busses/usb/xhci",
         "busses/usb/uhci",
         "busses/usb/ohci",
         "busses/usb/ehci",
-        "busses/usb/xhci",
         NULL
     };
 

src/add-ons/kernel/bus_managers/usb/usb_private.h

@@ -579 +579 @@
                                             uint8 hubPort,
                                             usb_device_descriptor &desc,
                                             int8 deviceAddress,
-                                            usb_speed speed, bool isRootHub);
+                                            usb_speed speed, bool isRootHub,
+                                            void *controllerCookie = NULL);
 virtual                                 ~Hub();
 
 virtual status_t                        Changed(change_item **changeList,

src/add-ons/kernel/busses/usb/xhci.cpp

@@ -8 +8 @@
  *      Michael Lotz <mmlr@mlotz.ch>
  *      Jian Chiang <j.jian.chiang@gmail.com>
  *      Jérôme Duval <jerome.duval@gmail.com>
+ *      Akshay Jaggi <akshay1994.leo@gmail.com>
  */
 
 
@@ -174 +175 @@
 
     uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH);
     fCapabilityRegisters += offset;
+    fCapabilityLength = HCI_CAPLENGTH(hciCapLength);
     TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength);
-    fOperationalRegisters = fCapabilityRegisters + HCI_CAPLENGTH(hciCapLength);
+    fOperationalRegisters = fCapabilityRegisters + fCapabilityLength;
     fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF);
     fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF);
     TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters);
@@ -199 +201 @@
         eec = ReadCapReg32(eecp);
         if (XECP_ID(eec) != XHCI_LEGSUP_CAPID)
             continue;
-    }
-    TRACE("eecp register: 0x%04" B_PRIx32 "\n", eecp);
-    if (eec & XHCI_LEGSUP_BIOSOWNED) {
-        TRACE_ALWAYS("the host controller is bios owned, claiming"
-            " ownership\n");
-        WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED);
-
-        for (int32 i = 0; i < 20; i++) {
-            eec = ReadCapReg32(eecp);
-
-            if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0)
-                break;
-
-            TRACE_ALWAYS("controller is still bios owned, waiting\n");
-            snooze(50000);
-        }
-
+                
+        TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp);
         if (eec & XHCI_LEGSUP_BIOSOWNED) {
-            TRACE_ERROR("bios won't give up control over the host "
-                "controller (ignoring)\n");
-        } else if (eec & XHCI_LEGSUP_OSOWNED) {
-            TRACE_ALWAYS("successfully took ownership of the host "
-                "controller\n");
+            TRACE_ALWAYS("the host controller is bios owned, claiming"
+                " ownership\n");
+            WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED);
+    
+            for (int32 i = 0; i < 20; i++) {
+                eec = ReadCapReg32(eecp);
+    
+                if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0)
+                    break;
+    
+                TRACE_ALWAYS("controller is still bios owned, waiting\n");
+                snooze(50000);
+            }
+    
+            if (eec & XHCI_LEGSUP_BIOSOWNED) {
+                TRACE_ERROR("bios won't give up control over the host "
+                    "controller (ignoring)\n");
+            } else if (eec & XHCI_LEGSUP_OSOWNED) {
+                TRACE_ALWAYS("successfully took ownership of the host "
+                    "controller\n");
+            }
+    
+            // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes
+            // do indicate a successful handover but do not remove their SMIs
+            // and then freeze the system when interrupts are generated.
+            WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED);
         }
-
-        // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes
-        // do indicate a successful handover but do not remove their SMIs
-        // and then freeze the system when interrupts are generated.
-        WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED);
+        break;
+    }
+    uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS);
+    legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI;
+    legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI;
+    WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts);
+
+    // On Intel's Panther Point and Lynx Point Chipset taking ownership 
+    // of EHCI owned ports, is what we do here.
+    if(fPCIInfo->vendor_id == PCI_VENDOR_ID_INTEL 
+        && (fPCIInfo->device_id == PCI_DEVICE_ID_INTEL_PANTHER_POINT_XHCI
+            || fPCIInfo->device_id == PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI
+            || fPCIInfo->device_id == PCI_DEVICE_ID_INTEL_LYNX_POINT_LP_XHCI)) {
+        
+        TRACE("Intel xHC Controller\n");
+        TRACE("Looking for EHCI owned ports\n");
+        
+        uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus,
+            fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4);
+        
+        TRACE("Superspeed Ports: 0x%"B_PRIx32"\n", ports);
+        
+        sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
+            fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports);
+        
+        ports = sPCIModule->read_pci_config(fPCIInfo->bus,
+            fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4);
+        
+        TRACE("Superspeed ports now under XHCI : 0x%"B_PRIx32"\n", ports);
+            
+        ports = sPCIModule->read_pci_config(fPCIInfo->bus,
+            fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4);
+            
+        TRACE("USB 2.0 Ports : 0x%"B_PRIx32"\n", ports);
+            
+        sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
+            fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports);
+            
+        ports = sPCIModule->read_pci_config(fPCIInfo->bus,
+            fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4);
+            
+        TRACE("USB 2.0 ports now under XHCI: 0x%"B_PRIx32"\n", ports);
     }
-    WriteCapReg32(eecp + XHCI_LEGCTLSTS, XHCI_LEGCTLSTS_DISABLE_SMI);
 
     // halt the host controller
     if (ControllerHalt() < B_OK) {
@@ -337 +381 @@
     }
 
     // read port count from capability register
-    uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1);
-
+    uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1);    
     fPortCount = HCS_MAX_PORTS(capabilities);
     if (fPortCount == 0) {
         TRACE_ERROR("Invalid number of ports: %u\n", fPortCount);
@@ -574 +617 @@
     xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie();
     uint8 id = XHCI_ENDPOINT_ID(pipe);
     if (id >= XHCI_MAX_ENDPOINTS)
+    {
+        TRACE_ERROR("Invalid Endpoint");
         return B_BAD_VALUE;
+    }
     setupDescriptor->transfer = transfer;
+    transfer->InitKernelAccess();
     _LinkDescriptorForPipe(setupDescriptor, endpoint);
 
     TRACE("SubmitControlRequest() request linked\n");
 
+    TRACE("Endpoint Status 0x%"B_PRIx32" 0x%"B_PRIx32" 0x%"B_PRIx64"\n", 
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint0,
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
+        endpoint->device->device_ctx->endpoints[id-1].qwendpoint2
+        );
     Ring(endpoint->device->slot, id);
-
+    TRACE("Endpoint Status 0x%"B_PRIx32" 0x%"B_PRIx32" 0x%"B_PRIx64"\n", 
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint0,
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
+        endpoint->device->device_ctx->endpoints[id-1].qwendpoint2
+        );
     return B_OK;
 }
 
@@ -625 +681 @@
 
     xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie();
     descriptor->transfer = transfer;
+    transfer->InitKernelAccess();
     _LinkDescriptorForPipe(descriptor, endpoint);
 
     TRACE("SubmitNormalRequest() request linked\n");
 
+    TRACE("Endpoint Status 0x%"B_PRIx32" 0x%"B_PRIx32" 0x%"B_PRIx64"\n", 
+        (endpoint->device->device_ctx->endpoints[id-1]).dwendpoint0,
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
+        endpoint->device->device_ctx->endpoints[id-1].qwendpoint2
+        );
     Ring(endpoint->device->slot, id);
+    TRACE("Endpoint Status 0x%"B_PRIx32" 0x%"B_PRIx32" 0x%"B_PRIx64"\n", 
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint0,
+        endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
+        endpoint->device->device_ctx->endpoints[id-1].qwendpoint2
+        );
 
     return B_OK;
 }
@@ -994 +1061 @@
         "XHCI input context");
     if (device->input_ctx_area < B_OK) {
         TRACE_ERROR("unable to create a input context area\n");
+        device->state = XHCI_STATE_DISABLED;
         return NULL;
     }
 
@@ -1003 +1071 @@
 
     uint32 route = 0;
     uint8 routePort = hubPort;
-    uint8 rhPort = 0;
+    uint8 rhPort = hubPort;
     for (Device *hubDevice = parent; hubDevice != RootObject();
         hubDevice = (Device *)hubDevice->Parent()) {
 
@@ -1020 +1088 @@
     }
 
     device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route);
-    //device->input_ctx->slot.dwslot0 =
-    //  SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1) | SLOT_0_ROUTE(route);
 
     // add the speed
     switch (speed) {
@@ -1059 +1125 @@
         "XHCI device context");
     if (device->device_ctx_area < B_OK) {
         TRACE_ERROR("unable to create a device context area\n");
+        device->state = XHCI_STATE_DISABLED;        
         delete_area(device->input_ctx_area);
         return NULL;
     }
     memset(device->device_ctx, 0, sizeof(*device->device_ctx));
 
     device->trb_area = fStack->AllocateArea((void **)&device->trbs,
-        &device->trb_addr, sizeof(*device->trbs), "XHCI endpoint trbs");
+        &device->trb_addr, sizeof(*device->trbs)*(XHCI_MAX_ENDPOINTS-1)*(XHCI_MAX_TRANSFERS), "XHCI endpoint trbs");
     if (device->trb_area < B_OK) {
         TRACE_ERROR("unable to create a device trbs area\n");
+        device->state = XHCI_STATE_DISABLED;
         delete_area(device->input_ctx_area);
         delete_area(device->device_ctx_area);
         return NULL;
@@ -1102 +1170 @@
     if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1, 1, 0,
         maxPacketSize, maxPacketSize, speed) != B_OK) {
         TRACE_ERROR("unable to configure default control endpoint\n");
+        device->state = XHCI_STATE_DISABLED;
+        delete_area(device->input_ctx_area);
+        delete_area(device->device_ctx_area);
+        delete_area(device->trb_area);
         return NULL;
     }
 
@@ -1116 +1188 @@
     // device should get to addressed state (bsr = 0)
     if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) {
         TRACE_ERROR("unable to set address\n");
+        device->state = XHCI_STATE_DISABLED;
+        delete_area(device->input_ctx_area);
+        delete_area(device->device_ctx_area);
+        delete_area(device->trb_area);
         return NULL;
     }
 
@@ -1154 +1230 @@
 
     if (actualLength != 8) {
         TRACE_ERROR("error while getting the device descriptor\n");
+        device->state = XHCI_STATE_DISABLED;
+        delete_area(device->input_ctx_area);
+        delete_area(device->device_ctx_area);
+        delete_area(device->trb_area);
         return NULL;
     }
 
@@ -1161 +1241 @@
         deviceDescriptor.device_class, deviceDescriptor.device_subclass,
         deviceDescriptor.device_protocol);
 
+    if(deviceDescriptor.device_class==0x09)
+    {
+        TRACE("creating new HUB\n");
+        TRACE("getting the hub descriptor\n");
+        size_t actualLength = 0;
+        usb_hub_descriptor hubDescriptor;
+        pipe.SendRequest(
+            USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD,       // type
+            USB_REQUEST_GET_DESCRIPTOR,                         // request
+            USB_DESCRIPTOR_HUB << 8,                            // value
+            0,                                                  // index
+            sizeof(usb_hub_descriptor),                         // length
+            (void *)&hubDescriptor,                             // buffer
+            sizeof(usb_hub_descriptor),                         // buffer length
+            &actualLength);
+        
+        if(actualLength!=sizeof(usb_hub_descriptor))
+        {
+            TRACE_ERROR("error while getting the hub descriptor\n");
+            device->state = XHCI_STATE_DISABLED;
+            delete_area(device->input_ctx_area);
+            delete_area(device->device_ctx_area);
+            delete_area(device->trb_area);
+            return NULL;
+        }
+        
+        device->input_ctx->slot.dwslot0 |= SLOT_0_HUB_BIT;
+        device->input_ctx->slot.dwslot1 |= SLOT_1_NUM_PORTS(hubDescriptor.num_ports);
+        if(speed == USB_SPEED_HIGHSPEED)
+        {
+            device->input_ctx->slot.dwslot2 |= SLOT_2_TT_TIME(HUB_TTT_GET(hubDescriptor.characteristics)); 
+        }
+        
+        Hub *hub = new(std::nothrow) Hub(parent, hubAddress, hubPort,
+            deviceDescriptor, device->address + 1, speed, false, device);
+        if(!hub)
+        {
+            TRACE_ERROR("no memory to allocate hub\n");
+            device->state = XHCI_STATE_DISABLED;
+            delete_area(device->input_ctx_area);
+            delete_area(device->device_ctx_area);
+            delete_area(device->trb_area);
+            return NULL;
+        }
+        fPortSlots[hubPort] = slot;
+        TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot);
+        return (Device *)hub;
+    }
     TRACE("creating new device\n");
     Device *deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort,
         deviceDescriptor, device->address + 1, speed, false, device);
     if (!deviceObject) {
         TRACE_ERROR("no memory to allocate device\n");
+        device->state = XHCI_STATE_DISABLED;
+        delete_area(device->input_ctx_area);
+        delete_area(device->device_ctx_area);
+        delete_area(device->trb_area);
         return NULL;
     }
     fPortSlots[hubPort] = slot;
@@ -1193 +1325 @@
 status_t
 XHCI::_InsertEndpointForPipe(Pipe *pipe)
 {
+    TRACE("_InsertEndpointForPipe endpoint address %"B_PRId8"\n", pipe->EndpointAddress());
     if (pipe->ControllerCookie() != NULL
         || pipe->Parent()->Type() != USB_OBJECT_DEVICE) {
         // default pipe is already referenced
@@ -1278 +1411 @@
         TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id,
             ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0));
         device->state = XHCI_STATE_CONFIGURED;
+        
     }
     pipe->SetControllerCookie(&device->endpoints[id]);
 
@@ -1304 +1438 @@
     TRACE("_LinkDescriptorForPipe\n");
     MutexLocker endpointLocker(endpoint->lock);
     if (endpoint->used >= XHCI_MAX_TRANSFERS)
+    {
+        TRACE_ERROR("MISS-FIRE MISS-FIRE\n");
         return B_BAD_VALUE;
+    }
 
     endpoint->used++;
     if (endpoint->td_head == NULL)
@@ -1468 +1605 @@
 
     status->status = status->change = 0;
     uint32 portStatus = ReadOpReg(XHCI_PORTSC(index));
-    //TRACE("port status=0x%08lx\n", portStatus);
+    TRACE("port %" B_PRId8 " status=0x%08" B_PRIx32 "\n", index, portStatus);
 
     // build the status
     switch (PS_SPEED_GET(portStatus)) {
@@ -1767 +1904 @@
 {
     TRACE("HandleTransferComplete trb %p\n", trb);
     addr_t source = trb->qwtrb0;
-    //uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2);
-    //uint32 remainder = TRB_2_REM_GET(trb->dwtrb2);
+    uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2);
+    uint32 remainder = TRB_2_REM_GET(trb->dwtrb2);
     uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3);
     uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3);
 
@@ -1785 +1922 @@
             offset);
         (void)offset;
         _UnlinkDescriptorForPipe(td, endpoint);
-
+        td->trb_completion_code = completionCode;
+        td->trb_left = remainder;
         // add descriptor to finished list (to be processed and freed)
         Lock();
         td->next = fFinishedHead;
@@ -1838 +1976 @@
 status_t
 XHCI::Noop()
 {
+    TRACE("Noop\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -1850 +1989 @@
 status_t
 XHCI::EnableSlot(uint8 *slot)
 {
+    TRACE("Enable Slot\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -1867 +2007 @@
 status_t
 XHCI::DisableSlot(uint8 slot)
 {
+    TRACE("Disable Slot\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -1879 +2020 @@
 status_t
 XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot)
 {
+    TRACE("Set Address\n");
     xhci_trb trb;
     trb.qwtrb0 = inputContext;
     trb.dwtrb2 = 0;
@@ -1894 +2036 @@
 status_t
 XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot)
 {
+    TRACE("Configure Endpoint\n");
     xhci_trb trb;
     trb.qwtrb0 = inputContext;
     trb.dwtrb2 = 0;
@@ -1909 +2052 @@
 status_t
 XHCI::EvaluateContext(uint64 inputContext, uint8 slot)
 {
+    TRACE("Evaluate Context\n");
     xhci_trb trb;
     trb.qwtrb0 = inputContext;
     trb.dwtrb2 = 0;
@@ -1921 +2065 @@
 status_t
 XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot)
 {
+    TRACE("Reset Endpoint\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -1936 +2081 @@
 status_t
 XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot)
 {
+    TRACE("Stop Endpoint\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -1951 +2097 @@
 status_t
 XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot)
 {
+    TRACE("Set TR Dequeue\n");
     xhci_trb trb;
     trb.qwtrb0 = dequeue;
     trb.dwtrb2 = TRB_2_STREAM(stream);
@@ -1964 +2111 @@
 status_t
 XHCI::ResetDevice(uint8 slot)
 {
+    TRACE("Reset Device\n");
     xhci_trb trb;
     trb.qwtrb0 = 0;
     trb.dwtrb2 = 0;
@@ -2000 +2148 @@
 
         while (1) {
             uint32 temp = fEventRing[i].dwtrb3;
+            TRACE_ALWAYS("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08"
+                B_PRIx32 ")\n", i, (uint8)TRB_3_TYPE_GET(temp), fEventRing[i].qwtrb0,
+                fEventRing[i].dwtrb2, fEventRing[i].dwtrb3);
             uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0;
             if (j != k)
                 break;
@@ -2073 +2224 @@
             td->next = NULL;
             Unlock();
 
+            TRACE("finishing transfer td %p\n", td);
+            
             Transfer* transfer = td->transfer;
             bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out);
             usb_request_data *requestData = transfer->RequestData();
-
-            // TODO check event
+            
             status_t callbackStatus = B_OK;
-            size_t actualLength = requestData ? requestData->Length
-                : transfer->DataLength();
-            TRACE("finishing transfer td %p\n", td);
-            if (directionIn && actualLength > 0) {
-                if (requestData) {
-                    TRACE("copying in data %d bytes\n", requestData->Length);
-                    memcpy((uint8 *)transfer->Vector()[0].iov_base,
-                        td->buffer_log[0], requestData->Length);
-                } else {
-                    TRACE("copying in iov count %ld\n", transfer->VectorCount());
-                    ReadDescriptorChain(td, transfer->Vector(),
-                        transfer->VectorCount());
+            switch(td->trb_completion_code)
+            {
+                case COMP_SHORT_PACKET:
+                case COMP_SUCCESS:
+                    callbackStatus = B_OK;
+                    break;
+                case COMP_DATA_BUFFER:
+                    callbackStatus = directionIn ? B_DEV_DATA_OVERRUN : B_DEV_DATA_UNDERRUN;
+                    break;
+                case COMP_BABBLE:
+                    callbackStatus = directionIn ? B_DEV_FIFO_OVERRUN : B_DEV_FIFO_UNDERRUN;
+                    break;
+                case COMP_USB_TRANSACTION:
+                    callbackStatus = B_DEV_CRC_ERROR;
+                    break;
+                case COMP_STALL:
+                    callbackStatus = B_DEV_STALLED;
+                    break;
+                default:
+                    callbackStatus = B_DEV_STALLED;
+                    break;
+            }
+            
+            size_t actualLength = 0;
+            
+            if(callbackStatus == B_OK)
+            {
+                actualLength = requestData ? requestData->Length
+                    : transfer->DataLength();
+                    
+                if(td->trb_completion_code == COMP_SHORT_PACKET)
+                    actualLength -= td->trb_left;
+    
+                if (directionIn && actualLength > 0) {
+                    if (requestData) {
+                        TRACE("copying in data %d bytes\n", requestData->Length);
+                        transfer->PrepareKernelAccess();
+                        memcpy((uint8 *)transfer->Vector()[0].iov_base,
+                            td->buffer_log[0], requestData->Length);
+                    } else {
+                        TRACE("copying in iov count %ld\n", transfer->VectorCount());
+                        transfer->PrepareKernelAccess();
+                        ReadDescriptorChain(td, transfer->Vector(),
+                            transfer->VectorCount());
+                    }
                 }
             }
-            transfer->Finished(callbackStatus, actualLength);
-
+            transfer->Finished(callbackStatus, actualLength);                       
+            delete transfer;
             FreeDescriptor(td);
             Lock();
         }

src/add-ons/kernel/busses/usb/xhci.h

@@ -45 +45 @@
     struct xhci_td  *next;
     Transfer *transfer;
     uint8   trb_count;
+    uint8   trb_completion_code;
+    uint32  trb_left;
 } xhci_td __attribute__((__aligned__(16)));
 
 

src/add-ons/kernel/busses/usb/xhci_hardware.h

@@ -5 +5 @@
  * Authors:
  *      Jian Chiang <j.jian.chiang@gmail.com>
  *      Jérôme Duval <jerome.duval@gmail.com>
+ *      Akshay Jaggi <akshay1994.leo@gmail.com>
  */
 #ifndef XHCI_HARDWARE_H
 #define XHCI_HARDWARE_H
 
+// Intel quirks
+#define XHCI_INTEL_USB3PRM                      0xDC    // USB 3.0 Port Routing Mask
+#define XHCI_INTEL_USB3_PSSEN                   0xD8    // USB 3.0 Port SuperSpeed Enable
+#define XHCI_INTEL_USB2PRM                      0xD4    // USB 2.0 Port Routing Mask
+#define XHCI_INTEL_XUSB2PR                      0xD0    // USB 2.0 Port Routing
+#define PCI_DEVICE_ID_INTEL_PANTHER_POINT_XHCI  0x1E31
+#define PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI     0x8C31
+#define PCI_DEVICE_ID_INTEL_LYNX_POINT_LP_XHCI  0x9C31
+#define PCI_VENDOR_ID_INTEL                     0x8086
 
 // Host Controller Capability Registers
 #define XHCI_HCI_CAPLENGTH  0x00        // HCI Capability Register Length
@@ -17 +27 @@
 #define XHCI_HCSPARAMS1     0x04        // Structural Parameters 1
 // HCSPARAMS1
 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
-#define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
+#define HCS_MAX_PORTS(p)        (((p) >> 24) & 0xff)
 #define XHCI_HCSPARAMS2     0x08        // Structural Parameters 2
 #define HCS_IST(p)              (((p) >> 0) & 0xf)
 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
 #define HCS_SPR(p)              (((p) >> 26) & 0x1)
-#define HCS_MAX_SC_BUFFERS(p)   (((p) >> 27) & 0x1f)
+#define HCS_MAX_SC_BUFFERS(p)   (((((p) >> 21) & 0x1f)<<5)|(((p) >> 27) & 0x1f))
 #define XHCI_HCSPARAMS3     0x0C        // Structural Parameters 3
 #define HCS_U1_DEVICE_LATENCY(p)    (((p) >> 0) & 0xff)
 #define HCS_U2_DEVICE_LATENCY(p)    (((p) >> 16) & 0xffff)
@@ -98 +108 @@
 #define XHCI_LEGSUP_BIOSOWNED   (1 << 16)   // BIOS Owned Semaphore
 
 #define XHCI_LEGCTLSTS          0x04
-#define XHCI_LEGCTLSTS_DISABLE_SMI  ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
+#define XHCI_LEGCTLSTS_DISABLE_SMI  ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
+#define XHCI_LEGCTLSTS_EVENTS_SMI (0x7 << 29)
 
 #define XHCI_SUPPORTED_PROTOCOLS_CAPID  0x02
 #define XHCI_SUPPORTED_PROTOCOLS_0_MINOR(x) (((x) >> 16) & 0xff)
@@ -336 +347 @@
 #define SLOT_2_PORT_NUM_GET(x)          (((x) >> 8) & 0xFF)
 #define SLOT_2_TT_TIME(x)               (((x) & 0x3) << 16)
 #define SLOT_2_TT_TIME_GET(x)           (((x) >> 16) & 0x3)
-#define SLOT_2_IRQ_TARGET(x)                (((x) & 0x1F) << 27)
-#define SLOT_2_IRQ_TARGET_GET(x)            (((x) >> 27) & 0x1f)
+#define SLOT_2_IRQ_TARGET(x)                (((x) & 0x7F) << 22)
+#define SLOT_2_IRQ_TARGET_GET(x)            (((x) >> 22) & 0x7F)
 
 #define SLOT_3_DEVICE_ADDRESS(x)        ((x) & 0xFF)
 #define SLOT_3_DEVICE_ADDRESS_GET(x)    ((x) & 0xFF)
 #define SLOT_3_SLOT_STATE(x)            (((x) & 0x1F) << 27)
 #define SLOT_3_SLOT_STATE_GET(x)        (((x) >> 27) & 0x1F)
 
+#define HUB_TTT_GET(x)                  (((x) >> 5) & 0x3)
 
 struct xhci_endpoint_ctx {
     uint32  dwendpoint0;