Changes between Initial Version and Version 1 of Ticket #11619, comment 14


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Timestamp:
May 31, 2015, 2:26:18 AM (9 years ago)
Author:
edglex

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  • Ticket #11619, comment 14

    initial v1  
    1 I think that the offset for the extended capabilities pointer is wrong, this seems to be the only reason why the reads and writes would fail: in PCI::ReadConfig and WriteConfig we have (size == 4 && (offset & 3) != 0) as a condition for failure without even to make a read/write. So extendedCapPointer should not be 0xFF/255 as it is (see the read failure in "these lines are of interest" comment above).
     1I think that the offset for the extended capabilities pointer is wrong, this seems to be the only reason why the reads and writes would fail: in PCI::ReadConfig and WriteConfig we have (size == 4 && (offset & 3) != 0) as a condition for failure without even atempting to make a read/write. So extendedCapPointer should not be 0xFF/255 as it is (see the read failure in "these lines are of interest" comment above).
    22
    33I suspect that if this is corrected the writes to disable interrupts/BIOS control may work and then the controller might reset correctly. However at the moment I have no idea why the offset would be wrong (or even if I am just barking up the wrong tree).