| | 1 | Technical notes on Radeon HD, straight from AMD engineers. I am mostly documenting this to avoid the bus factor... |
| | 2 | |
| | 3 | '''Radeon HD mode setting:''' |
| | 4 | {{{ |
| | 5 | There are two basic parts we generally work with when programming the display hardware, the crtc and the encoder. |
| | 6 | The crtc is basically a display controller and covers the display fb offset, the timing, and the pll setup. |
| | 7 | The encoder is the part that takes the bit stream from the crtc and formats it for the proper electrical signal for |
| | 8 | the connected monitor (TMDS, LVDS, DAC, DP, etc.). It's probably easiest to look at the ATOM tables using AtomDis |
| | 9 | (more on this below) and follow the same pattern in your driver. Follow atombios_crtc_mode_set() and radeon_atom_encoder_mode_set() |
| | 10 | in the drm. Basically the modeset sequence looks like: |
| | 11 | |
| | 12 | Disable encoder (dpms off) |
| | 13 | Disable crtc (dpms off) |
| | 14 | Set up the crtc to encoder routing |
| | 15 | Program the pll |
| | 16 | Program spread spectrum if applicable |
| | 17 | Program mode timing |
| | 18 | Program the crtc base address |
| | 19 | Program the overscan registers |
| | 20 | Program the scaler |
| | 21 | Program the encoder |
| | 22 | Enable the crtc (dpms on) |
| | 23 | Enable the encoder (dpms on) |
| | 24 | |
| | 25 | Note that the pll provides the pixclock for the crtc and the link clocks for the encoders, so it needs to be programmed for all displays. |
| | 26 | For displayport on evergreen and newer asics, multiple displays can be driven by the same pll due to the way DP clocking works. |
| | 27 | }}} |
| | 28 | |
| | 29 | |
