Changes between Version 6 and Version 7 of HardwareInfo/video/RadeonHD_tech


Ignore:
Timestamp:
Aug 9, 2012, 1:26:29 PM (7 years ago)
Author:
kallisti5
Comment:

update PLL usage info

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  • HardwareInfo/video/RadeonHD_tech

    v6 v7  
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     83'''Assigning phase locked loops'''
     84Radeon HD cards can have several PLL clock sources. Some PLL sources can only be used for certain encoders.
     85  * DCE3.x: DP == PLL1 or PLL2, non-DP == PLL1 or PLL2
     86  * DCE4.0: DP == EXT_PLL or PLL1 or PLL2, non-DP == PLL1 or PLL2
     87  * DCE4.1: DP == PLL1 or PLL2, non-DP == PLL1 or PLL2
     88  * DCE5.0: DP == DCPLL or PLL1 or PLL2, non-DP == PLL1 or PLL2
     89  * DCE6.0: DP == PLL0 or PLL1 or PLL2, non-DP == PLL1 or PLL2
     90    * I think you might be able to use PLL0 as an independent PLL on DCE6.0 as well, but I don't think it was validated in hw so it may not work correctly depends on the DCE family
     91  * DCE6.1: DP == PLL0 or PLL1 (PHY BCDEF) or PLL2 (PHY A), non-DP == PLL0 or PLL1 (PHY BCDEF) or PLL2 (PHY A)
     92
    8393'''Calculating phase locked loops'''
    8494PLL (Phase locked loop) is an electronic device to generate a programmable clock frequency. PLL computations can be *complex*... here is the simplified version which may apply to other video cards: