Ticket #12955: nvidia.10de_0240_000500.0.11.log

File nvidia.10de_0240_000500.0.11.log, 58.9 KB (added by vidrep, 4 years ago)
Line 
1ACCELERANT_MODE_COUNT: the modelist contains 240 modes
2GET_MODE_LIST: exporting the modelist created before.
3GET_ACCELERANT_DEVICE_INFO: returning info
4PROPOSEMODE: Haiku screenprefs tunnel detected.
5Haiku: tunnel access target=swap, command=get, value=0
6Haiku: tunnel access target=usepanel, command=get, value=0
7Haiku: tunnel access target=tvstandard, command=get, value=0
8Haiku: tunnel access target=swap, command=get, value=0
9Haiku: tunnel access target=usepanel, command=get, value=0
10Haiku: tunnel access target=tvstandard, command=get, value=0
11GET_EDID_INFO: returning info
12Haiku: tunnel access target=usepanel, command=get, value=0
13Haiku: tunnel access target=tvstandard, command=get, value=0
14Haiku: tunnel access target=tvstandard, command=get, value=0
15GET_EDID_INFO: returning info
16Haiku: tunnel access target=swap, command=get, value=0
17Haiku: tunnel access target=usepanel, command=get, value=0
18Haiku: tunnel access target=tvstandard, command=get, value=0
19GET_EDID_INFO: returning info
20GET_ACCELERANT_DEVICE_INFO: returning info
21GET_EDID_INFO: returning info
22Haiku: tunnel access target=swap, command=get, value=0
23Haiku: tunnel access target=usepanel, command=get, value=0
24Haiku: tunnel access target=tvstandard, command=get, value=0
25Haiku: tunnel access target=swap, command=set, value=0
26SETMODE: (ENTER) initial modeflags: $0000015f
27SETMODE: requested target pixelclock 147222kHz
28SETMODE: requested virtual_width 1680, virtual_height 1050
29PROPOSEMODE: (ENTER) requested virtual_width 1680, virtual_height 1050
30INIT: memory pitch will be set to 1680 pixels for colorspace 0x00000008
31DAC: NV4/NV10/NV20 restrictions apply
32DAC: pix VCO frequency found 588.888889Mhz
33DAC: pix PLL check: requested 147.220993MHz got 147.222229MHz, mnp 0x09 0x35 0x02
34PROPOSEMODE: validated virtual_width 1680, virtual_height 1050 pixels
35PROPOSEMODE: initial modeflags: $0000015f
36PROPOSEMODE: validated modeflags: $0000015f
37PROPOSEMODE: completed successfully.
38CRTC: setting DPMS: display off, hsync disabled, vsync disabled
39CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
40INIT: memory pitch will be set to 1680 pixels for colorspace 0x00000008
41SETMODE: setting DUALHEAD mode
42INIT: switching CRTC/DAC use to be straight-through
43SETMODE: target clock 147222kHz
44DAC: NV4/NV10/NV20 restrictions apply
45DAC: pix VCO frequency found 588.888889Mhz
46DAC: pix PLL check: requested 147.222000MHz got 147.222229MHz, mnp 0x09 0x35 0x02
47DAC: dumping current pixelPLL settings:
48DAC: divider1 settings ($00023509): M1=9, N1=53, P1=4
49DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
50DAC: phase discriminator frequency is 2.777778Mhz
51DAC: VCO frequency is 588.888889Mhz
52DAC: pixelclock is 147.222229Mhz
53DAC: end of dump.
54DAC: current NV30_PLLSETUP settings: $00000000
55DAC: current (0x0000c040) settings: $340bc003
56DAC: Setting PIX PLL for pixelclock 147.222000
57DAC: PIX PLL frequency should be locked now...
58SETMODE: target2 clock 147222kHz
59DAC2: NV10/NV20 restrictions apply
60DAC2: pix VCO frequency found 588.888889Mhz
61DAC2: pix PLL check: requested 147.222000MHz got 147.222229MHz, mnp 0x09 0x35 0x02
62DAC2: dumping current pixelPLL settings:
63DAC2: divider1 settings ($00023509): M1=9, N1=53, P1=4
64DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
65DAC2: phase discriminator frequency is 2.777778Mhz
66DAC2: VCO frequency is 588.888889Mhz
67DAC2: pixelclock is 147.222229Mhz
68DAC2: end of dump.
69DAC2: current NV30_PLLSETUP settings: $00000000
70DAC2: current (0x0000c040) settings: $340bc003
71DAC2: Setting PIX PLL for pixelclock 147.222000
72DAC2: PIX PLL frequency should be locked now...
73DAC: Setting screen mode 4 brightness 1.000000
74DAC: setting palette
75DAC: PAL pixrdmsk readback $ff
76DAC2: Setting screen mode 4 brightness 1.000000
77DAC2: setting palette
78DAC2: PAL pixrdmsk readback $ff
79CRTC: setting card pitch (offset between lines)
80CRTC: offset register set to: $0348
81CRTC2: setting card pitch (offset between lines)
82CRTC2: offset register set to: $0348
83CRTC: setting card RAM to be displayed bpp 32
84CRTC: startadd: $00000800
85CRTC: frameRAM: $90000000
86CRTC: framebuffer: $90000800
87CRTC2: setting card RAM to be displayed bpp 32
88CRTC2: startadd: $00000800
89CRTC2: frameRAM: $90000000
90CRTC2: framebuffer: $90000800
91CRTC: setting timing
92CRTC: Setting full timing...
93CRTC:
94 HTOT:115
95 HDISPEND:d1
96 HBLNKS:d1
97 HBLNKE:119
98 HSYNCS:df
99 HSYNCE:f6
100 VTOT:43d
101 VDISPEND:419
102 VBLNKS:419
103 VBLNKE:43e
104 VSYNCS:41b
105 VSYNCE:41e
106CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
107CRTC2: setting timing
108CRTC2: Setting full timing...
109CRTC2:
110 HTOT:115
111 HDISPEND:d1
112 HBLNKS:d1
113 HBLNKE:119
114 HSYNCS:df
115 HSYNCE:f6
116 VTOT:43d
117 VDISPEND:419
118 VBLNKS:419
119 VBLNKE:43e
120 VSYNCS:41b
121 VSYNCE:41e
122CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
123ACC_DMA: timer numerator $000014c8, denominator $00000271
124ACC_DMA: command buffer is at adress $0x93ff8000
125SET_DPMS_MODE: $00000001
126CRTC: setting DPMS: display on, hsync enabled, vsync enabled
127CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
128INIT: RAM access OK.
129SETMODE: booted since 171500.341000 mS
130Haiku: tunnel access target=usepanel, command=set, value=0
131Haiku: tunnel access target=tvstandard, command=set, value=0
132SETMODE: (ENTER) initial modeflags: $0000015f
133SETMODE: requested target pixelclock 31329kHz
134SETMODE: requested virtual_width 800, virtual_height 500
135PROPOSEMODE: (ENTER) requested virtual_width 800, virtual_height 500
136INIT: memory pitch will be set to 800 pixels for colorspace 0x00000008
137DAC: NV4/NV10/NV20 restrictions apply
138DAC: pix VCO frequency found 500.000000Mhz
139DAC: pix PLL check: requested 31.329000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
140PROPOSEMODE: validated virtual_width 800, virtual_height 500 pixels
141PROPOSEMODE: initial modeflags: $0000015f
142PROPOSEMODE: validated modeflags: $0000015f
143PROPOSEMODE: completed successfully.
144CRTC: setting DPMS: display off, hsync disabled, vsync disabled
145CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
146INIT: memory pitch will be set to 800 pixels for colorspace 0x00000008
147SETMODE: setting DUALHEAD mode
148INIT: switching CRTC/DAC use to be straight-through
149SETMODE: target clock 31250kHz
150DAC: NV4/NV10/NV20 restrictions apply
151DAC: pix VCO frequency found 500.000000Mhz
152DAC: pix PLL check: requested 31.250000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
153DAC: dumping current pixelPLL settings:
154DAC: divider1 settings ($00023509): M1=9, N1=53, P1=4
155DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
156DAC: phase discriminator frequency is 2.777778Mhz
157DAC: VCO frequency is 588.888889Mhz
158DAC: pixelclock is 147.222229Mhz
159DAC: end of dump.
160DAC: current NV30_PLLSETUP settings: $00000000
161DAC: current (0x0000c040) settings: $340bc003
162DAC: Setting PIX PLL for pixelclock 31.250000
163DAC: PIX PLL frequency should be locked now...
164SETMODE: target2 clock 31250kHz
165DAC2: NV10/NV20 restrictions apply
166DAC2: pix VCO frequency found 500.000000Mhz
167DAC2: pix PLL check: requested 31.250000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
168DAC2: dumping current pixelPLL settings:
169DAC2: divider1 settings ($00023509): M1=9, N1=53, P1=4
170DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
171DAC2: phase discriminator frequency is 2.777778Mhz
172DAC2: VCO frequency is 588.888889Mhz
173DAC2: pixelclock is 147.222229Mhz
174DAC2: end of dump.
175DAC2: current NV30_PLLSETUP settings: $00000000
176DAC2: current (0x0000c040) settings: $340bc003
177DAC2: Setting PIX PLL for pixelclock 31.250000
178DAC2: PIX PLL frequency should be locked now...
179DAC: Setting screen mode 4 brightness 1.000000
180DAC: setting palette
181DAC: PAL pixrdmsk readback $ff
182DAC2: Setting screen mode 4 brightness 1.000000
183DAC2: setting palette
184DAC2: PAL pixrdmsk readback $ff
185CRTC: setting card pitch (offset between lines)
186CRTC: offset register set to: $0190
187CRTC2: setting card pitch (offset between lines)
188CRTC2: offset register set to: $0190
189CRTC: setting card RAM to be displayed bpp 32
190CRTC: startadd: $00000800
191CRTC: frameRAM: $90000000
192CRTC: framebuffer: $90000800
193CRTC2: setting card RAM to be displayed bpp 32
194CRTC2: startadd: $00000800
195CRTC2: frameRAM: $90000000
196CRTC2: framebuffer: $90000800
197CRTC: setting timing
198CRTC: Setting full timing...
199CRTC:
200 HTOT:79
201 HDISPEND:63
202 HBLNKS:63
203 HBLNKE:7d
204 HSYNCS:6a
205 HSYNCE:74
206 VTOT:204
207 VDISPEND:1f3
208 VBLNKS:1f3
209 VBLNKE:205
210 VSYNCS:1f5
211 VSYNCE:1f8
212CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
213CRTC2: setting timing
214CRTC2: Setting full timing...
215CRTC2:
216 HTOT:79
217 HDISPEND:63
218 HBLNKS:63
219 HBLNKE:7d
220 HSYNCS:6a
221 HSYNCE:74
222 VTOT:204
223 VDISPEND:1f3
224 VBLNKS:1f3
225 VBLNKE:205
226 VSYNCS:1f5
227 VSYNCE:1f8
228CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
229ACC_DMA: timer numerator $000014c8, denominator $00000271
230ACC_DMA: command buffer is at adress $0x93ff8000
231SET_DPMS_MODE: $00000001
232CRTC: setting DPMS: display on, hsync enabled, vsync enabled
233CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
234INIT: RAM access OK.
235SETMODE: booted since 171549.332000 mS
236Overlay: Not exporting hook B_OVERLAY_COUNT.
237Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
238Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
239Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
240Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
241Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
242Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
243Overlay: Not exporting hook B_RELEASE_OVERLAY.
244Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
245GET_EDID_INFO: returning info
246GET_EDID_INFO: returning info
247GET_EDID_INFO: returning info
248GET_EDID_INFO: returning info
249Haiku: tunnel access target=swap, command=get, value=0
250Haiku: tunnel access target=usepanel, command=get, value=0
251Haiku: tunnel access target=tvstandard, command=get, value=0
252GET_EDID_INFO: returning info
253GET_ACCELERANT_DEVICE_INFO: returning info
254Haiku: tunnel access target=swap, command=get, value=0
255Haiku: tunnel access target=usepanel, command=get, value=0
256Haiku: tunnel access target=tvstandard, command=get, value=0
257Haiku: tunnel access target=swap, command=get, value=0
258Haiku: tunnel access target=usepanel, command=get, value=0
259Haiku: tunnel access target=tvstandard, command=get, value=0
260Haiku: tunnel access target=swap, command=get, value=0
261Haiku: tunnel access target=usepanel, command=get, value=0
262Haiku: tunnel access target=tvstandard, command=get, value=0
263Haiku: tunnel access target=swap, command=get, value=0
264Haiku: tunnel access target=usepanel, command=get, value=0
265Haiku: tunnel access target=tvstandard, command=get, value=0
266GET_EDID_INFO: returning info
267Haiku: tunnel access target=swap, command=get, value=0
268Haiku: tunnel access target=usepanel, command=get, value=0
269Haiku: tunnel access target=tvstandard, command=get, value=0
270Haiku: tunnel access target=swap, command=get, value=0
271Haiku: tunnel access target=usepanel, command=get, value=0
272Haiku: tunnel access target=tvstandard, command=get, value=0
273Haiku: tunnel access target=swap, command=get, value=0
274Haiku: tunnel access target=usepanel, command=get, value=0
275Haiku: tunnel access target=tvstandard, command=get, value=0
276Haiku: tunnel access target=swap, command=get, value=0
277Haiku: tunnel access target=usepanel, command=get, value=0
278Haiku: tunnel access target=tvstandard, command=get, value=0
279Haiku: tunnel access target=swap, command=set, value=0
280SETMODE: (ENTER) initial modeflags: $0000015f
281SETMODE: requested target pixelclock 31250kHz
282SETMODE: requested virtual_width 800, virtual_height 500
283PROPOSEMODE: (ENTER) requested virtual_width 800, virtual_height 500
284INIT: memory pitch will be set to 800 pixels for colorspace 0x00000008
285DAC: NV4/NV10/NV20 restrictions apply
286DAC: pix VCO frequency found 500.000000Mhz
287DAC: pix PLL check: requested 31.250000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
288PROPOSEMODE: validated virtual_width 800, virtual_height 500 pixels
289PROPOSEMODE: initial modeflags: $0000015f
290PROPOSEMODE: validated modeflags: $0000015f
291PROPOSEMODE: completed successfully.
292CRTC: setting DPMS: display off, hsync disabled, vsync disabled
293CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
294INIT: memory pitch will be set to 800 pixels for colorspace 0x00000008
295SETMODE: setting DUALHEAD mode
296INIT: switching CRTC/DAC use to be straight-through
297SETMODE: target clock 31250kHz
298DAC: NV4/NV10/NV20 restrictions apply
299DAC: pix VCO frequency found 500.000000Mhz
300DAC: pix PLL check: requested 31.250000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
301DAC: dumping current pixelPLL settings:
302DAC: divider1 settings ($00041404): M1=4, N1=20, P1=16
303DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
304DAC: phase discriminator frequency is 6.250000Mhz
305DAC: VCO frequency is 500.000000Mhz
306DAC: pixelclock is 31.250000Mhz
307DAC: end of dump.
308DAC: current NV30_PLLSETUP settings: $00000000
309DAC: current (0x0000c040) settings: $340bc003
310DAC: Setting PIX PLL for pixelclock 31.250000
311DAC: PIX PLL frequency should be locked now...
312SETMODE: target2 clock 31250kHz
313DAC2: NV10/NV20 restrictions apply
314DAC2: pix VCO frequency found 500.000000Mhz
315DAC2: pix PLL check: requested 31.250000MHz got 31.250000MHz, mnp 0x04 0x14 0x04
316DAC2: dumping current pixelPLL settings:
317DAC2: divider1 settings ($00041404): M1=4, N1=20, P1=16
318DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
319DAC2: phase discriminator frequency is 6.250000Mhz
320DAC2: VCO frequency is 500.000000Mhz
321DAC2: pixelclock is 31.250000Mhz
322DAC2: end of dump.
323DAC2: current NV30_PLLSETUP settings: $00000000
324DAC2: current (0x0000c040) settings: $340bc003
325DAC2: Setting PIX PLL for pixelclock 31.250000
326DAC2: PIX PLL frequency should be locked now...
327DAC: Setting screen mode 4 brightness 1.000000
328DAC: setting palette
329DAC: PAL pixrdmsk readback $ff
330DAC2: Setting screen mode 4 brightness 1.000000
331DAC2: setting palette
332DAC2: PAL pixrdmsk readback $ff
333CRTC: setting card pitch (offset between lines)
334CRTC: offset register set to: $0190
335CRTC2: setting card pitch (offset between lines)
336CRTC2: offset register set to: $0190
337CRTC: setting card RAM to be displayed bpp 32
338CRTC: startadd: $00000800
339CRTC: frameRAM: $90000000
340CRTC: framebuffer: $90000800
341CRTC2: setting card RAM to be displayed bpp 32
342CRTC2: startadd: $00000800
343CRTC2: frameRAM: $90000000
344CRTC2: framebuffer: $90000800
345CRTC: setting timing
346CRTC: Setting full timing...
347CRTC:
348 HTOT:79
349 HDISPEND:63
350 HBLNKS:63
351 HBLNKE:7d
352 HSYNCS:6a
353 HSYNCE:74
354 VTOT:204
355 VDISPEND:1f3
356 VBLNKS:1f3
357 VBLNKE:205
358 VSYNCS:1f5
359 VSYNCE:1f8
360CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
361CRTC2: setting timing
362CRTC2: Setting full timing...
363CRTC2:
364 HTOT:79
365 HDISPEND:63
366 HBLNKS:63
367 HBLNKE:7d
368 HSYNCS:6a
369 HSYNCE:74
370 VTOT:204
371 VDISPEND:1f3
372 VBLNKS:1f3
373 VBLNKE:205
374 VSYNCS:1f5
375 VSYNCE:1f8
376CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
377ACC_DMA: timer numerator $000014c8, denominator $00000271
378ACC_DMA: command buffer is at adress $0x93ff8000
379SET_DPMS_MODE: $00000001
380CRTC: setting DPMS: display on, hsync enabled, vsync enabled
381CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
382INIT: RAM access OK.
383SETMODE: booted since 202144.343000 mS
384Haiku: tunnel access target=usepanel, command=set, value=0
385Haiku: tunnel access target=tvstandard, command=set, value=0
386SETMODE: (ENTER) initial modeflags: $0000015f
387SETMODE: requested target pixelclock 52828kHz
388SETMODE: requested virtual_width 1024, virtual_height 640
389PROPOSEMODE: (ENTER) requested virtual_width 1024, virtual_height 640
390INIT: memory pitch will be set to 1024 pixels for colorspace 0x00000008
391DAC: NV4/NV10/NV20 restrictions apply
392DAC: pix VCO frequency found 845.454545Mhz
393DAC: pix PLL check: requested 52.827999MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
394PROPOSEMODE: validated virtual_width 1024, virtual_height 640 pixels
395PROPOSEMODE: initial modeflags: $0000015f
396PROPOSEMODE: validated modeflags: $0000015f
397PROPOSEMODE: completed successfully.
398CRTC: setting DPMS: display off, hsync disabled, vsync disabled
399CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
400INIT: memory pitch will be set to 1024 pixels for colorspace 0x00000008
401SETMODE: setting DUALHEAD mode
402INIT: switching CRTC/DAC use to be straight-through
403SETMODE: target clock 52840kHz
404DAC: NV4/NV10/NV20 restrictions apply
405DAC: pix VCO frequency found 845.454545Mhz
406DAC: pix PLL check: requested 52.840000MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
407DAC: dumping current pixelPLL settings:
408DAC: divider1 settings ($00041404): M1=4, N1=20, P1=16
409DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
410DAC: phase discriminator frequency is 6.250000Mhz
411DAC: VCO frequency is 500.000000Mhz
412DAC: pixelclock is 31.250000Mhz
413DAC: end of dump.
414DAC: current NV30_PLLSETUP settings: $00000000
415DAC: current (0x0000c040) settings: $340bc003
416DAC: Setting PIX PLL for pixelclock 52.840000
417DAC: PIX PLL frequency should be locked now...
418SETMODE: target2 clock 52840kHz
419DAC2: NV10/NV20 restrictions apply
420DAC2: pix VCO frequency found 845.454545Mhz
421DAC2: pix PLL check: requested 52.840000MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
422DAC2: dumping current pixelPLL settings:
423DAC2: divider1 settings ($00041404): M1=4, N1=20, P1=16
424DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
425DAC2: phase discriminator frequency is 6.250000Mhz
426DAC2: VCO frequency is 500.000000Mhz
427DAC2: pixelclock is 31.250000Mhz
428DAC2: end of dump.
429DAC2: current NV30_PLLSETUP settings: $00000000
430DAC2: current (0x0000c040) settings: $340bc003
431DAC2: Setting PIX PLL for pixelclock 52.840000
432DAC2: PIX PLL frequency should be locked now...
433DAC: Setting screen mode 4 brightness 1.000000
434DAC: setting palette
435DAC: PAL pixrdmsk readback $ff
436DAC2: Setting screen mode 4 brightness 1.000000
437DAC2: setting palette
438DAC2: PAL pixrdmsk readback $ff
439CRTC: setting card pitch (offset between lines)
440CRTC: offset register set to: $0200
441CRTC2: setting card pitch (offset between lines)
442CRTC2: offset register set to: $0200
443CRTC: setting card RAM to be displayed bpp 32
444CRTC: startadd: $00000800
445CRTC: frameRAM: $90000000
446CRTC: framebuffer: $90000800
447CRTC2: setting card RAM to be displayed bpp 32
448CRTC2: startadd: $00000800
449CRTC2: frameRAM: $90000000
450CRTC2: framebuffer: $90000800
451CRTC: setting timing
452CRTC: Setting full timing...
453CRTC:
454 HTOT:a1
455 HDISPEND:7f
456 HBLNKS:7f
457 HBLNKE:a5
458 HSYNCS:86
459 HSYNCE:93
460 VTOT:295
461 VDISPEND:27f
462 VBLNKS:27f
463 VBLNKE:296
464 VSYNCS:281
465 VSYNCE:284
466CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
467CRTC2: setting timing
468CRTC2: Setting full timing...
469CRTC2:
470 HTOT:a1
471 HDISPEND:7f
472 HBLNKS:7f
473 HBLNKE:a5
474 HSYNCS:86
475 HSYNCE:93
476 VTOT:295
477 VDISPEND:27f
478 VBLNKS:27f
479 VBLNKE:296
480 VSYNCS:281
481 VSYNCE:284
482CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
483ACC_DMA: timer numerator $000014c8, denominator $00000271
484ACC_DMA: command buffer is at adress $0x93ff8000
485SET_DPMS_MODE: $00000001
486CRTC: setting DPMS: display on, hsync enabled, vsync enabled
487CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
488INIT: RAM access OK.
489SETMODE: booted since 202157.390000 mS
490Overlay: Not exporting hook B_OVERLAY_COUNT.
491Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
492Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
493Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
494Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
495Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
496Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
497Overlay: Not exporting hook B_RELEASE_OVERLAY.
498Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
499GET_EDID_INFO: returning info
500GET_EDID_INFO: returning info
501GET_EDID_INFO: returning info
502GET_EDID_INFO: returning info
503Haiku: tunnel access target=swap, command=get, value=0
504Haiku: tunnel access target=usepanel, command=get, value=0
505Haiku: tunnel access target=tvstandard, command=get, value=0
506GET_EDID_INFO: returning info
507GET_ACCELERANT_DEVICE_INFO: returning info
508Haiku: tunnel access target=swap, command=get, value=0
509Haiku: tunnel access target=usepanel, command=get, value=0
510Haiku: tunnel access target=tvstandard, command=get, value=0
511Haiku: tunnel access target=swap, command=get, value=0
512Haiku: tunnel access target=usepanel, command=get, value=0
513Haiku: tunnel access target=tvstandard, command=get, value=0
514Haiku: tunnel access target=swap, command=get, value=0
515Haiku: tunnel access target=usepanel, command=get, value=0
516Haiku: tunnel access target=tvstandard, command=get, value=0
517Haiku: tunnel access target=swap, command=get, value=0
518Haiku: tunnel access target=usepanel, command=get, value=0
519Haiku: tunnel access target=tvstandard, command=get, value=0
520GET_EDID_INFO: returning info
521Haiku: tunnel access target=swap, command=get, value=0
522Haiku: tunnel access target=usepanel, command=get, value=0
523Haiku: tunnel access target=tvstandard, command=get, value=0
524Haiku: tunnel access target=swap, command=get, value=0
525Haiku: tunnel access target=usepanel, command=get, value=0
526Haiku: tunnel access target=tvstandard, command=get, value=0
527Haiku: tunnel access target=swap, command=get, value=0
528Haiku: tunnel access target=usepanel, command=get, value=0
529Haiku: tunnel access target=tvstandard, command=get, value=0
530Haiku: tunnel access target=swap, command=get, value=0
531Haiku: tunnel access target=usepanel, command=get, value=0
532Haiku: tunnel access target=tvstandard, command=get, value=0
533Haiku: tunnel access target=swap, command=set, value=0
534SETMODE: (ENTER) initial modeflags: $0000015f
535SETMODE: requested target pixelclock 52840kHz
536SETMODE: requested virtual_width 1024, virtual_height 640
537PROPOSEMODE: (ENTER) requested virtual_width 1024, virtual_height 640
538INIT: memory pitch will be set to 1024 pixels for colorspace 0x00000008
539DAC: NV4/NV10/NV20 restrictions apply
540DAC: pix VCO frequency found 845.454545Mhz
541DAC: pix PLL check: requested 52.840000MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
542PROPOSEMODE: validated virtual_width 1024, virtual_height 640 pixels
543PROPOSEMODE: initial modeflags: $0000015f
544PROPOSEMODE: validated modeflags: $0000015f
545PROPOSEMODE: completed successfully.
546CRTC: setting DPMS: display off, hsync disabled, vsync disabled
547CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
548INIT: memory pitch will be set to 1024 pixels for colorspace 0x00000008
549SETMODE: setting DUALHEAD mode
550INIT: switching CRTC/DAC use to be straight-through
551SETMODE: target clock 52840kHz
552DAC: NV4/NV10/NV20 restrictions apply
553DAC: pix VCO frequency found 845.454545Mhz
554DAC: pix PLL check: requested 52.840000MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
555DAC: dumping current pixelPLL settings:
556DAC: divider1 settings ($00045d0b): M1=11, N1=93, P1=16
557DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
558DAC: phase discriminator frequency is 2.272727Mhz
559DAC: VCO frequency is 845.454545Mhz
560DAC: pixelclock is 52.840908Mhz
561DAC: end of dump.
562DAC: current NV30_PLLSETUP settings: $00000000
563DAC: current (0x0000c040) settings: $340bc003
564DAC: Setting PIX PLL for pixelclock 52.840000
565DAC: PIX PLL frequency should be locked now...
566SETMODE: target2 clock 52840kHz
567DAC2: NV10/NV20 restrictions apply
568DAC2: pix VCO frequency found 845.454545Mhz
569DAC2: pix PLL check: requested 52.840000MHz got 52.840908MHz, mnp 0x0b 0x5d 0x04
570DAC2: dumping current pixelPLL settings:
571DAC2: divider1 settings ($00045d0b): M1=11, N1=93, P1=16
572DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
573DAC2: phase discriminator frequency is 2.272727Mhz
574DAC2: VCO frequency is 845.454545Mhz
575DAC2: pixelclock is 52.840908Mhz
576DAC2: end of dump.
577DAC2: current NV30_PLLSETUP settings: $00000000
578DAC2: current (0x0000c040) settings: $340bc003
579DAC2: Setting PIX PLL for pixelclock 52.840000
580DAC2: PIX PLL frequency should be locked now...
581DAC: Setting screen mode 4 brightness 1.000000
582DAC: setting palette
583DAC: PAL pixrdmsk readback $ff
584DAC2: Setting screen mode 4 brightness 1.000000
585DAC2: setting palette
586DAC2: PAL pixrdmsk readback $ff
587CRTC: setting card pitch (offset between lines)
588CRTC: offset register set to: $0200
589CRTC2: setting card pitch (offset between lines)
590CRTC2: offset register set to: $0200
591CRTC: setting card RAM to be displayed bpp 32
592CRTC: startadd: $00000800
593CRTC: frameRAM: $90000000
594CRTC: framebuffer: $90000800
595CRTC2: setting card RAM to be displayed bpp 32
596CRTC2: startadd: $00000800
597CRTC2: frameRAM: $90000000
598CRTC2: framebuffer: $90000800
599CRTC: setting timing
600CRTC: Setting full timing...
601CRTC:
602 HTOT:a1
603 HDISPEND:7f
604 HBLNKS:7f
605 HBLNKE:a5
606 HSYNCS:86
607 HSYNCE:93
608 VTOT:295
609 VDISPEND:27f
610 VBLNKS:27f
611 VBLNKE:296
612 VSYNCS:281
613 VSYNCE:284
614CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
615CRTC2: setting timing
616CRTC2: Setting full timing...
617CRTC2:
618 HTOT:a1
619 HDISPEND:7f
620 HBLNKS:7f
621 HBLNKE:a5
622 HSYNCS:86
623 HSYNCE:93
624 VTOT:295
625 VDISPEND:27f
626 VBLNKS:27f
627 VBLNKE:296
628 VSYNCS:281
629 VSYNCE:284
630CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
631ACC_DMA: timer numerator $000014c8, denominator $00000271
632ACC_DMA: command buffer is at adress $0x93ff8000
633SET_DPMS_MODE: $00000001
634CRTC: setting DPMS: display on, hsync enabled, vsync enabled
635CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
636INIT: RAM access OK.
637SETMODE: booted since 228901.108000 mS
638Haiku: tunnel access target=usepanel, command=set, value=0
639Haiku: tunnel access target=tvstandard, command=set, value=0
640SETMODE: (ENTER) initial modeflags: $0000015f
641SETMODE: requested target pixelclock 80136kHz
642SETMODE: requested virtual_width 1280, virtual_height 768
643PROPOSEMODE: (ENTER) requested virtual_width 1280, virtual_height 768
644INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
645DAC: NV4/NV10/NV20 restrictions apply
646DAC: pix VCO frequency found 641.666667Mhz
647DAC: pix PLL check: requested 80.136002MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
648PROPOSEMODE: validated virtual_width 1280, virtual_height 768 pixels
649PROPOSEMODE: initial modeflags: $0000015f
650PROPOSEMODE: validated modeflags: $0000015f
651PROPOSEMODE: completed successfully.
652CRTC: setting DPMS: display off, hsync disabled, vsync disabled
653CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
654INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
655SETMODE: setting DUALHEAD mode
656INIT: switching CRTC/DAC use to be straight-through
657SETMODE: target clock 80208kHz
658DAC: NV4/NV10/NV20 restrictions apply
659DAC: pix VCO frequency found 641.666667Mhz
660DAC: pix PLL check: requested 80.208000MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
661DAC: dumping current pixelPLL settings:
662DAC: divider1 settings ($00045d0b): M1=11, N1=93, P1=16
663DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
664DAC: phase discriminator frequency is 2.272727Mhz
665DAC: VCO frequency is 845.454545Mhz
666DAC: pixelclock is 52.840908Mhz
667DAC: end of dump.
668DAC: current NV30_PLLSETUP settings: $00000000
669DAC: current (0x0000c040) settings: $340bc003
670DAC: Setting PIX PLL for pixelclock 80.208000
671DAC: PIX PLL frequency should be locked now...
672SETMODE: target2 clock 80208kHz
673DAC2: NV10/NV20 restrictions apply
674DAC2: pix VCO frequency found 641.666667Mhz
675DAC2: pix PLL check: requested 80.208000MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
676DAC2: dumping current pixelPLL settings:
677DAC2: divider1 settings ($00045d0b): M1=11, N1=93, P1=16
678DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
679DAC2: phase discriminator frequency is 2.272727Mhz
680DAC2: VCO frequency is 845.454545Mhz
681DAC2: pixelclock is 52.840908Mhz
682DAC2: end of dump.
683DAC2: current NV30_PLLSETUP settings: $00000000
684DAC2: current (0x0000c040) settings: $340bc003
685DAC2: Setting PIX PLL for pixelclock 80.208000
686DAC2: PIX PLL frequency should be locked now...
687DAC: Setting screen mode 4 brightness 1.000000
688DAC: setting palette
689DAC: PAL pixrdmsk readback $ff
690DAC2: Setting screen mode 4 brightness 1.000000
691DAC2: setting palette
692DAC2: PAL pixrdmsk readback $ff
693CRTC: setting card pitch (offset between lines)
694CRTC: offset register set to: $0280
695CRTC2: setting card pitch (offset between lines)
696CRTC2: offset register set to: $0280
697CRTC: setting card RAM to be displayed bpp 32
698CRTC: startadd: $00000800
699CRTC: frameRAM: $90000000
700CRTC: framebuffer: $90000800
701CRTC2: setting card RAM to be displayed bpp 32
702CRTC2: startadd: $00000800
703CRTC2: frameRAM: $90000000
704CRTC2: framebuffer: $90000800
705CRTC: setting timing
706CRTC: Setting full timing...
707CRTC:
708 HTOT:cd
709 HDISPEND:9f
710 HBLNKS:9f
711 HBLNKE:d1
712 HSYNCS:a8
713 HSYNCE:b9
714 VTOT:319
715 VDISPEND:2ff
716 VBLNKS:2ff
717 VBLNKE:31a
718 VSYNCS:301
719 VSYNCE:304
720CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
721CRTC2: setting timing
722CRTC2: Setting full timing...
723CRTC2:
724 HTOT:cd
725 HDISPEND:9f
726 HBLNKS:9f
727 HBLNKE:d1
728 HSYNCS:a8
729 HSYNCE:b9
730 VTOT:319
731 VDISPEND:2ff
732 VBLNKS:2ff
733 VBLNKE:31a
734 VSYNCS:301
735 VSYNCE:304
736CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
737ACC_DMA: timer numerator $000014c8, denominator $00000271
738ACC_DMA: command buffer is at adress $0x93ff8000
739SET_DPMS_MODE: $00000001
740CRTC: setting DPMS: display on, hsync enabled, vsync enabled
741CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
742INIT: RAM access OK.
743SETMODE: booted since 228914.739000 mS
744Overlay: Not exporting hook B_OVERLAY_COUNT.
745Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
746Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
747Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
748Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
749Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
750Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
751Overlay: Not exporting hook B_RELEASE_OVERLAY.
752Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
753GET_EDID_INFO: returning info
754GET_EDID_INFO: returning info
755GET_EDID_INFO: returning info
756GET_EDID_INFO: returning info
757Haiku: tunnel access target=swap, command=get, value=0
758Haiku: tunnel access target=usepanel, command=get, value=0
759Haiku: tunnel access target=tvstandard, command=get, value=0
760GET_EDID_INFO: returning info
761GET_ACCELERANT_DEVICE_INFO: returning info
762Haiku: tunnel access target=swap, command=get, value=0
763Haiku: tunnel access target=usepanel, command=get, value=0
764Haiku: tunnel access target=tvstandard, command=get, value=0
765Haiku: tunnel access target=swap, command=get, value=0
766Haiku: tunnel access target=usepanel, command=get, value=0
767Haiku: tunnel access target=tvstandard, command=get, value=0
768Haiku: tunnel access target=swap, command=get, value=0
769Haiku: tunnel access target=usepanel, command=get, value=0
770Haiku: tunnel access target=tvstandard, command=get, value=0
771Haiku: tunnel access target=swap, command=get, value=0
772Haiku: tunnel access target=usepanel, command=get, value=0
773Haiku: tunnel access target=tvstandard, command=get, value=0
774GET_EDID_INFO: returning info
775Haiku: tunnel access target=swap, command=get, value=0
776Haiku: tunnel access target=usepanel, command=get, value=0
777Haiku: tunnel access target=tvstandard, command=get, value=0
778Haiku: tunnel access target=swap, command=get, value=0
779Haiku: tunnel access target=usepanel, command=get, value=0
780Haiku: tunnel access target=tvstandard, command=get, value=0
781Haiku: tunnel access target=swap, command=get, value=0
782Haiku: tunnel access target=usepanel, command=get, value=0
783Haiku: tunnel access target=tvstandard, command=get, value=0
784Haiku: tunnel access target=swap, command=get, value=0
785Haiku: tunnel access target=usepanel, command=get, value=0
786Haiku: tunnel access target=tvstandard, command=get, value=0
787Haiku: tunnel access target=swap, command=set, value=0
788SETMODE: (ENTER) initial modeflags: $0000015f
789SETMODE: requested target pixelclock 80208kHz
790SETMODE: requested virtual_width 1280, virtual_height 768
791PROPOSEMODE: (ENTER) requested virtual_width 1280, virtual_height 768
792INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
793DAC: NV4/NV10/NV20 restrictions apply
794DAC: pix VCO frequency found 641.666667Mhz
795DAC: pix PLL check: requested 80.208000MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
796PROPOSEMODE: validated virtual_width 1280, virtual_height 768 pixels
797PROPOSEMODE: initial modeflags: $0000015f
798PROPOSEMODE: validated modeflags: $0000015f
799PROPOSEMODE: completed successfully.
800CRTC: setting DPMS: display off, hsync disabled, vsync disabled
801CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
802INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
803SETMODE: setting DUALHEAD mode
804INIT: switching CRTC/DAC use to be straight-through
805SETMODE: target clock 80208kHz
806DAC: NV4/NV10/NV20 restrictions apply
807DAC: pix VCO frequency found 641.666667Mhz
808DAC: pix PLL check: requested 80.208000MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
809DAC: dumping current pixelPLL settings:
810DAC: divider1 settings ($00034d0c): M1=12, N1=77, P1=8
811DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
812DAC: phase discriminator frequency is 2.083333Mhz
813DAC: VCO frequency is 641.666667Mhz
814DAC: pixelclock is 80.208336Mhz
815DAC: end of dump.
816DAC: current NV30_PLLSETUP settings: $00000000
817DAC: current (0x0000c040) settings: $340bc003
818DAC: Setting PIX PLL for pixelclock 80.208000
819DAC: PIX PLL frequency should be locked now...
820SETMODE: target2 clock 80208kHz
821DAC2: NV10/NV20 restrictions apply
822DAC2: pix VCO frequency found 641.666667Mhz
823DAC2: pix PLL check: requested 80.208000MHz got 80.208336MHz, mnp 0x0c 0x4d 0x03
824DAC2: dumping current pixelPLL settings:
825DAC2: divider1 settings ($00034d0c): M1=12, N1=77, P1=8
826DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
827DAC2: phase discriminator frequency is 2.083333Mhz
828DAC2: VCO frequency is 641.666667Mhz
829DAC2: pixelclock is 80.208336Mhz
830DAC2: end of dump.
831DAC2: current NV30_PLLSETUP settings: $00000000
832DAC2: current (0x0000c040) settings: $340bc003
833DAC2: Setting PIX PLL for pixelclock 80.208000
834DAC2: PIX PLL frequency should be locked now...
835DAC: Setting screen mode 4 brightness 1.000000
836DAC: setting palette
837DAC: PAL pixrdmsk readback $ff
838DAC2: Setting screen mode 4 brightness 1.000000
839DAC2: setting palette
840DAC2: PAL pixrdmsk readback $ff
841CRTC: setting card pitch (offset between lines)
842CRTC: offset register set to: $0280
843CRTC2: setting card pitch (offset between lines)
844CRTC2: offset register set to: $0280
845CRTC: setting card RAM to be displayed bpp 32
846CRTC: startadd: $00000800
847CRTC: frameRAM: $90000000
848CRTC: framebuffer: $90000800
849CRTC2: setting card RAM to be displayed bpp 32
850CRTC2: startadd: $00000800
851CRTC2: frameRAM: $90000000
852CRTC2: framebuffer: $90000800
853CRTC: setting timing
854CRTC: Setting full timing...
855CRTC:
856 HTOT:cd
857 HDISPEND:9f
858 HBLNKS:9f
859 HBLNKE:d1
860 HSYNCS:a8
861 HSYNCE:b9
862 VTOT:319
863 VDISPEND:2ff
864 VBLNKS:2ff
865 VBLNKE:31a
866 VSYNCS:301
867 VSYNCE:304
868CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
869CRTC2: setting timing
870CRTC2: Setting full timing...
871CRTC2:
872 HTOT:cd
873 HDISPEND:9f
874 HBLNKS:9f
875 HBLNKE:d1
876 HSYNCS:a8
877 HSYNCE:b9
878 VTOT:319
879 VDISPEND:2ff
880 VBLNKS:2ff
881 VBLNKE:31a
882 VSYNCS:301
883 VSYNCE:304
884CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
885ACC_DMA: timer numerator $000014c8, denominator $00000271
886ACC_DMA: command buffer is at adress $0x93ff8000
887SET_DPMS_MODE: $00000001
888CRTC: setting DPMS: display on, hsync enabled, vsync enabled
889CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
890INIT: RAM access OK.
891SETMODE: booted since 257689.275000 mS
892Haiku: tunnel access target=usepanel, command=set, value=0
893Haiku: tunnel access target=tvstandard, command=set, value=0
894SETMODE: (ENTER) initial modeflags: $0000015f
895SETMODE: requested target pixelclock 83462kHz
896SETMODE: requested virtual_width 1280, virtual_height 800
897PROPOSEMODE: (ENTER) requested virtual_width 1280, virtual_height 800
898INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
899DAC: NV4/NV10/NV20 restrictions apply
900DAC: pix VCO frequency found 666.666667Mhz
901DAC: pix PLL check: requested 83.461998MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
902PROPOSEMODE: validated virtual_width 1280, virtual_height 800 pixels
903PROPOSEMODE: initial modeflags: $0000015f
904PROPOSEMODE: validated modeflags: $0000015f
905PROPOSEMODE: completed successfully.
906CRTC: setting DPMS: display off, hsync disabled, vsync disabled
907CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
908INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
909SETMODE: setting DUALHEAD mode
910INIT: switching CRTC/DAC use to be straight-through
911SETMODE: target clock 83333kHz
912DAC: NV4/NV10/NV20 restrictions apply
913DAC: pix VCO frequency found 666.666667Mhz
914DAC: pix PLL check: requested 83.333000MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
915DAC: dumping current pixelPLL settings:
916DAC: divider1 settings ($00034d0c): M1=12, N1=77, P1=8
917DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
918DAC: phase discriminator frequency is 2.083333Mhz
919DAC: VCO frequency is 641.666667Mhz
920DAC: pixelclock is 80.208336Mhz
921DAC: end of dump.
922DAC: current NV30_PLLSETUP settings: $00000000
923DAC: current (0x0000c040) settings: $340bc003
924DAC: Setting PIX PLL for pixelclock 83.333000
925DAC: PIX PLL frequency should be locked now...
926SETMODE: target2 clock 83333kHz
927DAC2: NV10/NV20 restrictions apply
928DAC2: pix VCO frequency found 666.666667Mhz
929DAC2: pix PLL check: requested 83.333000MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
930DAC2: dumping current pixelPLL settings:
931DAC2: divider1 settings ($00034d0c): M1=12, N1=77, P1=8
932DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
933DAC2: phase discriminator frequency is 2.083333Mhz
934DAC2: VCO frequency is 641.666667Mhz
935DAC2: pixelclock is 80.208336Mhz
936DAC2: end of dump.
937DAC2: current NV30_PLLSETUP settings: $00000000
938DAC2: current (0x0000c040) settings: $340bc003
939DAC2: Setting PIX PLL for pixelclock 83.333000
940DAC2: PIX PLL frequency should be locked now...
941DAC: Setting screen mode 4 brightness 1.000000
942DAC: setting palette
943DAC: PAL pixrdmsk readback $ff
944DAC2: Setting screen mode 4 brightness 1.000000
945DAC2: setting palette
946DAC2: PAL pixrdmsk readback $ff
947CRTC: setting card pitch (offset between lines)
948CRTC: offset register set to: $0280
949CRTC2: setting card pitch (offset between lines)
950CRTC2: offset register set to: $0280
951CRTC: setting card RAM to be displayed bpp 32
952CRTC: startadd: $00000800
953CRTC: frameRAM: $90000000
954CRTC: framebuffer: $90000800
955CRTC2: setting card RAM to be displayed bpp 32
956CRTC2: startadd: $00000800
957CRTC2: frameRAM: $90000000
958CRTC2: framebuffer: $90000800
959CRTC: setting timing
960CRTC: Setting full timing...
961CRTC:
962 HTOT:cd
963 HDISPEND:9f
964 HBLNKS:9f
965 HBLNKE:d1
966 HSYNCS:a8
967 HSYNCE:b9
968 VTOT:33a
969 VDISPEND:31f
970 VBLNKS:31f
971 VBLNKE:33b
972 VSYNCS:321
973 VSYNCE:324
974CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
975CRTC2: setting timing
976CRTC2: Setting full timing...
977CRTC2:
978 HTOT:cd
979 HDISPEND:9f
980 HBLNKS:9f
981 HBLNKE:d1
982 HSYNCS:a8
983 HSYNCE:b9
984 VTOT:33a
985 VDISPEND:31f
986 VBLNKS:31f
987 VBLNKE:33b
988 VSYNCS:321
989 VSYNCE:324
990CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
991ACC_DMA: timer numerator $000014c8, denominator $00000271
992ACC_DMA: command buffer is at adress $0x93ff8000
993SET_DPMS_MODE: $00000001
994CRTC: setting DPMS: display on, hsync enabled, vsync enabled
995CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
996INIT: RAM access OK.
997SETMODE: booted since 257705.578000 mS
998Overlay: Not exporting hook B_OVERLAY_COUNT.
999Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
1000Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
1001Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
1002Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
1003Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
1004Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
1005Overlay: Not exporting hook B_RELEASE_OVERLAY.
1006Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
1007GET_EDID_INFO: returning info
1008GET_EDID_INFO: returning info
1009GET_EDID_INFO: returning info
1010GET_EDID_INFO: returning info
1011Haiku: tunnel access target=swap, command=get, value=0
1012Haiku: tunnel access target=usepanel, command=get, value=0
1013Haiku: tunnel access target=tvstandard, command=get, value=0
1014GET_EDID_INFO: returning info
1015GET_ACCELERANT_DEVICE_INFO: returning info
1016Haiku: tunnel access target=swap, command=get, value=0
1017Haiku: tunnel access target=usepanel, command=get, value=0
1018Haiku: tunnel access target=tvstandard, command=get, value=0
1019Haiku: tunnel access target=swap, command=get, value=0
1020Haiku: tunnel access target=usepanel, command=get, value=0
1021Haiku: tunnel access target=tvstandard, command=get, value=0
1022Haiku: tunnel access target=swap, command=get, value=0
1023Haiku: tunnel access target=usepanel, command=get, value=0
1024Haiku: tunnel access target=tvstandard, command=get, value=0
1025Haiku: tunnel access target=swap, command=get, value=0
1026Haiku: tunnel access target=usepanel, command=get, value=0
1027Haiku: tunnel access target=tvstandard, command=get, value=0
1028GET_EDID_INFO: returning info
1029Haiku: tunnel access target=swap, command=get, value=0
1030Haiku: tunnel access target=usepanel, command=get, value=0
1031Haiku: tunnel access target=tvstandard, command=get, value=0
1032Haiku: tunnel access target=swap, command=get, value=0
1033Haiku: tunnel access target=usepanel, command=get, value=0
1034Haiku: tunnel access target=tvstandard, command=get, value=0
1035Haiku: tunnel access target=swap, command=get, value=0
1036Haiku: tunnel access target=usepanel, command=get, value=0
1037Haiku: tunnel access target=tvstandard, command=get, value=0
1038Haiku: tunnel access target=swap, command=get, value=0
1039Haiku: tunnel access target=usepanel, command=get, value=0
1040Haiku: tunnel access target=tvstandard, command=get, value=0
1041Haiku: tunnel access target=swap, command=set, value=0
1042SETMODE: (ENTER) initial modeflags: $0000015f
1043SETMODE: requested target pixelclock 83333kHz
1044SETMODE: requested virtual_width 1280, virtual_height 800
1045PROPOSEMODE: (ENTER) requested virtual_width 1280, virtual_height 800
1046INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
1047DAC: NV4/NV10/NV20 restrictions apply
1048DAC: pix VCO frequency found 666.666667Mhz
1049DAC: pix PLL check: requested 83.333000MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
1050PROPOSEMODE: validated virtual_width 1280, virtual_height 800 pixels
1051PROPOSEMODE: initial modeflags: $0000015f
1052PROPOSEMODE: validated modeflags: $0000015f
1053PROPOSEMODE: completed successfully.
1054CRTC: setting DPMS: display off, hsync disabled, vsync disabled
1055CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
1056INIT: memory pitch will be set to 1280 pixels for colorspace 0x00000008
1057SETMODE: setting DUALHEAD mode
1058INIT: switching CRTC/DAC use to be straight-through
1059SETMODE: target clock 83333kHz
1060DAC: NV4/NV10/NV20 restrictions apply
1061DAC: pix VCO frequency found 666.666667Mhz
1062DAC: pix PLL check: requested 83.333000MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
1063DAC: dumping current pixelPLL settings:
1064DAC: divider1 settings ($0003500c): M1=12, N1=80, P1=8
1065DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
1066DAC: phase discriminator frequency is 2.083333Mhz
1067DAC: VCO frequency is 666.666667Mhz
1068DAC: pixelclock is 83.333336Mhz
1069DAC: end of dump.
1070DAC: current NV30_PLLSETUP settings: $00000000
1071DAC: current (0x0000c040) settings: $340bc003
1072DAC: Setting PIX PLL for pixelclock 83.333000
1073DAC: PIX PLL frequency should be locked now...
1074SETMODE: target2 clock 83333kHz
1075DAC2: NV10/NV20 restrictions apply
1076DAC2: pix VCO frequency found 666.666667Mhz
1077DAC2: pix PLL check: requested 83.333000MHz got 83.333336MHz, mnp 0x0c 0x50 0x03
1078DAC2: dumping current pixelPLL settings:
1079DAC2: divider1 settings ($0003500c): M1=12, N1=80, P1=8
1080DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
1081DAC2: phase discriminator frequency is 2.083333Mhz
1082DAC2: VCO frequency is 666.666667Mhz
1083DAC2: pixelclock is 83.333336Mhz
1084DAC2: end of dump.
1085DAC2: current NV30_PLLSETUP settings: $00000000
1086DAC2: current (0x0000c040) settings: $340bc003
1087DAC2: Setting PIX PLL for pixelclock 83.333000
1088DAC2: PIX PLL frequency should be locked now...
1089DAC: Setting screen mode 4 brightness 1.000000
1090DAC: setting palette
1091DAC: PAL pixrdmsk readback $ff
1092DAC2: Setting screen mode 4 brightness 1.000000
1093DAC2: setting palette
1094DAC2: PAL pixrdmsk readback $ff
1095CRTC: setting card pitch (offset between lines)
1096CRTC: offset register set to: $0280
1097CRTC2: setting card pitch (offset between lines)
1098CRTC2: offset register set to: $0280
1099CRTC: setting card RAM to be displayed bpp 32
1100CRTC: startadd: $00000800
1101CRTC: frameRAM: $90000000
1102CRTC: framebuffer: $90000800
1103CRTC2: setting card RAM to be displayed bpp 32
1104CRTC2: startadd: $00000800
1105CRTC2: frameRAM: $90000000
1106CRTC2: framebuffer: $90000800
1107CRTC: setting timing
1108CRTC: Setting full timing...
1109CRTC:
1110 HTOT:cd
1111 HDISPEND:9f
1112 HBLNKS:9f
1113 HBLNKE:d1
1114 HSYNCS:a8
1115 HSYNCE:b9
1116 VTOT:33a
1117 VDISPEND:31f
1118 VBLNKS:31f
1119 VBLNKE:33b
1120 VSYNCS:321
1121 VSYNCE:324
1122CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
1123CRTC2: setting timing
1124CRTC2: Setting full timing...
1125CRTC2:
1126 HTOT:cd
1127 HDISPEND:9f
1128 HBLNKS:9f
1129 HBLNKE:d1
1130 HSYNCS:a8
1131 HSYNCE:b9
1132 VTOT:33a
1133 VDISPEND:31f
1134 VBLNKS:31f
1135 VBLNKE:33b
1136 VSYNCS:321
1137 VSYNCE:324
1138CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
1139ACC_DMA: timer numerator $000014c8, denominator $00000271
1140ACC_DMA: command buffer is at adress $0x93ff8000
1141SET_DPMS_MODE: $00000001
1142CRTC: setting DPMS: display on, hsync enabled, vsync enabled
1143CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
1144INIT: RAM access OK.
1145SETMODE: booted since 282144.128000 mS
1146Haiku: tunnel access target=usepanel, command=set, value=0
1147Haiku: tunnel access target=tvstandard, command=set, value=0
1148SETMODE: (ENTER) initial modeflags: $0000015f
1149SETMODE: requested target pixelclock 122614kHz
1150SETMODE: requested virtual_width 1400, virtual_height 1050
1151PROPOSEMODE: (ENTER) requested virtual_width 1400, virtual_height 1050
1152INIT: memory pitch will be set to 1408 pixels for colorspace 0x00000008
1153INIT: effective mode slopspace is 8 pixels
1154DAC: NV4/NV10/NV20 restrictions apply
1155DAC: pix VCO frequency found 980.000000Mhz
1156DAC: pix PLL check: requested 122.612999MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1157PROPOSEMODE: validated virtual_width 1400, virtual_height 1050 pixels
1158PROPOSEMODE: initial modeflags: $0000015f
1159PROPOSEMODE: validated modeflags: $0000015f
1160PROPOSEMODE: completed successfully.
1161CRTC: setting DPMS: display off, hsync disabled, vsync disabled
1162CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
1163INIT: memory pitch will be set to 1408 pixels for colorspace 0x00000008
1164INIT: effective mode slopspace is 8 pixels
1165SETMODE: setting DUALHEAD mode
1166INIT: switching CRTC/DAC use to be straight-through
1167SETMODE: target clock 122500kHz
1168DAC: NV4/NV10/NV20 restrictions apply
1169DAC: pix VCO frequency found 980.000000Mhz
1170DAC: pix PLL check: requested 122.500000MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1171DAC: dumping current pixelPLL settings:
1172DAC: divider1 settings ($0003500c): M1=12, N1=80, P1=8
1173DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
1174DAC: phase discriminator frequency is 2.083333Mhz
1175DAC: VCO frequency is 666.666667Mhz
1176DAC: pixelclock is 83.333336Mhz
1177DAC: end of dump.
1178DAC: current NV30_PLLSETUP settings: $00000000
1179DAC: current (0x0000c040) settings: $340bc003
1180DAC: Setting PIX PLL for pixelclock 122.500000
1181DAC: PIX PLL frequency should be locked now...
1182SETMODE: target2 clock 122500kHz
1183DAC2: NV10/NV20 restrictions apply
1184DAC2: pix VCO frequency found 980.000000Mhz
1185DAC2: pix PLL check: requested 122.500000MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1186DAC2: dumping current pixelPLL settings:
1187DAC2: divider1 settings ($0003500c): M1=12, N1=80, P1=8
1188DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
1189DAC2: phase discriminator frequency is 2.083333Mhz
1190DAC2: VCO frequency is 666.666667Mhz
1191DAC2: pixelclock is 83.333336Mhz
1192DAC2: end of dump.
1193DAC2: current NV30_PLLSETUP settings: $00000000
1194DAC2: current (0x0000c040) settings: $340bc003
1195DAC2: Setting PIX PLL for pixelclock 122.500000
1196DAC2: PIX PLL frequency should be locked now...
1197DAC: Setting screen mode 4 brightness 1.000000
1198DAC: setting palette
1199DAC: PAL pixrdmsk readback $ff
1200DAC2: Setting screen mode 4 brightness 1.000000
1201DAC2: setting palette
1202DAC2: PAL pixrdmsk readback $ff
1203CRTC: setting card pitch (offset between lines)
1204CRTC: offset register set to: $02c0
1205CRTC2: setting card pitch (offset between lines)
1206CRTC2: offset register set to: $02c0
1207CRTC: setting card RAM to be displayed bpp 32
1208CRTC: startadd: $00000800
1209CRTC: frameRAM: $90000000
1210CRTC: framebuffer: $90000800
1211CRTC2: setting card RAM to be displayed bpp 32
1212CRTC2: startadd: $00000800
1213CRTC2: frameRAM: $90000000
1214CRTC2: framebuffer: $90000800
1215CRTC: setting timing
1216CRTC: Setting full timing...
1217CRTC:
1218 HTOT:e6
1219 HDISPEND:ae
1220 HBLNKS:ae
1221 HBLNKE:ea
1222 HSYNCS:ba
1223 HSYNCE:cd
1224 VTOT:43d
1225 VDISPEND:419
1226 VBLNKS:419
1227 VBLNKE:43e
1228 VSYNCS:41b
1229 VSYNCE:41e
1230CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
1231CRTC2: setting timing
1232CRTC2: Setting full timing...
1233CRTC2:
1234 HTOT:e6
1235 HDISPEND:ae
1236 HBLNKS:ae
1237 HBLNKE:ea
1238 HSYNCS:ba
1239 HSYNCE:cd
1240 VTOT:43d
1241 VDISPEND:419
1242 VBLNKS:419
1243 VBLNKE:43e
1244 VSYNCS:41b
1245 VSYNCE:41e
1246CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
1247ACC_DMA: timer numerator $000014c8, denominator $00000271
1248ACC_DMA: command buffer is at adress $0x93ff8000
1249SET_DPMS_MODE: $00000001
1250CRTC: setting DPMS: display on, hsync enabled, vsync enabled
1251CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
1252INIT: RAM access OK.
1253SETMODE: booted since 282158.022000 mS
1254Overlay: Not exporting hook B_OVERLAY_COUNT.
1255Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
1256Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
1257Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
1258Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
1259Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
1260Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
1261Overlay: Not exporting hook B_RELEASE_OVERLAY.
1262Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
1263GET_EDID_INFO: returning info
1264GET_EDID_INFO: returning info
1265GET_EDID_INFO: returning info
1266GET_EDID_INFO: returning info
1267Haiku: tunnel access target=swap, command=get, value=0
1268Haiku: tunnel access target=usepanel, command=get, value=0
1269Haiku: tunnel access target=tvstandard, command=get, value=0
1270GET_EDID_INFO: returning info
1271GET_ACCELERANT_DEVICE_INFO: returning info
1272Haiku: tunnel access target=swap, command=get, value=0
1273Haiku: tunnel access target=usepanel, command=get, value=0
1274Haiku: tunnel access target=tvstandard, command=get, value=0
1275Haiku: tunnel access target=swap, command=get, value=0
1276Haiku: tunnel access target=usepanel, command=get, value=0
1277Haiku: tunnel access target=tvstandard, command=get, value=0
1278Haiku: tunnel access target=swap, command=get, value=0
1279Haiku: tunnel access target=usepanel, command=get, value=0
1280Haiku: tunnel access target=tvstandard, command=get, value=0
1281Haiku: tunnel access target=swap, command=get, value=0
1282Haiku: tunnel access target=usepanel, command=get, value=0
1283Haiku: tunnel access target=tvstandard, command=get, value=0
1284GET_EDID_INFO: returning info
1285Haiku: tunnel access target=swap, command=get, value=0
1286Haiku: tunnel access target=usepanel, command=get, value=0
1287Haiku: tunnel access target=tvstandard, command=get, value=0
1288Haiku: tunnel access target=swap, command=get, value=0
1289Haiku: tunnel access target=usepanel, command=get, value=0
1290Haiku: tunnel access target=tvstandard, command=get, value=0
1291Haiku: tunnel access target=swap, command=get, value=0
1292Haiku: tunnel access target=usepanel, command=get, value=0
1293Haiku: tunnel access target=tvstandard, command=get, value=0
1294Haiku: tunnel access target=swap, command=get, value=0
1295Haiku: tunnel access target=usepanel, command=get, value=0
1296Haiku: tunnel access target=tvstandard, command=get, value=0
1297Haiku: tunnel access target=swap, command=set, value=0
1298SETMODE: (ENTER) initial modeflags: $0000015f
1299SETMODE: requested target pixelclock 122500kHz
1300SETMODE: requested virtual_width 1400, virtual_height 1050
1301PROPOSEMODE: (ENTER) requested virtual_width 1400, virtual_height 1050
1302INIT: memory pitch will be set to 1408 pixels for colorspace 0x00000008
1303INIT: effective mode slopspace is 8 pixels
1304DAC: NV4/NV10/NV20 restrictions apply
1305DAC: pix VCO frequency found 980.000000Mhz
1306DAC: pix PLL check: requested 122.500000MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1307PROPOSEMODE: validated virtual_width 1400, virtual_height 1050 pixels
1308PROPOSEMODE: initial modeflags: $0000015f
1309PROPOSEMODE: validated modeflags: $0000015f
1310PROPOSEMODE: completed successfully.
1311CRTC: setting DPMS: display off, hsync disabled, vsync disabled
1312CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
1313INIT: memory pitch will be set to 1408 pixels for colorspace 0x00000008
1314INIT: effective mode slopspace is 8 pixels
1315SETMODE: setting DUALHEAD mode
1316INIT: switching CRTC/DAC use to be straight-through
1317SETMODE: target clock 122500kHz
1318DAC: NV4/NV10/NV20 restrictions apply
1319DAC: pix VCO frequency found 980.000000Mhz
1320DAC: pix PLL check: requested 122.500000MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1321DAC: dumping current pixelPLL settings:
1322DAC: divider1 settings ($00033105): M1=5, N1=49, P1=8
1323DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
1324DAC: phase discriminator frequency is 5.000000Mhz
1325DAC: VCO frequency is 980.000000Mhz
1326DAC: pixelclock is 122.500000Mhz
1327DAC: end of dump.
1328DAC: current NV30_PLLSETUP settings: $00000000
1329DAC: current (0x0000c040) settings: $340bc003
1330DAC: Setting PIX PLL for pixelclock 122.500000
1331DAC: PIX PLL frequency should be locked now...
1332SETMODE: target2 clock 122500kHz
1333DAC2: NV10/NV20 restrictions apply
1334DAC2: pix VCO frequency found 980.000000Mhz
1335DAC2: pix PLL check: requested 122.500000MHz got 122.500000MHz, mnp 0x05 0x31 0x03
1336DAC2: dumping current pixelPLL settings:
1337DAC2: divider1 settings ($00033105): M1=5, N1=49, P1=8
1338DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
1339DAC2: phase discriminator frequency is 5.000000Mhz
1340DAC2: VCO frequency is 980.000000Mhz
1341DAC2: pixelclock is 122.500000Mhz
1342DAC2: end of dump.
1343DAC2: current NV30_PLLSETUP settings: $00000000
1344DAC2: current (0x0000c040) settings: $340bc003
1345DAC2: Setting PIX PLL for pixelclock 122.500000
1346DAC2: PIX PLL frequency should be locked now...
1347DAC: Setting screen mode 4 brightness 1.000000
1348DAC: setting palette
1349DAC: PAL pixrdmsk readback $ff
1350DAC2: Setting screen mode 4 brightness 1.000000
1351DAC2: setting palette
1352DAC2: PAL pixrdmsk readback $ff
1353CRTC: setting card pitch (offset between lines)
1354CRTC: offset register set to: $02c0
1355CRTC2: setting card pitch (offset between lines)
1356CRTC2: offset register set to: $02c0
1357CRTC: setting card RAM to be displayed bpp 32
1358CRTC: startadd: $00000800
1359CRTC: frameRAM: $90000000
1360CRTC: framebuffer: $90000800
1361CRTC2: setting card RAM to be displayed bpp 32
1362CRTC2: startadd: $00000800
1363CRTC2: frameRAM: $90000000
1364CRTC2: framebuffer: $90000800
1365CRTC: setting timing
1366CRTC: Setting full timing...
1367CRTC:
1368 HTOT:e6
1369 HDISPEND:ae
1370 HBLNKS:ae
1371 HBLNKE:ea
1372 HSYNCS:ba
1373 HSYNCE:cd
1374 VTOT:43d
1375 VDISPEND:419
1376 VBLNKS:419
1377 VBLNKE:43e
1378 VSYNCS:41b
1379 VSYNCE:41e
1380CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
1381CRTC2: setting timing
1382CRTC2: Setting full timing...
1383CRTC2:
1384 HTOT:e6
1385 HDISPEND:ae
1386 HBLNKS:ae
1387 HBLNKE:ea
1388 HSYNCS:ba
1389 HSYNCE:cd
1390 VTOT:43d
1391 VDISPEND:419
1392 VBLNKS:419
1393 VBLNKE:43e
1394 VSYNCS:41b
1395 VSYNCE:41e
1396CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
1397ACC_DMA: timer numerator $000014c8, denominator $00000271
1398ACC_DMA: command buffer is at adress $0x93ff8000
1399SET_DPMS_MODE: $00000001
1400CRTC: setting DPMS: display on, hsync enabled, vsync enabled
1401CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
1402INIT: RAM access OK.
1403SETMODE: booted since 302043.471000 mS
1404Haiku: tunnel access target=usepanel, command=set, value=0
1405Haiku: tunnel access target=tvstandard, command=set, value=0
1406SETMODE: (ENTER) initial modeflags: $0000015f
1407SETMODE: requested target pixelclock 106472kHz
1408SETMODE: requested virtual_width 1440, virtual_height 900
1409PROPOSEMODE: (ENTER) requested virtual_width 1440, virtual_height 900
1410INIT: memory pitch will be set to 1440 pixels for colorspace 0x00000008
1411DAC: NV4/NV10/NV20 restrictions apply
1412DAC: pix VCO frequency found 850.000000Mhz
1413DAC: pix PLL check: requested 106.472000MHz got 106.250000MHz, mnp 0x04 0x22 0x03
1414PROPOSEMODE: validated virtual_width 1440, virtual_height 900 pixels
1415PROPOSEMODE: initial modeflags: $0000015f
1416PROPOSEMODE: validated modeflags: $0000015f
1417PROPOSEMODE: completed successfully.
1418CRTC: setting DPMS: display off, hsync disabled, vsync disabled
1419CRTC2: setting DPMS: display off, hsync disabled, vsync disabled
1420INIT: memory pitch will be set to 1440 pixels for colorspace 0x00000008
1421SETMODE: setting DUALHEAD mode
1422INIT: switching CRTC/DAC use to be straight-through
1423SETMODE: target clock 106250kHz
1424DAC: NV4/NV10/NV20 restrictions apply
1425DAC: pix VCO frequency found 850.000000Mhz
1426DAC: pix PLL check: requested 106.250000MHz got 106.250000MHz, mnp 0x04 0x22 0x03
1427DAC: dumping current pixelPLL settings:
1428DAC: divider1 settings ($00033105): M1=5, N1=49, P1=8
1429DAC: divider2 is enabled, settings ($80000401): M2=1, N2=4
1430DAC: phase discriminator frequency is 5.000000Mhz
1431DAC: VCO frequency is 980.000000Mhz
1432DAC: pixelclock is 122.500000Mhz
1433DAC: end of dump.
1434DAC: current NV30_PLLSETUP settings: $00000000
1435DAC: current (0x0000c040) settings: $340bc003
1436DAC: Setting PIX PLL for pixelclock 106.250000
1437DAC: PIX PLL frequency should be locked now...
1438SETMODE: target2 clock 106250kHz
1439DAC2: NV10/NV20 restrictions apply
1440DAC2: pix VCO frequency found 850.000000Mhz
1441DAC2: pix PLL check: requested 106.250000MHz got 106.250000MHz, mnp 0x04 0x22 0x03
1442DAC2: dumping current pixelPLL settings:
1443DAC2: divider1 settings ($00033105): M1=5, N1=49, P1=8
1444DAC2: divider2 is enabled, settings ($80000401): M2=1, N2=4
1445DAC2: phase discriminator frequency is 5.000000Mhz
1446DAC2: VCO frequency is 980.000000Mhz
1447DAC2: pixelclock is 122.500000Mhz
1448DAC2: end of dump.
1449DAC2: current NV30_PLLSETUP settings: $00000000
1450DAC2: current (0x0000c040) settings: $340bc003
1451DAC2: Setting PIX PLL for pixelclock 106.250000
1452DAC2: PIX PLL frequency should be locked now...
1453DAC: Setting screen mode 4 brightness 1.000000
1454DAC: setting palette
1455DAC: PAL pixrdmsk readback $ff
1456DAC2: Setting screen mode 4 brightness 1.000000
1457DAC2: setting palette
1458DAC2: PAL pixrdmsk readback $ff
1459CRTC: setting card pitch (offset between lines)
1460CRTC: offset register set to: $02d0
1461CRTC2: setting card pitch (offset between lines)
1462CRTC2: offset register set to: $02d0
1463CRTC: setting card RAM to be displayed bpp 32
1464CRTC: startadd: $00000800
1465CRTC: frameRAM: $90000000
1466CRTC: framebuffer: $90000800
1467CRTC2: setting card RAM to be displayed bpp 32
1468CRTC2: startadd: $00000800
1469CRTC2: frameRAM: $90000000
1470CRTC2: framebuffer: $90000800
1471CRTC: setting timing
1472CRTC: Setting full timing...
1473CRTC:
1474 HTOT:e9
1475 HDISPEND:b3
1476 HBLNKS:b3
1477 HBLNKE:ed
1478 HSYNCS:be
1479 HSYNCE:d1
1480 VTOT:3a2
1481 VDISPEND:383
1482 VBLNKS:383
1483 VBLNKE:3a3
1484 VSYNCS:385
1485 VSYNCE:388
1486CRTC: sync polarity: H:pos V:pos , MISC reg readback: $0b
1487CRTC2: setting timing
1488CRTC2: Setting full timing...
1489CRTC2:
1490 HTOT:e9
1491 HDISPEND:b3
1492 HBLNKS:b3
1493 HBLNKE:ed
1494 HSYNCS:be
1495 HSYNCE:d1
1496 VTOT:3a2
1497 VDISPEND:383
1498 VBLNKS:383
1499 VBLNKE:3a3
1500 VSYNCS:385
1501 VSYNCE:388
1502CRTC2: sync polarity: H:pos V:pos , MISC reg readback: $0b
1503ACC_DMA: timer numerator $000014c8, denominator $00000271
1504ACC_DMA: command buffer is at adress $0x93ff8000
1505SET_DPMS_MODE: $00000001
1506CRTC: setting DPMS: display on, hsync enabled, vsync enabled
1507CRTC2: setting DPMS: display on, hsync enabled, vsync enabled
1508INIT: RAM access OK.
1509SETMODE: booted since 302061.504000 mS
1510Overlay: Not exporting hook B_OVERLAY_COUNT.
1511Overlay: Not exporting hook B_OVERLAY_SUPPORTED_SPACES.
1512Overlay: Not exporting hook B_OVERLAY_SUPPORTED_FEATURES.
1513Overlay: Not exporting hook B_ALLOCATE_OVERLAY_BUFFER.
1514Overlay: Not exporting hook B_RELEASE_OVERLAY_BUFFER.
1515Overlay: Not exporting hook B_GET_OVERLAY_CONSTRAINTS.
1516Overlay: Not exporting hook B_ALLOCATE_OVERLAY.
1517Overlay: Not exporting hook B_RELEASE_OVERLAY.
1518Overlay: Not exporting hook B_CONFIGURE_OVERLAY.
1519GET_EDID_INFO: returning info
1520GET_EDID_INFO: returning info
1521GET_EDID_INFO: returning info
1522GET_EDID_INFO: returning info
1523Haiku: tunnel access target=swap, command=get, value=0
1524Haiku: tunnel access target=usepanel, command=get, value=0
1525Haiku: tunnel access target=tvstandard, command=get, value=0
1526GET_EDID_INFO: returning info
1527GET_ACCELERANT_DEVICE_INFO: returning info
1528Haiku: tunnel access target=swap, command=get, value=0
1529Haiku: tunnel access target=usepanel, command=get, value=0
1530Haiku: tunnel access target=tvstandard, command=get, value=0
1531Haiku: tunnel access target=swap, command=get, value=0
1532Haiku: tunnel access target=usepanel, command=get, value=0
1533Haiku: tunnel access target=tvstandard, command=get, value=0
1534Haiku: tunnel access target=swap, command=get, value=0
1535Haiku: tunnel access target=usepanel, command=get, value=0
1536Haiku: tunnel access target=tvstandard, command=get, value=0
1537Haiku: tunnel access target=swap, command=get, value=0
1538Haiku: tunnel access target=usepanel, command=get, value=0
1539Haiku: tunnel access target=tvstandard, command=get, value=0
1540Haiku: tunnel access target=swap, command=get, value=0
1541Haiku: tunnel access target=usepanel, command=get, value=0
1542Haiku: tunnel access target=tvstandard, command=get, value=0
1543CRTC: disabling cursor
1544CRTC2: disabling cursor