| 1 | CPU_VGACNTRL (0x00041000): 0x80000000
|
|---|
| 2 | Gen5 disabled
|
|---|
| 3 | PORT_DBG (0x00042308): 0x00000000
|
|---|
| 4 | Gen5 HW DRRS off
|
|---|
| 5 | DIGITAL_PORT_HOTPLUG_CNTRL (0x00044030): 0x00000010
|
|---|
| 6 | FDI_PLL_BIOS_0 (0x00046000): 0xffffffff
|
|---|
| 7 | FDI_PLL_BIOS_1 (0x00046004): 0xffffffff
|
|---|
| 8 | FDI_PLL_BIOS_2 (0x00046008): 0xffffffff
|
|---|
| 9 | DISPLAY_PORT_PLL_BIOS_0 (0x0004600c): 0xffffffff
|
|---|
| 10 | DISPLAY_PORT_PLL_BIOS_1 (0x00046010): 0xffffffff
|
|---|
| 11 | DISPLAY_PORT_PLL_BIOS_2 (0x00046014): 0xffffffff
|
|---|
| 12 | FDI_PLL_FREQ_CTL (0x00046030): 0xffffffff
|
|---|
| 13 | BLC_PWM_CPU_CTL2 (0x00048250): 0x80000000
|
|---|
| 14 | Gen5 enable 1, pipe A, blinking 0, granularity 128
|
|---|
| 15 | Gen7.5 enable 1, pipe A, blinking 0, granularity 128
|
|---|
| 16 | BLC_PWM_CPU_CTL (0x00048254): 0x0000007e
|
|---|
| 17 | Gen5 cycle 126, freq 0
|
|---|
| 18 | Gen7.5 cycle 126, freq 0
|
|---|
| 19 | HTOTAL_A (0x00060000): 0x06df063f
|
|---|
| 20 | Gen2 1600 active, 1760 total
|
|---|
| 21 | Gen5 1600 active, 1760 total
|
|---|
| 22 | Gen7.5 1600 active, 1760 total
|
|---|
| 23 | HBLANK_A (0x00060004): 0x06df063f
|
|---|
| 24 | Gen2 1600 start, 1760 end
|
|---|
| 25 | Gen5 1600 start, 1760 end
|
|---|
| 26 | Gen7.5 1600 start, 1760 end
|
|---|
| 27 | HSYNC_A (0x00060008): 0x068f066f
|
|---|
| 28 | Gen2 1648 start, 1680 end
|
|---|
| 29 | Gen5 1648 start, 1680 end
|
|---|
| 30 | Gen7.5 1648 start, 1680 end
|
|---|
| 31 | VTOTAL_A (0x0006000c): 0x039d0383
|
|---|
| 32 | Gen2 900 active, 926 total
|
|---|
| 33 | Gen5 900 active, 926 total
|
|---|
| 34 | Gen7.5 900 active, 926 total
|
|---|
| 35 | VBLANK_A (0x00060010): 0x039d0383
|
|---|
| 36 | Gen2 900 start, 926 end
|
|---|
| 37 | Gen5 900 start, 926 end
|
|---|
| 38 | Gen7.5 900 start, 926 end
|
|---|
| 39 | VSYNC_A (0x00060014): 0x038b0386
|
|---|
| 40 | Gen2 903 start, 908 end
|
|---|
| 41 | Gen5 903 start, 908 end
|
|---|
| 42 | Gen7.5 903 start, 908 end
|
|---|
| 43 | PIPEASRC (0x0006001c): 0x063f0383
|
|---|
| 44 | Gen2 1600, 900
|
|---|
| 45 | Gen5 1600, 900
|
|---|
| 46 | Gen7.5 1600, 900
|
|---|
| 47 | VSYNCSHIFT_A (0x00060028): 0x00000000
|
|---|
| 48 | PIPEA_DATA_M1 (0x00060030): 0x7e34263a
|
|---|
| 49 | Gen5 TU 64, val 0x34263a 3417658
|
|---|
| 50 | Gen7.5 TU 64, val 0x34263a 3417658
|
|---|
| 51 | PIPEA_DATA_N1 (0x00060034): 0x00400000
|
|---|
| 52 | Gen5 val 0x400000 4194304
|
|---|
| 53 | Gen7.5 val 0x400000 4194304
|
|---|
| 54 | PIPEA_DATA_M2 (0x00060038): 0x00000000
|
|---|
| 55 | Gen5 TU 1, val 0x0 0
|
|---|
| 56 | PIPEA_DATA_N2 (0x0006003c): 0x00000000
|
|---|
| 57 | Gen5 val 0x0 0
|
|---|
| 58 | PIPEA_LINK_M1 (0x00060040): 0x0002e5ad
|
|---|
| 59 | Gen5 val 0x2e5ad 189869
|
|---|
| 60 | Gen7.5 val 0x2e5ad 189869
|
|---|
| 61 | PIPEA_LINK_N1 (0x00060044): 0x00080000
|
|---|
| 62 | Gen5 val 0x80000 524288
|
|---|
| 63 | Gen7.5 val 0x80000 524288
|
|---|
| 64 | PIPEA_LINK_M2 (0x00060048): 0x00000000
|
|---|
| 65 | Gen5 val 0x0 0
|
|---|
| 66 | PIPEA_LINK_N2 (0x0006004c): 0x00000000
|
|---|
| 67 | Gen5 val 0x0 0
|
|---|
| 68 | FDI_TXA_CTL (0x00060100): 0x00040000
|
|---|
| 69 | Gen5 disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable
|
|---|
| 70 | HTOTAL_B (0x00061000): 0x00000000
|
|---|
| 71 | Gen2 1 active, 1 total
|
|---|
| 72 | Gen5 1 active, 1 total
|
|---|
| 73 | Gen7.5 1 active, 1 total
|
|---|
| 74 | HBLANK_B (0x00061004): 0x00000000
|
|---|
| 75 | Gen2 1 start, 1 end
|
|---|
| 76 | Gen5 1 start, 1 end
|
|---|
| 77 | Gen7.5 1 start, 1 end
|
|---|
| 78 | HSYNC_B (0x00061008): 0x00000000
|
|---|
| 79 | Gen2 1 start, 1 end
|
|---|
| 80 | Gen5 1 start, 1 end
|
|---|
| 81 | Gen7.5 1 start, 1 end
|
|---|
| 82 | VTOTAL_B (0x0006100c): 0x00000000
|
|---|
| 83 | Gen2 1 active, 1 total
|
|---|
| 84 | Gen5 1 active, 1 total
|
|---|
| 85 | Gen7.5 1 active, 1 total
|
|---|
| 86 | VBLANK_B (0x00061010): 0x00000000
|
|---|
| 87 | Gen2 1 start, 1 end
|
|---|
| 88 | Gen5 1 start, 1 end
|
|---|
| 89 | Gen7.5 1 start, 1 end
|
|---|
| 90 | VSYNC_B (0x00061014): 0x00000000
|
|---|
| 91 | Gen2 1 start, 1 end
|
|---|
| 92 | Gen5 1 start, 1 end
|
|---|
| 93 | Gen7.5 1 start, 1 end
|
|---|
| 94 | PIPEBSRC (0x0006101c): 0x00000000
|
|---|
| 95 | Gen2 1, 1
|
|---|
| 96 | Gen5 1, 1
|
|---|
| 97 | Gen7.5 1, 1
|
|---|
| 98 | VSYNCSHIFT_B (0x00061028): 0x00000000
|
|---|
| 99 | PIPEB_DATA_M1 (0x00061030): 0x00000000
|
|---|
| 100 | Gen5 TU 1, val 0x0 0
|
|---|
| 101 | Gen7.5 TU 1, val 0x0 0
|
|---|
| 102 | PIPEB_DATA_N1 (0x00061034): 0x00000000
|
|---|
| 103 | Gen5 val 0x0 0
|
|---|
| 104 | Gen7.5 val 0x0 0
|
|---|
| 105 | PIPEB_DATA_M2 (0x00061038): 0x00000000
|
|---|
| 106 | Gen5 TU 1, val 0x0 0
|
|---|
| 107 | PIPEB_DATA_N2 (0x0006103c): 0x00000000
|
|---|
| 108 | Gen5 val 0x0 0
|
|---|
| 109 | PIPEB_LINK_M1 (0x00061040): 0x00000000
|
|---|
| 110 | Gen5 val 0x0 0
|
|---|
| 111 | Gen7.5 val 0x0 0
|
|---|
| 112 | PIPEB_LINK_N1 (0x00061044): 0x00000000
|
|---|
| 113 | Gen5 val 0x0 0
|
|---|
| 114 | Gen7.5 val 0x0 0
|
|---|
| 115 | PIPEB_LINK_M2 (0x00061048): 0x00000000
|
|---|
| 116 | Gen5 val 0x0 0
|
|---|
| 117 | PIPEB_LINK_N2 (0x0006104c): 0x00000000
|
|---|
| 118 | Gen5 val 0x0 0
|
|---|
| 119 | FDI_TXB_CTL (0x00061100): 0x00040000
|
|---|
| 120 | Gen2 disabled, pipe A, -hsync, -vsync
|
|---|
| 121 | Gen5 disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable
|
|---|
| 122 | HTOTAL_C (0x00062000): 0x00000000
|
|---|
| 123 | Gen5 1 active, 1 total
|
|---|
| 124 | Gen7.5 1 active, 1 total
|
|---|
| 125 | HBLANK_C (0x00062004): 0x00000000
|
|---|
| 126 | Gen5 1 start, 1 end
|
|---|
| 127 | Gen7.5 1 start, 1 end
|
|---|
| 128 | HSYNC_C (0x00062008): 0x00000000
|
|---|
| 129 | Gen5 1 start, 1 end
|
|---|
| 130 | Gen7.5 1 start, 1 end
|
|---|
| 131 | VTOTAL_C (0x0006200c): 0x00000000
|
|---|
| 132 | Gen5 1 active, 1 total
|
|---|
| 133 | Gen7.5 1 active, 1 total
|
|---|
| 134 | VBLANK_C (0x00062010): 0x00000000
|
|---|
| 135 | Gen5 1 start, 1 end
|
|---|
| 136 | Gen7.5 1 start, 1 end
|
|---|
| 137 | VSYNC_C (0x00062014): 0x00000000
|
|---|
| 138 | Gen5 1 start, 1 end
|
|---|
| 139 | Gen7.5 1 start, 1 end
|
|---|
| 140 | PIPECSRC (0x0006201c): 0x00000000
|
|---|
| 141 | Gen5 1, 1
|
|---|
| 142 | Gen7.5 1, 1
|
|---|
| 143 | VSYNCSHIFT_C (0x00062028): 0x00000000
|
|---|
| 144 | PIPEC_DATA_M1 (0x00062030): 0x00000000
|
|---|
| 145 | Gen5 TU 1, val 0x0 0
|
|---|
| 146 | Gen7.5 TU 1, val 0x0 0
|
|---|
| 147 | PIPEC_DATA_N1 (0x00062034): 0x00000000
|
|---|
| 148 | Gen5 val 0x0 0
|
|---|
| 149 | Gen7.5 val 0x0 0
|
|---|
| 150 | PIPEC_DATA_M2 (0x00062038): 0x00000000
|
|---|
| 151 | Gen5 TU 1, val 0x0 0
|
|---|
| 152 | PIPEC_DATA_N2 (0x0006203c): 0x00000000
|
|---|
| 153 | Gen5 val 0x0 0
|
|---|
| 154 | PIPEC_LINK_M1 (0x00062040): 0x00000000
|
|---|
| 155 | Gen5 val 0x0 0
|
|---|
| 156 | Gen7.5 val 0x0 0
|
|---|
| 157 | PIPEC_LINK_N1 (0x00062044): 0x00000000
|
|---|
| 158 | Gen5 val 0x0 0
|
|---|
| 159 | Gen7.5 val 0x0 0
|
|---|
| 160 | PIPEC_LINK_M2 (0x00062048): 0x00000000
|
|---|
| 161 | Gen5 val 0x0 0
|
|---|
| 162 | PIPEC_LINK_N2 (0x0006204c): 0x00000000
|
|---|
| 163 | Gen5 val 0x0 0
|
|---|
| 164 | FDI_TXC_CTL (0x00062100): 0x00000000
|
|---|
| 165 | Gen5 disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable
|
|---|
| 166 | CPU_eDP_A (0x00064000): 0xb0044004
|
|---|
| 167 | Gen7.5 enabled not reversed reserved not detected
|
|---|
| 168 | PFA_WIN_POS (0x00068070): 0x00000000
|
|---|
| 169 | Gen5 0, 0
|
|---|
| 170 | Gen7.5 0, 0
|
|---|
| 171 | PFA_WIN_SIZE (0x00068074): 0x00000000
|
|---|
| 172 | Gen5 0, 0
|
|---|
| 173 | Gen7.5 0, 0
|
|---|
| 174 | PFA_CTL_1 (0x00068080): 0x00000000
|
|---|
| 175 | Gen5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 176 | Gen7.5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 177 | PFA_CTL_2 (0x00068084): 0x00007e3e
|
|---|
| 178 | Gen5 vscale 0.986267
|
|---|
| 179 | PFA_CTL_3 (0x00068088): 0x00003f1f
|
|---|
| 180 | Gen5 vscale initial phase 0.493134
|
|---|
| 181 | PFA_CTL_4 (0x00068090): 0x00007ce0
|
|---|
| 182 | Gen5 hscale 0.975586
|
|---|
| 183 | PFB_WIN_POS (0x00068870): 0x00000000
|
|---|
| 184 | Gen5 0, 0
|
|---|
| 185 | Gen7.5 0, 0
|
|---|
| 186 | PFB_WIN_SIZE (0x00068874): 0x00000000
|
|---|
| 187 | Gen5 0, 0
|
|---|
| 188 | Gen7.5 0, 0
|
|---|
| 189 | PFB_CTL_1 (0x00068880): 0x00000000
|
|---|
| 190 | Gen5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 191 | Gen7.5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 192 | PFB_CTL_2 (0x00068884): 0x00000000
|
|---|
| 193 | Gen5 vscale 0.000000
|
|---|
| 194 | PFB_CTL_3 (0x00068888): 0x00000000
|
|---|
| 195 | Gen5 vscale initial phase 0.000000
|
|---|
| 196 | PFB_CTL_4 (0x00068890): 0x00000000
|
|---|
| 197 | Gen5 hscale 0.000000
|
|---|
| 198 | PFC_WIN_POS (0x00069070): 0x00000000
|
|---|
| 199 | Gen5 0, 0
|
|---|
| 200 | Gen7.5 0, 0
|
|---|
| 201 | PFC_WIN_SIZE (0x00069074): 0x00000000
|
|---|
| 202 | Gen5 0, 0
|
|---|
| 203 | Gen7.5 0, 0
|
|---|
| 204 | PFC_CTL_1 (0x00069080): 0x00000000
|
|---|
| 205 | Gen5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 206 | Gen7.5 disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
|
|---|
| 207 | PFC_CTL_2 (0x00069084): 0x00000000
|
|---|
| 208 | Gen5 vscale 0.000000
|
|---|
| 209 | PFC_CTL_3 (0x00069088): 0x00000000
|
|---|
| 210 | Gen5 vscale initial phase 0.000000
|
|---|
| 211 | PFC_CTL_4 (0x00069090): 0x00000000
|
|---|
| 212 | Gen5 hscale 0.000000
|
|---|
| 213 | PIPEACONF (0x00070008): 0xc0000050
|
|---|
| 214 | Gen2 enabled, active
|
|---|
| 215 | Gen5 enabled, active
|
|---|
| 216 | Gen7.5 enabled, active
|
|---|
| 217 | DSPACNTR (0x00070180): 0xd8004400
|
|---|
| 218 | Gen2 enabled, pipe A
|
|---|
| 219 | Gen5 enabled, pipe A
|
|---|
| 220 | Gen7.5 enabled, pipe A
|
|---|
| 221 | DSPABASE (0x00070184): 0x00000000
|
|---|
| 222 | DSPASTRIDE (0x00070188): 0x00001a00
|
|---|
| 223 | Gen2 6656 bytes
|
|---|
| 224 | Gen5 104
|
|---|
| 225 | Gen7.5 104
|
|---|
| 226 | DSPASURF (0x0007019c): 0x00b10000
|
|---|
| 227 | DSPATILEOFF (0x000701a4): 0x00000000
|
|---|
| 228 | Gen5 0, 0
|
|---|
| 229 | Gen7.5 0, 0
|
|---|
| 230 | PIPEBCONF (0x00071008): 0x00000000
|
|---|
| 231 | Gen2 disabled, inactive
|
|---|
| 232 | Gen5 disabled, inactive
|
|---|
| 233 | Gen7.5 disabled, inactive
|
|---|
| 234 | DSPBCNTR (0x00071180): 0x00004000
|
|---|
| 235 | Gen2 disabled, pipe A
|
|---|
| 236 | Gen5 disabled, pipe A
|
|---|
| 237 | Gen7.5 disabled, pipe A
|
|---|
| 238 | DSPBBASE (0x00071184): 0x00000000
|
|---|
| 239 | DSPBSTRIDE (0x00071188): 0x00000000
|
|---|
| 240 | Gen2 0 bytes
|
|---|
| 241 | Gen5 0
|
|---|
| 242 | Gen7.5 0
|
|---|
| 243 | DSPBSURF (0x0007119c): 0x00000000
|
|---|
| 244 | DSPBTILEOFF (0x000711a4): 0x00000000
|
|---|
| 245 | Gen5 0, 0
|
|---|
| 246 | Gen7.5 0, 0
|
|---|
| 247 | PIPECCONF (0x00072008): 0x00000000
|
|---|
| 248 | Gen5 disabled, inactive
|
|---|
| 249 | Gen7.5 disabled, inactive
|
|---|
| 250 | DSPCCNTR (0x00072180): 0x00000000
|
|---|
| 251 | Gen5 disabled, pipe A
|
|---|
| 252 | Gen7.5 disabled, pipe A
|
|---|
| 253 | DSPCBASE (0x00072184): 0x00000000
|
|---|
| 254 | DSPCSTRIDE (0x00072188): 0x00000000
|
|---|
| 255 | Gen5 0
|
|---|
| 256 | Gen7.5 0
|
|---|
| 257 | DSPCSURF (0x0007219c): 0x00000000
|
|---|
| 258 | DSPCTILEOFF (0x000721a4): 0x00000000
|
|---|
| 259 | Gen5 0, 0
|
|---|
| 260 | Gen7.5 0, 0
|
|---|
| 261 | PCH_DPLL_A (0x000c6014): 0x04800080
|
|---|
| 262 | Gen5 disable, sdvo high speed no, mode Non-LVDS, p2 Div 10, FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1
|
|---|
| 263 | PCH_DPLL_B (0x000c6018): 0x04800080
|
|---|
| 264 | Gen5 disable, sdvo high speed no, mode Non-LVDS, p2 Div 10, FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1
|
|---|
| 265 | PCH_FPA0 (0x000c6040): 0x00030d07
|
|---|
| 266 | Gen5 n = 3, m1 = 13, m2 = 7
|
|---|
| 267 | PCH_FPA1 (0x000c6044): 0x00030d07
|
|---|
| 268 | Gen5 n = 3, m1 = 13, m2 = 7
|
|---|
| 269 | PCH_FPB0 (0x000c6048): 0x00030d07
|
|---|
| 270 | Gen5 n = 3, m1 = 13, m2 = 7
|
|---|
| 271 | PCH_FPB1 (0x000c604c): 0x00030d07
|
|---|
| 272 | Gen5 n = 3, m1 = 13, m2 = 7
|
|---|
| 273 | PCH_DREF_CONTROL (0x000c6200): 0x00007400
|
|---|
| 274 | Gen5 cpu source nonspread, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable
|
|---|
| 275 | PCH_RAWCLK_FREQ (0x000c6204): 0x0000007d
|
|---|
| 276 | Gen5 FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125
|
|---|
| 277 | PCH_DPLL_TMR_CFG (0x000c6208): 0x0271186a
|
|---|
| 278 | PCH_SSC4_PARMS (0x000c6210): 0x01204860
|
|---|
| 279 | PCH_SSC4_AUX_PARMS (0x000c6214): 0x000029c5
|
|---|
| 280 | PCH_DPLL_ANALOG_CTL (0x000c6300): 0x00008000
|
|---|
| 281 | PCH_DPLL_SEL (0x000c7000): 0x00000000
|
|---|
| 282 | PCH_PP_STATUS (0x000c7200): 0x80000008
|
|---|
| 283 | Gen5 on, not ready, sequencing idle
|
|---|
| 284 | Gen7.5 on, not ready, sequencing idle
|
|---|
| 285 | PCH_PP_CONTROL (0x000c7204): 0xabcd0007
|
|---|
| 286 | Gen5 blacklight enabled, power down on reset, panel on
|
|---|
| 287 | Gen7.5 blacklight enabled, power down on reset, panel on
|
|---|
| 288 | PCH_PP_ON_DELAYS (0x000c7208): 0x47d00001
|
|---|
| 289 | PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001
|
|---|
| 290 | PCH_PP_DIVISOR (0x000c7210): 0x00186906
|
|---|
| 291 | BLC_PWM_PCH_CTL1 (0x000c8250): 0x80000000
|
|---|
| 292 | Gen5 enable 1, override 0, inverted polarity 0
|
|---|
| 293 | Gen7.5 enable 1, override 0, inverted polarity 0
|
|---|
| 294 | BLC_PWM_PCH_CTL2 (0x000c8254): 0x03d00000
|
|---|
| 295 | Gen5 freq 976, cycle 0
|
|---|
| 296 | Gen7.5 freq 976, cycle 0
|
|---|
| 297 | TRANS_HTOTAL_A (0x000e0000): 0x00000000
|
|---|
| 298 | Gen5 1 active, 1 total
|
|---|
| 299 | Gen7.5 1 active, 1 total
|
|---|
| 300 | TRANS_HBLANK_A (0x000e0004): 0x00000000
|
|---|
| 301 | Gen5 1 start, 1 end
|
|---|
| 302 | Gen7.5 1 start, 1 end
|
|---|
| 303 | TRANS_HSYNC_A (0x000e0008): 0x00000000
|
|---|
| 304 | Gen5 1 start, 1 end
|
|---|
| 305 | Gen7.5 1 start, 1 end
|
|---|
| 306 | TRANS_VTOTAL_A (0x000e000c): 0x00000000
|
|---|
| 307 | Gen5 1 active, 1 total
|
|---|
| 308 | Gen7.5 1 active, 1 total
|
|---|
| 309 | TRANS_VBLANK_A (0x000e0010): 0x00000000
|
|---|
| 310 | Gen5 1 start, 1 end
|
|---|
| 311 | Gen7.5 1 start, 1 end
|
|---|
| 312 | TRANS_VSYNC_A (0x000e0014): 0x00000000
|
|---|
| 313 | Gen5 1 start, 1 end
|
|---|
| 314 | Gen7.5 1 start, 1 end
|
|---|
| 315 | TRANS_VSYNCSHIFT_A (0x000e0028): 0x00000000
|
|---|
| 316 | TRANSA_DATA_M1 (0x000e0030): 0x00000000
|
|---|
| 317 | Gen5 TU 1, val 0x0 0
|
|---|
| 318 | TRANSA_DATA_N1 (0x000e0034): 0x00000000
|
|---|
| 319 | Gen5 val 0x0 0
|
|---|
| 320 | TRANSA_DATA_M2 (0x000e0038): 0x00000000
|
|---|
| 321 | Gen5 TU 1, val 0x0 0
|
|---|
| 322 | TRANSA_DATA_N2 (0x000e003c): 0x00000000
|
|---|
| 323 | Gen5 val 0x0 0
|
|---|
| 324 | TRANSA_DP_LINK_M1 (0x000e0040): 0x00000000
|
|---|
| 325 | Gen5 val 0x0 0
|
|---|
| 326 | TRANSA_DP_LINK_N1 (0x000e0044): 0x00000000
|
|---|
| 327 | Gen5 val 0x0 0
|
|---|
| 328 | TRANSA_DP_LINK_M2 (0x000e0048): 0x00000000
|
|---|
| 329 | Gen5 val 0x0 0
|
|---|
| 330 | TRANSA_DP_LINK_N2 (0x000e004c): 0x00000000
|
|---|
| 331 | Gen5 val 0x0 0
|
|---|
| 332 | TRANS_DP_CTL_A (0x000e0300): 0x60000418
|
|---|
| 333 | TRANS_HTOTAL_B (0x000e1000): 0x00000000
|
|---|
| 334 | Gen5 1 active, 1 total
|
|---|
| 335 | TRANS_HBLANK_B (0x000e1004): 0x00000000
|
|---|
| 336 | Gen5 1 start, 1 end
|
|---|
| 337 | TRANS_HSYNC_B (0x000e1008): 0x00000000
|
|---|
| 338 | Gen5 1 start, 1 end
|
|---|
| 339 | TRANS_VTOTAL_B (0x000e100c): 0x00000000
|
|---|
| 340 | Gen5 1 active, 1 total
|
|---|
| 341 | TRANS_VBLANK_B (0x000e1010): 0x00000000
|
|---|
| 342 | Gen5 1 start, 1 end
|
|---|
| 343 | TRANS_VSYNC_B (0x000e1014): 0x00000000
|
|---|
| 344 | Gen5 1 start, 1 end
|
|---|
| 345 | TRANS_VSYNCSHIFT_B (0x000e1028): 0x00000000
|
|---|
| 346 | TRANSB_DATA_M1 (0x000e1030): 0x00000000
|
|---|
| 347 | Gen5 TU 1, val 0x0 0
|
|---|
| 348 | TRANSB_DATA_N1 (0x000e1034): 0x00000000
|
|---|
| 349 | Gen5 val 0x0 0
|
|---|
| 350 | TRANSB_DATA_M2 (0x000e1038): 0x00000000
|
|---|
| 351 | Gen5 TU 1, val 0x0 0
|
|---|
| 352 | TRANSB_DATA_N2 (0x000e103c): 0x00000000
|
|---|
| 353 | Gen5 val 0x0 0
|
|---|
| 354 | TRANSB_DP_LINK_M1 (0x000e1040): 0x00000000
|
|---|
| 355 | Gen5 val 0x0 0
|
|---|
| 356 | TRANSB_DP_LINK_N1 (0x000e1044): 0x00000000
|
|---|
| 357 | Gen5 val 0x0 0
|
|---|
| 358 | TRANSB_DP_LINK_M2 (0x000e1048): 0x00000000
|
|---|
| 359 | Gen5 val 0x0 0
|
|---|
| 360 | TRANSB_DP_LINK_N2 (0x000e104c): 0x00000000
|
|---|
| 361 | Gen5 val 0x0 0
|
|---|
| 362 | PCH_ADPA (0x000e1100): 0x00f40000
|
|---|
| 363 | Gen5 disabled, pipe A, -hsync, -vsync
|
|---|
| 364 | HDMIB (0x000e1140): 0x00000018
|
|---|
| 365 | Gen5 disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected
|
|---|
| 366 | HDMIC (0x000e1150): 0x0000001c
|
|---|
| 367 | Gen5 disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected
|
|---|
| 368 | HDMID (0x000e1160): 0x00000018
|
|---|
| 369 | Gen5 disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected
|
|---|
| 370 | PCH_LVDS (0x000e1180): 0x00000000
|
|---|
| 371 | Gen5 disabled, pipe A, 18 bit, 1 channel
|
|---|
| 372 | TRANS_DP_CTL_B (0x000e1300): 0x60000018
|
|---|
| 373 | TRANS_HTOTAL_C (0x000e2000): 0x00000000
|
|---|
| 374 | Gen5 1 active, 1 total
|
|---|
| 375 | TRANS_HBLANK_C (0x000e2004): 0x00000000
|
|---|
| 376 | Gen5 1 start, 1 end
|
|---|
| 377 | TRANS_HSYNC_C (0x000e2008): 0x00000000
|
|---|
| 378 | Gen5 1 start, 1 end
|
|---|
| 379 | TRANS_VTOTAL_C (0x000e200c): 0x00000000
|
|---|
| 380 | Gen5 1 active, 1 total
|
|---|
| 381 | TRANS_VBLANK_C (0x000e2010): 0x00000000
|
|---|
| 382 | Gen5 1 start, 1 end
|
|---|
| 383 | TRANS_VSYNC_C (0x000e2014): 0x00000000
|
|---|
| 384 | Gen5 1 start, 1 end
|
|---|
| 385 | TRANS_VSYNCSHIFT_C (0x000e2028): 0x00000000
|
|---|
| 386 | TRANSC_DATA_M1 (0x000e2030): 0x00000000
|
|---|
| 387 | Gen5 TU 1, val 0x0 0
|
|---|
| 388 | TRANSC_DATA_N1 (0x000e2034): 0x00000000
|
|---|
| 389 | Gen5 val 0x0 0
|
|---|
| 390 | TRANSC_DATA_M2 (0x000e2038): 0x00000000
|
|---|
| 391 | Gen5 TU 1, val 0x0 0
|
|---|
| 392 | TRANSC_DATA_N2 (0x000e203c): 0x00000000
|
|---|
| 393 | Gen5 val 0x0 0
|
|---|
| 394 | TRANSC_DP_LINK_M1 (0x000e2040): 0x00000000
|
|---|
| 395 | Gen5 val 0x0 0
|
|---|
| 396 | TRANSC_DP_LINK_N1 (0x000e2044): 0x00000000
|
|---|
| 397 | Gen5 val 0x0 0
|
|---|
| 398 | TRANSC_DP_LINK_M2 (0x000e2048): 0x00000000
|
|---|
| 399 | Gen5 val 0x0 0
|
|---|
| 400 | TRANSC_DP_LINK_N2 (0x000e204c): 0x00000000
|
|---|
| 401 | Gen5 val 0x0 0
|
|---|
| 402 | TRANS_DP_CTL_C (0x000e2300): 0x60000018
|
|---|
| 403 | PCH_DP_B (0x000e4100): 0x00000000
|
|---|
| 404 | PCH_DP_C (0x000e4200): 0x00000004
|
|---|
| 405 | PCH_DP_D (0x000e4300): 0x00000000
|
|---|
| 406 | TRANSACONF (0x000f0008): 0x00000000
|
|---|
| 407 | Gen5 disable, inactive, progressive
|
|---|
| 408 | Gen7.5 disable, inactive, progressive
|
|---|
| 409 | FDI_RXA_CTL (0x000f000c): 0x00020040
|
|---|
| 410 | Gen5 disable, train pattern pattern_1, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk
|
|---|
| 411 | FDI_RXA_MISC (0x000f0010): 0x00000080
|
|---|
| 412 | Gen5 FDI Delay 128
|
|---|
| 413 | Gen7.5 FDI Delay 128
|
|---|
| 414 | FDI_RXA_IIR (0x000f0014): 0x00000000
|
|---|
| 415 | FDI_RXA_IMR (0x000f0018): 0x00000fff
|
|---|
| 416 | FDI_RXA_TUSIZE1 (0x000f0030): 0x7e000000
|
|---|
| 417 | FDI_RXA_TUSIZE2 (0x000f0038): 0x7e000000
|
|---|
| 418 | TRANSBCONF (0x000f1008): 0x00000000
|
|---|
| 419 | Gen5 disable, inactive, progressive
|
|---|
| 420 | FDI_RXB_CTL (0x000f100c): 0x00000040
|
|---|
| 421 | Gen5 disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk
|
|---|
| 422 | FDI_RXB_MISC (0x000f1010): 0x00000080
|
|---|
| 423 | Gen5 FDI Delay 128
|
|---|
| 424 | FDI_RXB_IIR (0x000f1014): 0x00000000
|
|---|
| 425 | FDI_RXB_IMR (0x000f1018): 0x00000fff
|
|---|
| 426 | FDI_RXB_TUSIZE1 (0x000f1030): 0x7e000000
|
|---|
| 427 | FDI_RXB_TUSIZE2 (0x000f1038): 0x7e000000
|
|---|
| 428 | TRANSCCONF (0x000f2008): 0x00000000
|
|---|
| 429 | Gen5 disable, inactive, progressive
|
|---|
| 430 | FDI_RXC_CTL (0x000f200c): 0x00000040
|
|---|
| 431 | Gen5 disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk
|
|---|
| 432 | FDI_RXC_MISC (0x000f2010): 0x00000080
|
|---|
| 433 | Gen5 FDI Delay 128
|
|---|
| 434 | FDI_RXC_TUSIZE1 (0x000f2030): 0x7e000000
|
|---|
| 435 | FDI_RXC_TUSIZE2 (0x000f2038): 0x7e000000
|
|---|
| 436 | FDI_PLL_CTL_1 (0x000fe000): 0x7e000000
|
|---|
| 437 | FDI_PLL_CTL_2 (0x000fe004): 0x7e000000
|
|---|
| 438 | GFX_MODE (0x00002520): 0x00002a00
|
|---|
